A trench gate IGBT preparation method based on trench side wall accurate oxidation processing, a trench gate IGBT and a power module

Abstract

The application discloses a trench gate IGBT preparation method based on trench sidewall accurate oxidation processing, a trench gate IGBT and a power module, and belongs to the technical field of trench gate IGBTs. The method comprises the following steps: first, trench is prepared; a first gate oxide layer is grown on the inner wall surface of the trench; a polycrystalline silicon layer is deposited in the trench and on the surface of the semiconductor substrate to completely fill the trench; the polycrystalline silicon layer on the sidewall of the trench is removed to expose the first gate oxide layer at the trench sidewall; the first gate oxide layer exposed to the trench sidewall is removed to re-expose the silicon surface of the trench sidewall; a second gate oxide layer is grown on the exposed silicon surface of the trench sidewall; the polycrystalline silicon layer reserved at the bottom of the trench is removed to expose the first gate oxide layer at the bottom of the trench; a conductive material is deposited in the trench to form a gate electrode; and subsequent processes are continued to obtain the trench gate IGBT. According to the application, the thick-bottom thin-wall gate oxide structure is realized through step-by-step oxidation, the thick bottom relieves the electric field concentration, and the thin wall ensures the channel mobility.

Description

Technical Field

[0001] This invention relates to a method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls, a trench gate IGBT and a power module, belonging to the field of trench gate IGBT technology. Background Technology

[0002] Trench gate IGBTs have become the mainstream device in modern power electronic devices because they eliminate the JFET structure of planar gate IGBTs. IGBTs are insulated-gate bipolar transistors, while JFETs are junction field-effect transistors. They offer higher channel density and lower on-state voltage drop. In the manufacturing process of trench gate IGBTs, the quality and thickness uniformity of the gate oxide layer directly determine the device's threshold voltage, channel mobility, and long-term reliability.

[0003] Traditional trench gate oxidation processes typically employ a single-stage thermal oxidation method. After etching to form the trench, the silicon wafer is directly subjected to high-temperature thermal oxidation, simultaneously growing a layer of silicon dioxide as a gate oxide layer on the inner walls of the trench, including the sidewalls and the bottom. However, this process has inherent drawbacks due to crystal orientation-dependent oxidation rate differences and uneven reactant concentration distribution within the deep and narrow trenches. Specifically, in single-crystal silicon, the oxidation rate of the sidewalls in a crystal orientation is usually faster than that at the bottom. This results in the gate oxide layer at the bottom of the trench often being thinner than that on the sidewalls. Furthermore, during device operation, the bottom of the trench, especially the bottom corner, is the region with the most concentrated electric field. The combination of a thinner bottom gate oxide layer and a high electric field makes the gate dielectric highly susceptible to breakdown at this location, severely limiting the device's breakdown voltage and long-term reliability.

[0004] To address this issue, existing technologies have explored various methods, such as ion implantation to introduce impurities like fluorine or nitrogen into the bottom of the trench to accelerate oxidation, or using multiple deposition and etching processes to adjust the thickness of different areas. However, these methods are often complex, lack sufficient control precision, or are prone to damaging the sidewall interface quality, thus affecting the channel carrier mobility. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls, as well as a trench gate IGBT and a power module, to solve the problems of insufficient control precision, easy damage to the sidewall interface quality, and impact on the channel carrier mobility in the prior art.

[0006] To achieve the above objectives, the present invention employs the following technical solution: In a first aspect, the present invention provides a method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls, comprising: A drift layer is formed on a semiconductor substrate with a silicon surface, and trenches are etched on the drift layer. A first gate oxide layer is grown on the inner wall surface of the trench through a first thermal oxidation process; A polysilicon layer is deposited in the trench and on the surface of the semiconductor substrate. After deposition, the polysilicon layer completely fills the trench. The polysilicon layer is etched back until the polysilicon layer on the trench sidewall is removed, leaving only the polysilicon layer filling the bottom of the trench, thus exposing the first gate oxide layer on the trench sidewall. Using the polysilicon layer retained at the bottom of the trench as a mask, the first gate oxide layer exposed on the trench sidewall is removed, so that the silicon surface of the trench sidewall is exposed again. A second gate oxide layer is grown on the exposed silicon surface of the trench sidewall through a second thermal oxidation process; Remove the polysilicon layer retained at the bottom of the trench to expose the first gate oxide layer at the bottom of the trench; Conductive material is deposited in the trench to form the gate electrode, and the standard IGBT fabrication process is then performed to obtain the trench gate IGBT.

[0007] Furthermore, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0008] Through the above-mentioned further technical solutions, the thicker first gate oxide layer effectively alleviates the electric field concentration phenomenon at the bottom of the trench, improves the breakdown voltage and gate reliability of the device; the thinner second gate oxide layer with excellent interface quality is conducive to forming a high-mobility conductive channel, reducing the on-resistance of the device, and improving the stability of the threshold voltage.

[0009] Furthermore, the thickness of the first gate oxide layer is 100~200nm, and the thickness of the second gate oxide layer is 50~100nm.

[0010] Furthermore, the back etching is a dry anisotropic etching process, and the thickness of the polysilicon layer at the bottom of the trench after back etching is 0.3~0.8μm.

[0011] Furthermore, the removal of the first gate oxide layer exposed on the trench sidewall, using the polysilicon layer retained at the bottom of the trench as a mask, includes: The polysilicon layer retained at the bottom of the trench is used as a protective layer, and the first gate oxide layer exposed on the sidewall of the trench is selectively removed by a wet etching process.

[0012] Furthermore, the removal of the polysilicon layer retained at the bottom of the trench is performed using a dry etching or wet etching process.

[0013] Furthermore, before the first gate oxide layer is grown on the inner wall surface of the trench through the first thermal oxidation process, the process further includes: Ion implantation is performed on the bottom of the trench, and the implanted ions are either nitrogen ions or oxygen ions.

[0014] Furthermore, the semiconductor substrate is a silicon substrate or a silicon carbide substrate.

[0015] In a second aspect, the present invention provides a trench gate IGBT, which is prepared by the trench gate IGBT preparation method based on precise oxidation processing of trench sidewalls as described in any one of the first aspects.

[0016] Thirdly, the present invention provides a power module fabricated based on the trench gate IGBT described in the second aspect.

[0017] Compared with the prior art, the beneficial effects achieved by the present invention are: This invention provides a method for fabricating a trench gate IGBT based on precise oxidation of the trench sidewalls, as well as a trench gate IGBT and a power module. The method achieves step-by-step oxidation through a first and second thermal oxidation process, and introduces a polysilicon layer as a mask, allowing the gate oxide layers at the bottom and sidewalls of the trench to form independently without interference. This breaks the limitation of traditional processes where the sidewall and bottom oxide layers must be grown simultaneously, improving the control precision of each oxide layer. By separately fabricating the first and second gate oxide layers, the thicknesses of the first and second gate oxide layers can be controlled separately, thereby optimizing the device's electric field distribution, improving the device's breakdown voltage and gate reliability, ensuring channel characteristics, and facilitating the formation of a high-mobility conductive channel. By first fabricating the polysilicon layer and then removing the polysilicon layer on the trench sidewalls, the first gate oxide layer at the trench sidewalls is exposed, avoiding damage to the sidewall interface quality. The entire fabrication method is fully compatible with existing silicon semiconductor process lines, requiring no additional special equipment and keeping costs under control. Attached Figure Description

[0018] Figure 1 This is a flowchart of a method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls, provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of the forward breakdown curve provided in the embodiment; Figure 3 This is a schematic diagram of the negative breakdown curve provided in the embodiment. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solution of the present invention more clearly, and should not be used to limit the scope of protection of the present invention.

[0020] Based on such Figure 1 The flowchart shown illustrates the following two embodiments of the present invention, which further illustrate the technical solution.

[0021] Example 1

[0022] This embodiment provides a method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewall, including the following steps one to eight.

[0023] Step 1: Provide a semiconductor substrate with a doping concentration of 1e14cm. -3 An N-type single-crystal silicon wafer is used. A drift layer is formed on the semiconductor substrate by chemical vapor deposition. In other embodiments, this chemical vapor deposition can be replaced by epitaxial growth. In this embodiment, the drift layer is specifically an N-drift layer. A hard mask layer, namely silicon dioxide, is deposited on the surface of the drift layer using low-pressure chemical vapor deposition. In other embodiments, it can be replaced by silicon nitride. Trenches with a depth of 5 μm and a width of 1 μm are etched in the drift layer by photolithography and dry etching.

[0024] Step 2: The intermediate product obtained in Step 1 is placed in a high-temperature oxidation furnace for the first thermal oxidation process. In an oxygen atmosphere (which can be replaced by a water vapor atmosphere in other embodiments), the temperature is controlled at 1000~1150℃. A first gate oxide layer is grown on the inner wall of the trench and the surface of the drift layer. The inner wall of the trench includes sidewalls and a bottom. In this embodiment, the thickness of the first gate oxide layer is controlled at 150nm.

[0025] Step 3: Deposit an undoped or in-situ doped polysilicon layer on the surface of the intermediate product obtained in Step 2 using low-pressure chemical vapor deposition. The polysilicon thickness should be sufficient to completely fill the entire trench; in this embodiment, the deposition thickness is 1.2 μm to ensure that there are no voids inside the trench.

[0026] Step 4: Using a plasma dry etching apparatus, perform anisotropic back etching on the polysilicon layer. The etching time is controlled by endpoint detection to precisely remove the polysilicon layer above the trench sidewalls and on the surface, retaining only a certain height of polysilicon layer at the bottom of the trench. In this embodiment, the thickness of the retained bottom polysilicon layer is 0.5 μm, and its top surface is located above the bottom corner of the trench, serving to protect the bottom first gate oxide layer.

[0027] Step 5: Using a wet etching process, the intermediate product obtained in Step 4 is immersed in a diluted hydrofluoric acid solution, specifically a hydrofluoric acid solution diluted at a water:hydrofluoric acid volume ratio of 100:1. Due to the protection of the polycrystalline silicon layer at the bottom, the first gate oxide layer at the bottom will not be etched; while the first gate oxide layer exposed on the trench sidewall is completely removed, exposing the single-crystal silicon surface.

[0028] Step Six: The intermediate product obtained in Step Five is placed in an oxidation furnace for a second thermal oxidation process. The oxidation temperature is slightly lower than the first thermal oxidation process, controlled at 900~1050℃, to grow a high-quality second gate oxide layer on the exposed silicon surface of the trench sidewalls. Since the bottom of the trench is covered by the polysilicon layer and the first gate oxide layer, the bottom silicon cannot come into contact with the oxidation atmosphere; therefore, no oxide layer is grown at the bottom in this step. In this embodiment, the thickness of the second gate oxide layer is controlled at 80nm.

[0029] Step 7: Using a dry etching process, completely remove the remaining polysilicon layer at the bottom of the trench, exposing the first gate oxide layer. In other embodiments, this step can be replaced by a wet etching process using a TMAH solution. At this point, a composite gate dielectric structure with a thick bottom and thin walls is formed within the trench.

[0030] Step 8: Deposit another layer of conductive polysilicon using low-pressure chemical vapor deposition (LPCVD) and perform back etching. In other embodiments, this back etching can be replaced by chemical mechanical polishing (CMP) to form a gate electrode that fills the trench. Subsequently, continue with the standard IGBT process flow, such as forming the P-body region, N+ source region, dielectric layer, contact vias, and metal electrodes, to obtain the trench gate IGBT.

[0031] Example 2

[0032] The difference between this embodiment and Embodiment 1 is that a bottom ion implantation process is added before the first thermal oxidation process in step two. Specifically, after the trench is formed, nitrogen ions are implanted into the bottom of the trench at a vertical angle of 0 degrees or a small angle, with an implantation dose of 1e15cm. -2 The implantation energy is 30keV. This implantation step can significantly promote the oxidation rate of silicon at the bottom of the trench during subsequent thermal oxidation, allowing the thickness of the first gate oxide layer grown in step two to be further increased to over 200nm, thereby achieving stronger bottom withstand voltage capability. This step does not affect the subsequent oxidation of the sidewalls, enabling further precise control of the bottom thickness.

[0033] The performance of the trench gate IGBTs prepared in Examples 1 and 2 was tested below. A Keysight B1505 curve tracer was used for testing, and the gate oxide breakdown voltage test was employed. Test conditions: The emitter and collector of the trench gate IGBT were shorted and grounded. A positive or negative scanning voltage was applied to the gate, starting from 0V and increasing at a rate of 1V / step or -1V / step, until the gate leakage current exceeded 0.1μA. The voltage value at this point was recorded as the positive or negative breakdown voltage of the gate. The positive breakdown curve is shown below. Figure 2 As shown, the negative breakdown curve of the test is as follows: Figure 3 As shown.

[0034] The data shows that increasing the thickness of the bottom second gate oxide layer in Example 2 significantly improves the gate negative breakdown voltage.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

[0036] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any variations and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the invention, fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for fabricating trench gate IGBTs based on precise oxidation processing of trench sidewalls, characterized in that, include: A drift layer is formed on a semiconductor substrate with a silicon surface, and trenches are etched on the drift layer. A first gate oxide layer is grown on the inner wall surface of the trench through a first thermal oxidation process; A polysilicon layer is deposited in the trench and on the surface of the semiconductor substrate. After deposition, the polysilicon layer completely fills the trench. The polysilicon layer is etched back until the polysilicon layer on the trench sidewall is removed, leaving only the polysilicon layer filling the bottom of the trench, thus exposing the first gate oxide layer on the trench sidewall. Using the polysilicon layer retained at the bottom of the trench as a mask, the first gate oxide layer exposed on the trench sidewall is removed, so that the silicon surface of the trench sidewall is exposed again. A second gate oxide layer is grown on the exposed silicon surface of the trench sidewall through a second thermal oxidation process; Remove the polysilicon layer retained at the bottom of the trench to expose the first gate oxide layer at the bottom of the trench; Conductive material is deposited in the trench to form the gate electrode, and the standard IGBT fabrication process is then performed to obtain the trench gate IGBT.

2. The method for fabricating trench gate IGBTs based on precise oxidation processing of trench sidewalls according to claim 1, characterized in that, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

3. The method for fabricating trench gate IGBTs based on precise oxidation processing of trench sidewalls according to claim 1, characterized in that, The thickness of the first gate oxide layer is 100~200nm, and the thickness of the second gate oxide layer is 50~100nm.

4. The method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls according to claim 1, characterized in that, The back etching is a dry anisotropic etching process, and the thickness of the polysilicon layer at the bottom of the trench after back etching is 0.3~0.8μm.

5. The method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls according to claim 1, characterized in that, The removal of the first gate oxide layer exposed on the trench sidewall, using the polysilicon layer retained at the bottom of the trench as a mask, includes: The polysilicon layer retained at the bottom of the trench is used as a protective layer, and the first gate oxide layer exposed on the sidewall of the trench is selectively removed by a wet etching process.

6. The method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls according to claim 1, characterized in that, The removal of the polysilicon layer retained at the bottom of the trench is performed using either dry etching or wet etching processes.

7. The method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls according to claim 1, characterized in that, Before the first gate oxide layer is grown on the inner wall surface of the trench through the first thermal oxidation process, the process further includes: Ion implantation is performed on the bottom of the trench, and the implanted ions are either nitrogen ions or oxygen ions.

8. The method for fabricating a trench gate IGBT based on precise oxidation processing of the trench sidewalls according to claim 1, characterized in that, The semiconductor substrate is a silicon substrate or a silicon carbide substrate.

9. A trench gate IGBT, characterized in that, The trench gate IGBT is prepared using the method described in any one of claims 1 to 8, which is based on precise oxidation processing of the trench sidewalls.

10. A power module, characterized in that, It is prepared based on the trench gate IGBT according to claim 9.

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