Method for manufacturing semiconductor structure and mos transistor
Patent Information
- Application Number
- CN202510516944.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2026-10-27
AI Technical Summary
在浅沟道隔离结构与有源区交界处，器件往往存在一定的形貌差异，这种局部形貌上的不规则性会导致后续离子注入时离子在有源区分布不均匀，从而影响MOS管的性能
[0022]以栅极结构为掩模，对有源区进行源极和漏极的离子注入，形成源极区域和漏极区域；
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Figure CN122995172A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for fabricating a semiconductor structure and a MOS transistor. Background Technology
[0002] In the manufacturing process of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), shallow channel isolation structures are often used to define the active region. At the boundary between the shallow channel isolation structure and the active region, there are often certain morphological differences in the device. This local morphological irregularity can lead to uneven ion distribution in the active region during subsequent ion implantation, thus affecting the performance of the MOSFET. Summary of the Invention
[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for fabricating a semiconductor structure and a MOS transistor, which can reduce the protrusion at the interface between the isolation structure and the substrate, and can mask the small surface morphology undulations in the active region, making the dose and angle distribution of ion implantation more uniform, thereby improving the performance of the MOS transistor.
[0004] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:
[0005] A first oxide layer and a mask layer are sequentially formed on the first side of the substrate;
[0006] An isolation structure is formed on the first side of the substrate using photolithography and deposition processes based on the first oxide layer mask layer. The upper surface of the isolation structure is higher than the upper surface of the first oxide layer, and the sidewalls of the isolation structure extend along the first direction at the junction of the isolation structure and the substrate.
[0007] Wet etching is used to etch both the first oxide layer and the extension simultaneously;
[0008] After wet etching, a second oxide layer is formed on the first side of the substrate, and the upper surface of the second oxide layer is lower than the upper surface of the isolation structure.
[0009] Trap ion implantation is performed on the side of the second oxide layer away from the substrate.
[0010] According to the semiconductor structure fabrication method of this application, wet etching is isotropic. While removing the first oxide layer, it simultaneously etches the local protruding areas at the edge of the isolation structure, thereby reducing the protrusion at the junction of the isolation structure and the substrate. After wet etching, a second oxide layer is formed on the substrate surface, which can reduce the morphological height difference at the junction of the isolation structure and the substrate, and can also cover up the small surface morphological undulations of the substrate, making the dose and angle distribution of ion implantation more uniform, thereby improving the performance of the MOS transistor.
[0011] According to one embodiment of this application, during the process of simultaneously etching the first oxide layer and the extension using wet etching, the etching solution is either a hydrogen fluoride solution or a buffered silicon oxide etching solution.
[0012] According to one embodiment of this application, after simultaneously etching the first oxide layer and the extension using wet etching, the method further includes:
[0013] The extension was wet-etched using hydrogen fluoride gas.
[0014] According to one embodiment of this application, the second oxide layer is formed by a thermal oxidation process or a chemical vapor deposition process.
[0015] According to one embodiment of this application, the thickness of the second oxide layer is 20 angstroms to 100 angstroms.
[0016] According to one embodiment of this application, the absolute value of the difference between the height difference between the upper surface of the isolation structure and the upper surface of the second oxide layer and the initial height difference is less than a preset threshold, where the initial height difference is the height difference between the upper surface of the isolation structure and the upper surface of the first oxide layer.
[0017] According to one embodiment of this application, during the trap region ion implantation process on the side of the second oxide layer away from the substrate, the implanted ions are of the type N-type doped ions or P-type doped ions.
[0018] According to one embodiment of this application, after performing trap ion implantation into the substrate from the side of the second oxide layer away from the substrate, the method further includes:
[0019] Rapid thermal annealing is performed on the device after ion implantation in the trap region.
[0020] According to one embodiment of this application, after performing trap ion implantation into the substrate on the side of the second oxide layer away from the substrate, the method further includes:
[0021] A gate structure is formed on the second oxide layer;
[0022] Using the gate structure as a mask, ion implantation is performed on the active region to form the source and drain regions.
[0023] Metallization layers are deposited on the surfaces of the source and drain regions, and interconnection structures of the source, drain, and gate are formed by patterning.
[0024] A passivation layer is formed on the surface of the interconnect structure, and the device is then packaged.
[0025] Secondly, this application provides a MOSFET, which is manufactured according to the aforementioned method.
[0026] According to the MOS transistor of this application, wet etching is isotropic. While removing the first oxide layer, it simultaneously etches the local protruding areas at the edge of the isolation structure, thereby reducing the protrusion at the junction of the isolation structure and the substrate. After wet etching, a second oxide layer is formed on the substrate surface, which can reduce the morphological height difference at the junction of the isolation structure and the substrate, and can also cover up the small surface morphological undulations of the substrate, making the dose and angle distribution of ion implantation more uniform, thereby improving the performance of the MOS transistor.
[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0028] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0029] Figure 1 This is one of the schematic diagrams illustrating the fabrication process of forming an isolation structure in related technologies;
[0030] Figure 2 This is the second schematic diagram of the process of forming an isolation structure in related technologies;
[0031] Figure 3 This is the third schematic diagram of the process of forming an isolation structure in related technologies;
[0032] Figure 4 This is the third schematic diagram of the process of forming an isolation structure in related technologies;
[0033] Figure 5 This is a cross-sectional schematic diagram of the interface between the isolation structure and the substrate in related technologies;
[0034] Figure 6 This is a flowchart of a method for fabricating a semiconductor structure provided in an embodiment of this application;
[0035] Figure 7 This is one of the staged structural diagrams of a semiconductor structure fabricated using the fabrication method provided in this application embodiment;
[0036] Figure 8This is a second schematic diagram of the staged structure of a semiconductor structure fabricated using the fabrication method provided in the embodiments of this application;
[0037] Figure 9 This is a cross-sectional schematic diagram of the interface between the isolation structure and the substrate provided in the embodiments of this application.
[0038] Figure label:
[0039] Substrate 10, mask layer 20, silicon oxide layer 21, silicon nitride layer 22, TEOS layer 30, photoresist layer 40, isolation region 50, isolation structure 60, first oxide layer 70, second oxide layer 80. Detailed Implementation
[0040] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0041] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled at" or "connected at" two nodes, it can be directly coupled to or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.
[0042] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0043] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0044] Reference Figures 1 to 4 , Figures 1 to 4 The fabrication process of forming the isolation structure 60 in the related technology is shown. In the manufacturing process of MOSFETs, isolation technology is often used to define the active region. The isolation process can be summarized as follows: First, a silicon oxide layer 21, a silicon nitride layer 22, a TEOS layer 30 (tetraethyl orthosilicate), and a photoresist layer 40 are sequentially deposited on a silicon substrate 10, and the photoresist pattern is prepared to form... Figure 1 The structure shown is then formed by removing part of the silicon oxide layer 21 and silicon nitride layer 22, and removing the TEOS layer 30 and photoresist layer 40, through photolithography and reactive ion etching. Figure 2 The structure is shown. The trench sidewalls are then thermally oxidized, and the trench is filled using chemical vapor deposition, typically with silica as the filler material, to form isolation zone 50. Figure 3 The structure shown is as follows. After filling, the silica filling in the trenches is planarized using a chemical mechanical polishing process, and the silicon nitride layer 22 is removed to form... Figure 4 The structure shown.
[0045] Reference Figure 5 , Figure 5 A cross-section of the interface between the isolation structure 60 and the substrate in the related art is shown. Due to the inherent characteristics of the etching process, the sidewalls at the interface between the isolation structure 60 and the substrate have an inclination angle, resulting in local protrusions at the edges of the isolation structure 60 (such as...). Figure 5 As shown in region A, this creates a geometric obstruction in the ion implantation path. This local morphological irregularity leads to uneven ion distribution in the active region during subsequent ion implantation, affecting the uniformity of the MOS transistor threshold voltage.
[0046] Reference Figures 2 to 4 as well as Figures 6 to 8 . Figures 2 to 4 The fabrication process of the isolation structure is shown. Figure 6 The flowchart of the method for fabricating the semiconductor structure provided in the embodiments of this application is shown. Figure 7 and Figure 8The staged structure for fabricating the semiconductor structure provided in the embodiments of this application is shown. One embodiment of this application proposes a method for fabricating a semiconductor structure, including steps 10, 20, 30, and 40.
[0047] Step 10: A first oxide layer 70 and a mask layer 20 are sequentially formed on the first side of the substrate 10;
[0048] Step 20: Based on the first oxide layer 70 and the mask layer 20, an isolation structure 60 is formed on the first side of the substrate 10 by photolithography and deposition processes. The upper surface of the isolation structure 60 is higher than the upper surface of the first oxide layer 70, and the sidewall of the isolation structure 60 extends along the first direction at the junction of the isolation structure 60 and the substrate 10.
[0049] Step 30: Wet etching is used to simultaneously etch the first oxide layer 70 and the extension;
[0050] Step 40: After wet etching, a second oxide layer 80 is formed on the first side of the substrate, and the upper surface of the second oxide layer 80 is lower than the upper surface of the isolation structure 60.
[0051] Step 50: Perform trap region ion implantation into the substrate 10 on the side of the second oxide layer 80 away from the substrate 10.
[0052] Substrate 10, as the basic structure of the semiconductor structure, mainly provides rigid support for the entire semiconductor structure, ensuring that the device maintains structural integrity during subsequent high-temperature processes (such as oxidation and annealing) and long-term use. The material of substrate 10 can be selected according to the actual application requirements, and is not limited here. For example, substrate 10 can be a silicon substrate.
[0053] The mask layer 20 can be silicon nitride. Silicon nitride hardly reacts with common etchants at room temperature, and exhibits excellent corrosion resistance, especially in alkaline solutions, making it suitable as a mask material to protect the underlying substrate 10 during the etching process.
[0054] The first oxide layer 70 can be a thermally oxidized film grown in the early stages of the isolation process, primarily used to achieve electrical isolation. The first oxide layer 70 can be generated by thermal oxidation. The thickness of the first oxide layer 70 can be determined based on the actual application scenario and is not limited here. For example, the thickness of the first oxide layer 70 can be 20 angstroms to 100 angstroms.
[0055] The isolation structure 60 can be formed by etching and depositing silicon dioxide. The depth of the isolation structure 60 can be determined according to the actual application scenario and is not limited here. For example, the depth of the isolation structure 60 can be 200-500 nm. The top surface of the isolation structure 60 is usually higher than the surface of the first oxide layer 70, and the height difference between the two can be selected according to the actual application requirements and is not limited here. For example, the height difference between the two can be 10-30 nm.
[0056] It is understandable that the first oxide layer 70 is mainly composed of silicon dioxide. Wet etching primarily utilizes the chemical reaction between the etching solution and the first oxide layer 70 without reacting with the substrate 10, thus corroding away the first oxide layer 70 to remove it. The etching solution should be able to chemically react with silicon dioxide to generate a gas or a soluble liquid; for example, the etching solution could be hydrofluoric acid. The substrate 10 can be immersed in the etching solution for etching, or the etching solution can be uniformly sprayed onto the surface of the substrate 10 through a nozzle to improve uniformity and etching rate.
[0057] The first direction refers to Figure 4 as well as Figures 7 to 8 The X direction in the diagram. The extension refers to the portion of the isolation structure 60 that forms a shield along the first direction above the substrate due to the inclination of its sidewalls (e.g., ...). Figure 5 (As shown in region A).
[0058] Reference Figure 4 and Figure 7 Due to its inherent isotropic etching characteristics, wet etching processes exhibit an approximately uniform etching rate across all three-dimensional directions during the removal of the first oxide layer 70, thus also etching the isolation structure 60. However, the isolation structure 60 is typically formed using a deposition process, while the first oxide layer 70 is usually generated using a thermal oxidation method. Due to the difference in fabrication processes, the density of the isolation structure 60 is lower than that of the first oxide layer 70. Therefore, the etching rate of the etching solution on the extension of the isolation structure 60 is greater than the etching rate on the first oxide layer 70, and the upper surface of the isolation structure 60 is higher than the upper surface of the first oxide layer 70, meaning that the first oxide layer 70 surrounds the root of the isolation structure 60 exposed on the substrate surface. During wet etching, the first oxide layer 70 acts as an etching barrier on the root of the isolation structure 60, reducing the etching rate of the etching solution on the sidewalls of the root of the isolation structure 60, thereby allowing the extension of the isolation structure 60 (such as...) to be etched. Figure 7 The reduced protrusion of region A' reduces geometric obstruction in the ion implantation path, thereby improving the uniformity of ion implantation.
[0059] During wet etching, the etching time and etching solution concentration can be adjusted to ensure complete removal of the first oxide layer 70 without over-etching the isolation structure 60. It should be noted that the degree of corrosion varies depending on the etching solution or etching method used; therefore, the etching time and etching solution concentration are not limited here.
[0060] After wet etching, the film can be rinsed immediately with deionized water, dried, and then baked in a vacuum drying oven to avoid residual liquid affecting the quality of subsequent films.
[0061] Reference Figure 8 , Figure 8 This diagram illustrates a phased structure of a semiconductor structure fabricated using the method provided in this application. After wet etching, a high-temperature thermal oxidation process is used to react the silicon surface with oxygen to form a dense second oxide layer 80, the main component of which is silicon dioxide. The second oxide layer 80 can reduce the height difference in morphology at the interface between the isolation structure 60 and the substrate 10, and can repair the surface damage to the substrate 10 caused by the aforementioned wet etching process, masking minor surface morphology undulations of the substrate 10. This results in a more uniform dose and angle distribution of ions implanted in the subsequent well region ion implantation step, thereby improving the performance of the semiconductor structure. Furthermore, the second oxide layer 80 can absorb some of the ion kinetic energy during the well region ion implantation step, reducing amorphization damage to the surface of the substrate 10.
[0062] The semiconductor structure proposed in this application may include a MOS transistor. Well region ion implantation of the active region on the side of the second oxide layer 80 away from the substrate 10 is primarily used to provide the required substrate 10 doping type for NMOS or PMOS transistors. For example, PMOS transistors are typically fabricated in N-wells, while NMOS transistors are fabricated in P-wells, ensuring proper channel formation. The implantation dose determines the carrier concentration in the well region, directly affecting the threshold voltage. The ion implantation concentration can be determined based on the actual application scenario and is not limited here.
[0063] According to the semiconductor structure fabrication method of this application, wet etching is isotropic. While removing the oxide layer on the surface of the substrate 10, it simultaneously etches the local protruding areas at the edge of the isolation structure 60, thereby reducing the protrusion at the junction of the isolation structure 60 and the substrate 10. After wet etching, a second oxide layer 80 is formed on the surface of the substrate 10, which can reduce the morphological height difference at the junction of the isolation structure 60 and the substrate 10, and can also cover up the small surface morphological undulations of the substrate 10, making the dose and angle distribution of ion implantation more uniform, thereby improving the performance of the semiconductor structure.
[0064] In some embodiments, during the process of simultaneously etching the first oxide layer 70 and the extension using wet etching, the etching solution is a hydrogen fluoride solution or a buffered silicon oxide etching solution.
[0065] Hydrofluoric acid is a highly corrosive acid that can react directly with silicon dioxide (first oxide layer 70). Hydrofluoric acid has a rapid etching rate on silicon dioxide, but an extremely low etching rate on the silicon substrate 10, making it suitable for precisely removing the oxide layer without damaging the silicon substrate.
[0066] The buffered silicon oxide etching solution is made by mixing hydrofluoric acid and ammonium fluoride in a certain ratio (such as 6:1 or 7:1). The addition of ammonium fluoride can buffer the acidity of hydrofluoric acid, making the etching rate more uniform. Compared with pure hydrofluoric acid, the surface after etching with buffered silicon oxide etching solution is smoother and reduces the generation of micro-defects.
[0067] Reference Figure 9 , Figure 9 A cross-section of the junction between the isolation structure 60 and the substrate 10 in an embodiment of this application is shown. In some embodiments, after simultaneously etching the first oxide layer 70 and the extension using wet etching, the method further includes: wet etching the extension using hydrogen fluoride gas.
[0068] Hydrogen fluoride gas refers to the gas formed after the hydrogen fluoride solution is atomized. The hydrogen fluoride gas is anisotropic; after the first oxide layer 70 is removed by wet etching, the hydrogen fluoride gas can be sprayed towards the extension. The hydrogen fluoride gas has high selectivity for silicon dioxide (isolation structure 60), hardly etching the silicon substrate 10, but further etching the extension to reduce its protrusion (e.g., ...). Figure 9 As shown in region A', this further reduces geometric obstruction in the ion implantation path, making the subsequently implanted ions more evenly distributed in the active region, thereby improving the uniformity and consistency of the threshold voltage of the MOS transistor.
[0069] In some embodiments, the second oxide layer 80 is formed by a thermal oxidation process or a chemical vapor deposition process.
[0070] In the case of thermal oxidation, the substrate 10 reacts chemically with the oxidant at high temperature to directly generate silicon dioxide, which can then serve as the second oxide layer 80. In the thermal oxidation process, the oxidation rate decreases exponentially with increasing film thickness, facilitating control of the second oxide layer 80. Furthermore, no external source material is required; the oxide layer is generated solely through the reaction of the substrate 10 with the gas, avoiding the introduction of metal contamination.
[0071] In the case of chemical vapor deposition (CVD), a silicon dioxide thin film is deposited on the surface of substrate 10 by a chemical reaction of precursor gases (such as SiH4 / O2, TEOS / O3, etc.). The silicon dioxide thin film can then serve as the second oxide layer 80. CVD offers a relatively fast deposition rate for silicon dioxide and allows for process temperatures as low as 300–400°C, reducing the risk of high-temperature damage.
[0072] In some embodiments, the thickness of the second oxide layer 80 is 20 angstroms to 100 angstroms.
[0073] The second oxide layer 80 can act as a barrier layer, absorbing some of the implantation energy during subsequent well ion implantation and reducing amorphization damage to the silicon substrate 10 surface. When the thickness of the second oxide layer 80 is between 20 Å and 50 Å, it minimizes the impact on the implantation depth while ensuring surface protection; when the thickness of the second oxide layer 80 is between 50 Å and 100 Å, it is suitable for deep well implantation and can provide stronger damage resistance.
[0074] The specific value of the second oxide layer thickness 80 can be determined according to the actual application scenario and is not limited here. For example, the thickness of the second oxide layer 80 can be 30 angstroms, 50 angstroms, or 70 angstroms, etc.
[0075] In some embodiments, the absolute value of the difference between the height difference between the upper surface of the isolation structure 60 and the upper surface of the second oxide layer 80 and the initial height difference is less than a preset threshold, where the initial height difference is the height difference between the upper surface of the isolation structure 60 and the upper surface of the first oxide layer 70.
[0076] The initial height difference refers to the height difference between the surface of the isolation structure 60 and the surface of the first oxide layer 70. During the wet etching process to optimize the morphology of the isolation structure 60, the second oxide layer 80 is removed, and the height of the isolation structure 60 is also reduced, thus changing the height difference between the surface of the isolation structure 60 and the surface of the active region. When forming the second oxide layer 80, the thickness of the second oxide layer 80 can be controlled by vias, ensuring that the absolute value of the difference between the height difference between the surface of the isolation structure 60 and the surface of the second oxide layer 80 and the initial height difference is less than a preset threshold.
[0077] It should be noted that the height difference between the upper surface of the isolation structure 60 and the upper surface of the second oxide layer 80 is preferably the same as the initial height difference. However, considering the possibility of errors in the actual fabrication process, a preset threshold is set. The absolute value of the difference between the height difference between the surface of the isolation structure 60 and the surface of the second oxide layer 80 and the initial height difference is less than the preset threshold. In other words, the absolute value of the difference between the height difference between the surface of the isolation structure 60 and the surface of the second oxide layer 80 and the initial height difference is equal within the allowable error range. The preset threshold can be determined according to the needs of the actual application scenario and is not limited here. For example, the preset threshold can be 2 angstroms or 3 angstroms, etc.
[0078] In some embodiments, during the process of well region ion implantation into the substrate 10 on the side of the second oxide layer 80 away from the substrate 10, the implanted ions are of the type N-type doped ions or P-type doped ions.
[0079] When performing well region ion implantation on substrate 10, the type of implanted ions can be selected according to the required type of MOS transistor and the type of substrate 10. For example, if a P-type MOS transistor needs to be fabricated on an N-type substrate 10, P-type dopant ions are implanted into the active region to form a P-well. When fabricating a P-type MOS transistor on a P-type substrate 10, N-type dopant ions must first be implanted to form an N-well, and then P-type dopant ions are implanted into the N-well to form the source and drain regions.
[0080] The process of fabricating an N-type MOS transistor can be referred to the previous example, and will not be repeated here.
[0081] In some embodiments, after well region ion implantation is performed on the side of the second oxide layer 80 away from the substrate 10, the method further includes: performing rapid thermal annealing on the device after well region ion implantation.
[0082] During well region ion implantation on substrate 10, the high-speed impact of ions on substrate 10 may generate structural defects. These defects may affect the long-term stability of the device. Therefore, rapid thermal annealing is required after well region ion implantation. Rapid thermal annealing is a high-temperature heating process primarily aimed at settling the implanted ions in substrate 10 and repairing damage caused by the implantation process. Through annealing, ions can diffuse better into substrate 10, forming a more uniform doped layer, thereby improving the electrical performance of the MOS device.
[0083] In some embodiments, after ion implantation of the trap region into the substrate 10 on the side of the second oxide layer 80 away from the substrate 10, the method further includes: forming a gate structure on the second oxide layer 80; using the gate structure as a mask, performing source and drain ion implantation on the active region to form a source region and a drain region; depositing a metallization layer on the surface of the source region and the drain region, and forming an interconnect structure of the source, drain and gate by patterning; forming a passivation layer on the surface of the interconnect structure, and performing device packaging.
[0084] The gate structure includes a gate dielectric layer and a gate electrode layer. A high dielectric constant dielectric material can be deposited on the surface of the second oxide layer 80 using atomic layer deposition technology to form the gate dielectric layer. Then, a metal gate material and a conductive metal layer are deposited using physical vapor deposition to form the gate electrode layer. Finally, the gate is patterned using photolithography and reactive ion etching processes to form a gate structure with the target channel length.
[0085] After ion implantation, the area on the surface of substrate 10 not covered by the isolation structure 60 is the active region. Using the gate as a self-aligned mask, ion implantation is performed on the exposed active region for both source and drain. This step forms an ultra-shallow junction source / drain region by controlling the implantation energy. After implantation, a rapid single-pass annealing process is required to activate impurities and repair lattice damage.
[0086] To achieve electrical connection between the device and external circuitry, a metallization layer needs to be deposited on the surface of the source and drain regions. First, contact holes are formed using photolithography and reactive ion etching processes, followed by the deposition of a diffusion barrier layer and a metal filler material. After filling the trenches with electroplating, global planarization is achieved using chemical mechanical polishing. Subsequently, vertical and horizontal interconnect structures for the source, drain, and gate are constructed through multilayer metal wiring and via interconnects.
[0087] To protect the device from environmental corrosion and mechanical damage, a passivation layer is deposited on the surface of the interconnect structure, and solder joint openings are formed through photolithography and reactive ion etching. Finally, the device is packaged through wafer dicing, back metallization, and plastic or ceramic encapsulation to form a complete MOSFET.
[0088] It should be noted that the aforementioned steps for processing the device after ion implantation in the trap region to form a MOS device are merely illustrative and not an exhaustive list of the present solution. Any modifications, equivalent substitutions, improvements, or variations made within the spirit and principles of this invention, as well as any other reasonable implementation mode, should be included within the scope of protection of this invention.
[0089] One embodiment of this application provides a MOS transistor, which is fabricated according to the aforementioned semiconductor structure preparation method.
[0090] The specific steps and principles of the semiconductor structure fabrication method can be referred to in the foregoing embodiments, and will not be repeated here.
[0091] According to the MOS transistor of this application, wet etching is isotropic. While removing the first oxide layer 70 on the surface of the substrate 10, it simultaneously etches the local protruding areas at the edge of the isolation structure 60, thereby reducing the protrusion at the junction of the isolation structure 60 and the substrate 10. After wet etching, a second oxide layer 80 is formed on the surface of the substrate 10, which can reduce the morphological height difference at the junction of the isolation structure 60 and the substrate 10, and can also cover up the small surface morphological undulations of the substrate 10, making the dose and angle distribution of ion implantation more uniform, thereby improving the performance of the MOS transistor.
[0092] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A first oxide layer and a mask layer are sequentially formed on the first side of the substrate; An isolation structure is formed on the first side of the substrate based on the first oxide layer and the mask layer through photolithography and deposition processes. The upper surface of the isolation structure is higher than the upper surface of the first oxide layer, and the sidewall of the isolation structure extends along the first direction at the junction of the isolation structure and the substrate. Wet etching is used to simultaneously etch the first oxide layer and the extension. After wet etching, a second oxide layer is formed on the first side of the substrate, and the upper surface of the second oxide layer is lower than the upper surface of the isolation structure. Trap ion implantation is performed on the side of the second oxide layer away from the substrate.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, During the process of simultaneously etching the first oxide layer and the extension using wet etching, the etching solution used is either a hydrogen fluoride solution or a buffered silicon oxide etching solution.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, After simultaneously etching the first oxide layer and the extension using wet etching, the method further includes: The extension is wet-etched using hydrogen fluoride gas.
4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The second oxide layer is formed by thermal oxidation or chemical vapor deposition.
5. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The thickness of the second oxide layer is 20 angstroms to 100 angstroms.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The absolute value of the difference between the height difference between the upper surface of the isolation structure and the upper surface of the second oxide layer and the initial height difference is less than a preset threshold. The initial height difference is the height difference between the upper surface of the isolation structure and the upper surface of the first oxide layer.
7. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, During the trap region ion implantation process on the side of the second oxide layer away from the substrate, the implanted ions are either N-type doped ions or P-type doped ions.
8. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, After performing trap ion implantation into the substrate on the side of the second oxide layer away from the substrate, the method further includes: Rapid thermal annealing is performed on the device after ion implantation in the trap region.
9. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, After performing trap ion implantation into the substrate on the side of the second oxide layer away from the substrate, the method further includes: A gate structure is formed on the second oxide layer; Using the gate structure as a mask, ion implantation is performed on the active region to form the source region and the drain region. Metallization layers are deposited on the surfaces of the source region and the drain region, and interconnection structures of the source, drain and gate are formed by patterning. A passivation layer is formed on the surface of the interconnect structure, and the device is then packaged.
10. A MOSFET, characterized in that, The MOS transistor is prepared by the method according to any one of claims 1-9.