Hemt device and method of manufacturing the same

Abstract

The application provides a HEMT device and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor structure comprising a stack structure, a cap layer, a source electrode and a drain electrode, wherein the stack structure comprises a channel layer and a barrier layer which are sequentially stacked, the cap layer is located on the upper surface of the barrier layer, and the source electrode and the drain electrode are respectively electrically connected with the stack structure and located at a preset distance on the opposite sides of the cap layer; pre-treating a preset region on the upper surface of the cap layer to form a surface reinforcement layer covering the preset region; forming a groove penetrating through the surface reinforcement layer and having a bottom surface in the cap layer; and forming a gate electrode on the upper surface of the surface reinforcement layer and filling the groove. The surface reinforcement layer is formed on the preset region on the upper surface of the cap layer, the groove penetrating through the surface reinforcement layer and having a bottom surface in the cap layer is formed, and the gate electrode forms a Schottky contact with the surface reinforcement layer and an ohmic contact with the cap layer at the bottom surface of the groove, so that the gate electrode leakage is reduced and the stability of the threshold value of the device is ensured.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a HEMT device and its fabrication method. Background Technology

[0002] Enhancement-mode HEMTs (High Electron Mobility Transistors) have attracted widespread attention in high-power devices due to their high electron mobility, high electron saturation velocity, and high breakdown voltage characteristics. Currently, enhancement-mode HEMTs mainly include Schottky P-GaN gate HEMTs, ohmic P-GaN gate HEMTs, and hybrid gate HEMTs. After prolonged operation, the potential of the P-GaN cap layer in Schottky P-GaN gate HEMTs fluctuates, causing threshold voltage drift, performance degradation, and severely impacting device stability and reliability. While ohmic P-GaN gate HEMTs avoid threshold voltage drift, they suffer from severe gate leakage, also limiting device reliability and stability. Hybrid gate HEMTs can reduce gate leakage and suppress threshold voltage drift, but their fabrication process is relatively complex.

[0003] Therefore, there is an urgent need to find a simple fabrication method for HEMT devices that can reduce gate leakage current while avoiding threshold voltage drift. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a HEMT device and its fabrication method, which solves the problem that in the prior art, HEMT devices are difficult to reduce gate leakage current and avoid threshold voltage drift through a simple process.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a HEMT device, comprising the following steps:

[0006] A semiconductor structure is provided, the semiconductor structure including a stacked structure, a cap layer, a source and a drain, the stacked structure including a channel layer and a barrier layer stacked sequentially, the cap layer being located on the upper surface of the barrier layer, the source and the drain being electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer;

[0007] A predetermined area on the upper surface of the cap layer is pre-treated to form a surface reinforcement layer covering the predetermined area;

[0008] A groove is formed that penetrates the surface reinforcement layer and has its bottom surface located in the cap layer;

[0009] A gate is formed on the upper surface of the surface reinforcement layer and fills the groove.

[0010] Optionally, the semiconductor structure further includes a substrate and a buffer layer stacked sequentially, with the channel layer located on the upper surface of the buffer layer.

[0011] Optionally, the source and the drain are located on the upper surface of the barrier layer and respectively form ohmic contacts with the barrier layer.

[0012] Optionally, the source and the drain are embedded in the stacked structure and respectively form ohmic contacts with the channel layer; or the source and the drain are respectively embedded in the barrier layer and respectively form ohmic contacts with the barrier layer.

[0013] Optionally, the method for pretreating the preset area includes surface oxygen pretreatment and surface nitrogen pretreatment.

[0014] Optionally, in the direction of the source and drain arrangement, the size of the gate is not greater than the size of the surface reinforcement layer.

[0015] Optionally, the contact type between the bottom surface of the gate filling the groove portion and the cap layer is an ohmic contact, and the contact type between the gate located on the surface of the surface reinforcement layer and the surface reinforcement layer is a Schottky contact.

[0016] Optionally, the semiconductor structure includes a passivation layer that covers the exposed upper surface of the stacked structure, the source electrode penetrates the passivation layer and is electrically connected to the stacked structure, and the drain electrode penetrates the passivation layer and is electrically connected to the stacked structure.

[0017] Optionally, before forming the surface reinforcement layer, the method further includes forming a gate contact hole that penetrates the passivation layer, wherein the bottom surface of the gate contact hole exposes the upper surface of the cap layer, and the size of the gate contact hole is smaller than the size of the cap layer.

[0018] The present invention also provides a HEMT device, comprising:

[0019] A semiconductor structure includes a stacked structure, a cap layer, a source, and a drain. The stacked structure includes a channel layer and a barrier layer stacked sequentially. The cap layer is located on the upper surface of the barrier layer. The source and the drain are electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer.

[0020] A surface reinforcement layer covers a predetermined area on the upper surface of the cap layer;

[0021] A groove extends through the surface reinforcement layer and its bottom surface is located within the cap layer;

[0022] The gate is located on the upper surface of the surface reinforcement layer and fills the groove.

[0023] As described above, the HEMT device and its fabrication method of the present invention form a surface hardening layer on the upper surface of the cap layer, and simultaneously form a groove that penetrates the surface hardening layer and has its bottom surface located in the cap layer. Then, a gate is formed on the upper surface of the surface hardening layer and fills the groove. By forming a Schottky contact between the gate and the surface hardening layer, the gate leakage current of the device is reduced. Furthermore, by forming an ohmic contact between the gate and the cap layer at the bottom surface of the groove, a charge release path is formed to release the carriers trapped in the shallow energy level trap. This stabilizes the electrical characteristics of the device under long-term stress, avoids threshold drift of the device, improves the performance and reliability of the device, and has a simple process with high industrial application value. Attached Figure Description

[0024] Figure 1 The diagram shown is a process flow diagram of the fabrication method of the HEMT device of the present invention.

[0025] Figure 2 The diagram shows a cross-sectional structure of the semiconductor structure after the gate material layer is formed in the fabrication method of the HEMT device of the present invention.

[0026] Figure 3 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the HEMT device in Example 1.

[0027] Figure 4 The diagram shown is a cross-sectional view of the HEMT device fabrication method in Example 1 after the formation of the surface reinforcement layer.

[0028] Figure 5 The diagram shows a cross-sectional structure after the groove is formed in the fabrication method of the HEMT device in Example 1.

[0029] Figure 6 The diagram shows a cross-sectional structure of the HEMT device after gate formation, as shown in Example 1.

[0030] Figure 7 The diagram shows a cross-sectional structure of the HEMT device after the passivation layer is formed, as shown in Example 1.

[0031] Figure 8 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the HEMT device in Example 2.

[0032] Figure 9 The diagram shows a cross-sectional structure of the HEMT device after gate formation, as shown in Example 2.

[0033] Explanation of icon numbers

[0034] 1. Semiconductor Structure

[0035] 11 Substrate

[0036] 12 Buffer Layers

[0037] 13. Channel layer

[0038] 14. Barrier Layer

[0039] 15 hat layers

[0040] 16 gate material layers

[0041] 17 Surface reinforcement layer

[0042] 2. Passivation layer

[0043] 21 Gate contact hole

[0044] 22 Grooves

[0045] 3 gate

[0046] 4 Source

[0047] 41 First Ohmic Contact

[0048] 42 First plug

[0049] 5 Drain

[0050] 51 Second Ohmic Contact

[0051] 52 Second plug Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] Example 1

[0055] This embodiment provides a method for fabricating a HEMT device, such as... Figure 1 The diagram shown is a process flow chart of the fabrication method of the HEMT device, including the following steps:

[0056] S1: A semiconductor structure is provided, the semiconductor structure includes a stacked structure, a cap layer, a source and a drain, the stacked structure includes a channel layer and a barrier layer stacked sequentially, the cap layer is located on the upper surface of the barrier layer, the source and the drain are electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer;

[0057] S2: Pre-process a predetermined area on the upper surface of the cap layer to form a surface reinforcement layer covering the predetermined area;

[0058] S3: Form a groove that penetrates the surface reinforcement layer and has its bottom surface located in the cap layer;

[0059] S4: Form a gate located on the upper surface of the surface reinforcement layer and filling the groove.

[0060] Please see Figures 2 to 4 Steps S1 and S2 are performed as follows: A semiconductor structure 1 is provided. The semiconductor structure 1 includes a stacked structure, a cap layer 15, a source 4, and a drain 5. The stacked structure includes a channel layer 13 and a barrier layer 14 stacked sequentially. The cap layer 15 is located on the upper surface of the barrier layer 14. The source 4 and the drain 5 are electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer 15. A predetermined area on the upper surface of the cap layer 15 is pre-processed to form a surface reinforcement layer 17 covering the predetermined area.

[0061] As an example, such as Figure 3 The diagram shows a cross-sectional view of semiconductor structure 1. Semiconductor structure 1 also includes a substrate 11 and a buffer layer 12 stacked sequentially, with a channel layer 13 located on the upper surface of the buffer layer 12.

[0062] Specifically, the substrate 11 is typically the process platform for fabricating the trench layer 13, and the material of the substrate 11 includes silicon, silicon germanium, glass, silicon carbide, sapphire, diamond, gallium nitride, or other suitable materials.

[0063] Specifically, the buffer layer 12 is typically used to alleviate the lattice mismatch between the channel layer 13 and the substrate 11, ensuring the quality of the formed channel layer 13. Its lattice needs to have a small lattice mismatch with both the substrate 11 and the channel layer 13.

[0064] Specifically, the buffer layer 12 is typically a high-resistivity film or an insulating film, and the material of the buffer layer 12 includes AlN, AlGaN, GaN, InN, Ga2O3, or other suitable materials. Preferably, a high-resistivity GaN layer is used as the buffer layer 12.

[0065] It should be noted that, typically when the substrate 11 and the channel layer 13 have a good lattice matching degree and the substrate 11 is insulating, the channel layer 13 can also be directly formed on the upper surface of the substrate 11 without the need for a buffer layer 12 to adjust the lattice matching degree between the channel layer 13 and the substrate 11.

[0066] Specifically, the channel layer 13 may be made of GaN, AlGaN, InGaN, or other suitable semiconductor materials. Preferably, a GaN layer is used as the channel layer 13.

[0067] Specifically, the material of the barrier layer 14 includes InAlGaN, AlGaN, InAlN, or other suitable materials. Preferably, an AlGaN layer is used as the barrier layer 14.

[0068] It should be noted that, due to the material properties of the barrier layer 14 and the channel layer 13, a two-dimensional electron gas layer will be generated at the interface between the barrier layer 14 and the channel layer 13.

[0069] Specifically, the cap layer 15 is typically used to completely deplete the two-dimensional electron gas layer at the interface between the channel layer 13 and the barrier layer 14 directly below, so that the device is in a turn-off state at zero gate voltage. The material of the cap layer 15 includes P-type GaN, P-type AlGaN, or other suitable semiconductor materials. Preferably, a P-type GaN layer is used as the cap layer 15.

[0070] It should be noted that, as Figure 2 The diagram shows a cross-sectional view of the semiconductor structure 1 after the gate material layer 16 is formed. In the process of fabricating the semiconductor structure 1, a buffer layer 12, a channel layer 13, a barrier layer 14 and a gate material layer 16 are usually deposited sequentially on the substrate 11, and the gate material layer 16 is etched to form a cap layer 15 located on the upper surface of the barrier layer 14; then the device source 4 and drain 5 are fabricated.

[0071] Specifically, etching the gate material layer 16 includes the following steps: forming a patterned first photoresist layer on the upper surface of the gate material layer 16; etching the gate material layer 16 based on the patterned first photoresist layer, with the remaining gate material layer 16 on the upper surface of the barrier layer 14 serving as a cap layer 15.

[0072] Specifically, the process of forming the patterned first photoresist layer involves the commonly used photoresist coating, drying, exposure, and development process, which will not be elaborated here.

[0073] Specifically, after forming the cap layer 15 and before forming the source electrode 4 and drain electrode 5, the first photoresist layer needs to be removed. The method for removing the first photoresist layer is the commonly used photoresist stripping method, which will not be described in detail here.

[0074] As an example, source 4 and drain 5 are located on the upper surface of barrier layer 14 and form ohmic contacts with barrier layer 14 respectively, that is, source 4 and drain 5 are both located on the upper surface of barrier layer 14.

[0075] It should be noted that when the source electrode 4 and the drain electrode 5 are located on the upper surface of the barrier layer 14, an electrode material layer is directly formed covering the upper surface of the barrier layer 14 and the exposed surface of the cap layer 15. Then, the electrode material layer is etched to obtain the source electrode 4 and the drain electrode 5 located on opposite sides of the cap layer 15.

[0076] Specifically, source 4 and drain 5 are located on the upper surface of barrier layer 14. After forming source 4 and drain 5, a second photoresist layer can be directly formed to cover the exposed surfaces of source 4, drain 5, cap layer 15 and barrier layer 14, and pattern the second photoresist layer to expose a predetermined area on the upper surface of cap layer 15. A surface reinforcement layer 17 is formed based on the patterned second photoresist layer to cover the predetermined area on the upper surface of cap layer 15.

[0077] It should be noted that the method for forming the second photoresist layer and patterning the second photoresist layer is the commonly used photoresist coating, drying, exposure, and development process, which will not be elaborated here.

[0078] As an example, such as Figure 4 The diagram shows a cross-sectional structure after the surface reinforcement layer 17 has been formed. The pretreatment methods for the predetermined area include surface oxygen pretreatment, surface nitrogen pretreatment, or other suitable methods. Preferably, an oxygen pretreatment process is used to treat the predetermined area of ​​the cap layer 15 to form a GaON layer of predetermined thickness on the exposed surface of the cap layer 15 in the predetermined area as the surface reinforcement layer 17.

[0079] Specifically, while ensuring device performance, the size and shape of the preset area can be selected according to the actual situation; the thickness of the surface reinforcement layer 17 can be selected according to the actual situation.

[0080] Please see Figures 5 to 7 Steps S3 and S4 are executed: a groove 22 is formed that penetrates the surface reinforcement layer 17 and has its bottom surface located in the cap layer 15; a gate 3 is formed that is located on the upper surface of the surface reinforcement layer 17 and fills the groove 22.

[0081] Specifically, after forming the surface reinforcement layer 17 and before forming the groove 22, there is also a step of removing the second photoresist layer. The method for removing the second photoresist layer is the commonly used photoresist stripping method, which will not be described in detail here.

[0082] Specifically, such as Figure 5The diagram shows a cross-sectional view of the groove 22 after it has been formed. The formation of the groove 22 includes the following steps: forming a third photoresist layer covering the exposed surfaces of the source electrode 4, drain electrode 5, cap layer 15, and surface reinforcement layer 17, and patterning the third photoresist layer; etching the surface reinforcement layer 17 based on the patterned third photoresist layer to form a window penetrating the surface reinforcement layer 17, and etching the cap layer 15 exposed by the window based on the patterned third photoresist layer to obtain the groove 22 including the window.

[0083] Specifically, the methods for forming the third photoresist layer and the patterned third photoresist layer are the commonly used photoresist coating, drying, exposure, and development processes, which will not be elaborated here.

[0084] Specifically, the method for etching the surface reinforcement layer 17 based on the patterned third photoresist layer includes dry etching, wet etching, or other suitable methods; the method for etching the bottom of the opening based on the patterned third photoresist layer includes dry etching, wet etching, or other suitable methods.

[0085] It should be noted that after forming the groove 22 and before forming the gate 3, there is a step of stripping the third photoresist layer; the method for stripping the third photoresist layer is a common photoresist stripping method, which will not be described in detail here.

[0086] Specifically, after removing the third photoresist layer and before forming the gate 3, a fourth photoresist layer is formed that covers the exposed surfaces of the source 4, drain 5, cap layer 15, and surface reinforcement layer 17, as well as the exposed upper surface of barrier layer 14, and the fourth photoresist layer is patterned; the gate 3 is formed on the upper surface of surface reinforcement layer 17 and fills the groove 22 based on the patterned fourth photoresist layer.

[0087] As an example, in the direction of the arrangement of source 4 and drain 5, the size of gate 3 is not greater than the size of surface reinforcement layer 17.

[0088] Specifically, such as Figure 6 The diagram shown is a cross-sectional view of the gate 3 after it has been formed. The methods for forming the gate 3 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0089] As an example, the contact type between the bottom surface of the gate 3 filling the groove 22 portion and the cap layer 15 is an ohmic contact, and the contact type between the gate 3 located on the surface of the surface reinforcement layer 17 and the surface reinforcement layer 17 is a Schottky contact.

[0090] Specifically, by forming a Schottky contact between the surface reinforcement layer 17 and the gate 3, the gate leakage current of the device can be reduced. At the same time, by forming an ohmic contact between the gate 3 in the groove 22 and the cap layer 15, a charge release path is formed to release the carriers trapped in the shallow energy level trap, so that the electrical characteristics of the device remain stable under long-range stress, thereby ensuring the stability of the threshold voltage of the device.

[0091] Specifically, after forming the gate 3, the process also includes removing the fourth photoresist layer and forming a passivation layer 2. The passivation layer 2 covers the sidewalls of the source 4, drain 5 and gate 3 and the exposed surface of the barrier layer 14. At the same time, the passivation layer 2 also covers the exposed surface of the cap layer 15 and the surface reinforcement layer 17.

[0092] Specifically, the method for forming the patterned fourth photoresist layer is the commonly used photoresist coating, drying, exposure and development process, and the method for removing the fourth photoresist layer is the commonly used photoresist stripping process, which will not be elaborated here.

[0093] Specifically, such as Figure 7 The diagram shown is a cross-sectional view of the passivation layer 2 after its formation. The methods for forming the passivation layer 2 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0094] Specifically, a surface reinforcement layer 17 is formed on the upper surface of the cap layer 15, and a groove 22 is formed that penetrates the surface reinforcement layer 17 and has its bottom surface located in the cap layer 15. Then, a gate 3 is formed on the upper surface of the surface reinforcement layer 17 and fills the groove 22. A Schott contact is formed between the gate 3 and the surface reinforcement layer 17 to reduce the gate leakage current of the device.

[0095] Specifically, by making the portion of the gate 3 filling the groove 22 form an ohmic contact with the cap layer 15 on the bottom surface of the groove 22, a charge release path for the carriers trapped in the shallow energy level trap is formed in the groove 22, ensuring the stability of the electrical characteristics of the device under long-range stress, avoiding the drift of the device's threshold voltage, ensuring the stability of the device's threshold voltage, and improving the device's performance and reliability.

[0096] The HEMT device fabrication method of this embodiment improves the device fabrication process by forming a surface reinforcement layer 17 in a predetermined area on the upper surface of the cap layer 15, then forming a groove 22 that penetrates the surface reinforcement layer 17 and has its bottom surface located in the cap layer 15, and then forming a gate 3 located on the upper surface of the surface reinforcement layer 17 and filling the groove 22. A Schottky contact is formed between the gate 3 and the surface reinforcement layer 17, and an ohmic contact is formed between the gate 3 and the cap layer 15 on the bottom surface of the groove 22. This reduces the gate leakage current of the device, and at the same time forms a charge release path in the groove 22, so as to stabilize the electrical characteristics of the device under long-range stress, ensure the stability of the device threshold, improve the performance and reliability of the device, and the process is simple.

[0097] Example 2

[0098] This embodiment also provides another method for fabricating a HEMT device. The specific process flow of this method is the same as that in Embodiment 1, but the construction of its semiconductor structure is different from that in Embodiment 1. Figure 8 The figure shown is a schematic cross-sectional view of semiconductor structure 1.

[0099] It should be noted that the following is a description of the construction of the semiconductor structure 1 and the process of fabricating HEMT devices based on the semiconductor structure 1.

[0100] As an example, the source and drain 5 are embedded in the stacked structure and form ohmic contacts with the channel layer 13 respectively; or the source 4 and drain 5 are embedded in the barrier layer 14 and form ohmic contacts with the barrier layer 14 respectively.

[0101] Specifically, the source 4 and the drain 5 form an ohmic contact between the barrier layer 14 or the channel layer 13 on both sides opposite to the cap layer 15, so as to realize the electrical connection between the source 4 and the two-dimensional electron gas layer directly below it, and the electrical connection between the drain 5 and the two-dimensional electron gas layer directly below it.

[0102] It should be noted that when the source electrode 4 and the drain electrode 5 are embedded in the barrier layer 14 or in the stacked structure, a first ohmic contact portion 41 and a second ohmic contact portion 51 are usually provided at the bottom of the source electrode 4 and the drain electrode 5, respectively. The first ohmic contact portion 41 is embedded in the barrier layer 14 on one side of the cap layer 15 or penetrates the barrier layer 14, and the second ohmic contact portion 51 is embedded in the barrier layer 14 on the other side of the cap layer 15 or penetrates the barrier layer 14 on the other side.

[0103] Specifically, when the source electrode 4 and drain electrode 5 are embedded in the barrier layer 14 or in the stacked structure, after the cap layer 15 is formed and before the first ohmic contact portion 41 and the second ohmic contact portion 51 are formed, corresponding ohmic contact grooves need to be formed in the corresponding areas on both sides of the cap layer 15 that are opposite to each other. Then, the first ohmic contact portion 41 that fills the ohmic contact groove on one side of the cap layer 15 and the second ohmic contact portion 51 that fills the ohmic contact groove on the other side of the cap layer 15 are formed. The method of forming the ohmic contact groove and the method of forming the first ohmic contact portion 41 and the second ohmic contact portion 51 are commonly used trench etching methods and electrode fabrication methods, which will not be described in detail here.

[0104] It should be noted that, typically, both the first ohmic contact and the second ohmic contact portion 51 protrude from the upper surface of the barrier layer 14, and the portion of both protruding from the upper surface of the barrier layer 14 covers the upper surface of the portion filling the ohmic contact groove, and their cross-sectional dimensions are larger than the cross-sectional dimensions of the portion filling the ohmic contact groove. Here, the cross-section refers to the section perpendicular to the stacking direction of the channel layer 13 and the barrier layer 14.

[0105] As an example, the semiconductor structure 1 includes a passivation layer 2 that covers the exposed upper surface of the stacked structure, a source electrode 4 that penetrates the passivation layer 2 and is electrically connected to the stacked structure, and a drain electrode 5 that penetrates the passivation layer 2 and is electrically connected to the stacked structure.

[0106] Specifically, when the semiconductor structure 1 includes a passivation layer 2, after forming the cap layer 15 and before forming the passivation layer 2, a first ohmic contact portion 41 and a second ohmic contact portion 51, respectively embedded in or penetrating the barrier layer 14, are formed on opposite sides of the cap layer 15. Then, a passivation layer 2 is formed covering the first ohmic contact, the second ohmic contact portion 51, the exposed surface of the cap layer 15, and the exposed upper surface of the barrier layer 14. After forming the passivation layer 2, a through passivation layer is formed directly above the first ohmic contact portion 41. A first contact hole of the first ohmic contact portion 41 is formed on the bottom surface of layer 2, and a second contact hole of the second ohmic contact portion 51 is formed directly above the second ohmic contact portion 51, penetrating the passivation layer 2 and exposed on the bottom surface. Finally, a first plug 42 that fills the first contact hole and is electrically connected to the first ohmic contact portion 41 and a second plug 52 that fills the second contact hole and is electrically connected to the second ohmic contact portion 51 are formed. The first plug 42 and the first ohmic contact portion 41 constitute the source electrode 4, and the second plug 52 and the second ohmic contact portion 51 constitute the drain electrode 5.

[0107] It should be noted that when the first ohmic contact 41 and the second ohmic contact 51 are embedded in the barrier layer 14, both the first ohmic contact 41 and the second ohmic contact 51 form ohmic contacts with the barrier layer 14; when the first ohmic contact 41 and the second ohmic contact 51 penetrate the barrier layer 14 and are electrically connected to the channel layer 13, both the first ohmic contact 41 and the second ohmic contact 51 form ohmic contacts with the channel layer 13.

[0108] Specifically, while ensuring device performance, the size and shape of the first ohmic contact 41 can be selected according to the actual situation; the size and shape of the second ohmic contact 51 can be selected according to the actual situation; the opening size and shape of the first contact hole can be selected according to the actual situation; and the opening size and shape of the second contact hole can be selected according to the actual situation.

[0109] As an example, before forming the surface reinforcement layer 17, the step of forming a gate contact hole 21 that penetrates the passivation layer 2 is also included. The bottom surface of the gate contact hole 21 is exposed above the cap layer 15, and the size of the gate contact hole 21 is smaller than the size of the cap layer 15. That is, when the semiconductor structure 1 includes the passivation layer 2, before forming the surface reinforcement layer 17, it is necessary to first form a gate contact hole 21 that penetrates the passivation layer 2 directly above the cap layer 15 and exposes the bottom surface of the cap layer 15 in a predetermined area.

[0110] Specifically, the methods for forming the gate contact hole 21 include dry etching, wet etching, or other suitable methods.

[0111] Specifically, the bottom surface of the gate contact hole 21 is smaller than the top surface of the cap layer 15 and only the top surface of the cap layer 15 is exposed. The bottom surface of the gate contact hole 21 is a preset area. Under the premise of ensuring device performance, the opening size and opening shape of the gate contact hole 21 can be selected according to the actual situation.

[0112] Step S2: Pre-process the preset area on the upper surface of the cap layer 15 to form a surface reinforcement layer 17 covering the preset area.

[0113] As an example, methods for pretreating the predetermined area include surface oxygen pretreatment or other suitable methods. Preferably, an oxygen treatment process, a nitrogen treatment process, or other suitable methods are used.

[0114] It should be noted that during the pretreatment of the upper surface of the cap layer 15 exposed at the bottom of the gate contact hole 21, the passivation layer 2 is used as the masking layer, and the pretreatment process is carried out directly without the need to make a new photoresist layer. That is, the bottom of the gate contact hole 21 is the preset area, and the surface reinforcement layer 17 covers the bottom of the gate contact hole 21.

[0115] Step S3: Form a groove 22 that penetrates the surface reinforcement layer 17 and has its bottom surface located in the cap layer 15.

[0116] Specifically, before forming the groove 22, a photoresist layer for making the groove 22 needs to be formed, and the photoresist layer covers the upper surface of the passivation layer 2 and fills the gate contact hole 21. At the same time, the pattern of the groove 22 in the photoresist layer penetrates the photoresist layer in the gate contact hole 21, and the bottom surface exposes the area of ​​the surface reinforcement layer 17 to be etched, so as to form a groove 22 in the cap layer 15 that penetrates the surface reinforcement layer 17 and whose bottom surface is located at the bottom of the gate contact hole 21.

[0117] Step S4: A gate 3 is formed on the upper surface of the surface reinforcement layer 17 and filled with the groove 22. In the direction of the arrangement of the source 4 and the drain 5, the size of the gate 3 is not greater than the size of the surface reinforcement layer 17.

[0118] Specifically, such as Figure 9 As shown, this is a cross-sectional view of the gate 3 after it is formed. After the groove 22 is formed, the photoresist layer for forming the groove 22 is removed. Then, the gate metal layer that fills the gate contact hole 21 and the groove 22 at the bottom of the gate contact hole 21 can be formed directly. Then, the part of the gate metal layer covering the upper surface of the passivation layer 2 is etched to obtain the gate 3.

[0119] It should be noted that an ohmic contact is formed between the portion of the gate 3 filling the groove 22 and the cap layer 15, and a Schottky contact is formed between the portion of the bottom of the gate 3 and the surface reinforcement layer 17.

[0120] Specifically, after forming the gate contact hole 21, the upper surface of the cap layer 15 exposed at the bottom of the gate contact hole 21 is pre-treated to form a surface reinforcement layer 17. A groove 22 is formed in the cap layer 15 at the bottom of the gate contact hole 21, penetrating the surface reinforcement layer 17 and with its bottom surface located below the surface reinforcement layer 17. Then, a gate 3 is formed to fill the gate contact hole 21 and the groove 22. The portion of the gate 3 filling the groove 22 forms an ohmic contact with the cap layer 15, and the portion of the bottom of the gate 3 that contacts the surface reinforcement layer 17 forms a Schottky contact with the surface reinforcement layer 17. This reduces the gate leakage current of the device, ensures the stability of the threshold voltage of the device, improves the reliability of the device, and simplifies the process.

[0121] The HEMT device fabrication method of this embodiment uses the upper surface of the cap layer 15 exposed at the bottom of the gate contact hole 21 as a preset area, forms a surface reinforcement layer 17 on the bottom surface of the gate contact hole 21, and forms a groove 22 that penetrates the surface reinforcement layer 17 and is located in the cap layer 15 at the bottom of the gate contact hole 21. Then, a gate 3 is formed to fill the gate contact hole 21 and the groove 22. A Schottky contact is formed between the gate 3 and the surface reinforcement layer 17 at the bottom of the gate contact hole 21, and an ohmic contact is formed between the gate 3 and the cap layer 15 at the bottom of the groove 22. Subsequently, a charge release path for carriers trapped in the shallow energy level trap is formed in the groove 22, which ensures the stability of the device threshold. At the same time, the Schottky contact formed between the gate 3 and the surface reinforcement layer 17 reduces the gate leakage current of the device, improves the performance and reliability of the device, and the process is simple.

[0122] Example 3

[0123] This embodiment also provides a HEMT device, such as Figure 7 and Figure 9The figures shown are schematic diagrams of one and another cross-sectional structure of the HEMT device, respectively. The HEMT device includes a semiconductor structure 1, a surface reinforcement layer 17, a groove 22, and a gate 3. The semiconductor structure 1 includes a stacked structure, a cap layer 15, a source 4, and a drain 5. The stacked structure includes a channel layer 13 and a barrier layer 14 stacked sequentially. The cap layer 15 is located on the upper surface of the barrier layer 14. The source 4 and drain 5 are electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer 15. The surface reinforcement layer 17 is located in a predetermined area on the upper surface of the cap layer 15. The groove 22 penetrates the bottom surface of the surface reinforcement layer 17 and is located within the cap layer 15. The gate 3 is located on the upper surface of the surface reinforcement layer 17 and fills the groove 22. In the arrangement direction of the source 4 and drain 5, the size of the gate 3 is smaller than the size of the surface reinforcement layer 17.

[0124] Specifically, the semiconductor structure 1 also includes a substrate 11 and a buffer layer 12 stacked sequentially, and a channel layer 13 covering the upper surface of the buffer layer 12. While ensuring device performance, the size, shape and thickness of the substrate 11 can be selected according to the actual situation; the thickness of the buffer layer 12 can be selected according to the actual situation.

[0125] Specifically, while ensuring device performance, the thickness of the channel layer 13 can be selected according to the actual situation; the thickness of the barrier layer 14 can be selected according to the actual situation; and the size, shape and thickness of the cap layer 15 can be selected according to the actual situation.

[0126] Specifically, while ensuring device performance, the size, shape, and thickness of the surface reinforcement layer 17 can be selected according to actual conditions; the opening shape, opening size, and depth of the groove 22 can also be selected according to actual conditions. Here, the depth refers to the distance between the bottom surface of the groove 22 and the upper surface of the surface reinforcement layer 17.

[0127] Specifically, the source electrode 4 can be located on the upper surface of the barrier layer 14 and electrically connected to the barrier layer 14, or it can be embedded in the barrier layer 14 and electrically connected to the barrier layer 14, or it can penetrate the barrier layer 14 and be electrically connected to the channel layer 13; the drain electrode 5 can be located on the upper surface of the barrier layer 14 and electrically connected to the barrier layer 14, or it can be embedded in the barrier layer 14 and electrically connected to the barrier layer 14, or it can penetrate the barrier layer 14 and be electrically connected to the channel layer 13.

[0128] Specifically, the device also includes a passivation layer 2, which covers the upper surface of the barrier layer 14 and the exposed surfaces of the cap layer 15 and the surface reinforcement layer 17. The cap layer 15 has a first contact hole and a second contact hole that penetrate the passivation layer 2 on opposite sides. A gate contact hole 21 that penetrates the passivation layer 2 and exposes the surface reinforcement layer 17 is located directly above the cap layer 15. A groove 22 is located at the bottom of the gate contact hole 21. The source 4 fills the first contact hole, the drain 5 fills the second contact hole, and the gate 3 fills the gate contact hole 21 and forms an ohmic contact with the cap layer 15 at the bottom of the groove 22. At the same time, a Schottky contact is formed between the gate 3 and the surface reinforcement layer 17 at the bottom of the gate contact hole 21.

[0129] Specifically, the material of passivation layer 2 includes silicon oxide, silicon nitride, or other suitable materials.

[0130] Specifically, the thickness of passivation layer 2 can be selected according to the actual situation, while ensuring device performance.

[0131] It should be noted that the source electrode 4 and the drain electrode 5 are located on the upper surface of the barrier layer 14. The bottom surfaces of the first contact hole and the second contact hole are exposed on the upper surface of the barrier layer 14. The source electrode 4, which fills the first contact hole, forms an ohmic contact with the barrier layer 14, and the drain electrode 5, which fills the second contact hole, forms an ohmic contact with the barrier layer 14. The source electrode 4 and the drain electrode 5 are respectively embedded in or penetrate the barrier layer 14. The source electrode 4 is composed of a first ohmic contact portion 41 and a first plug 42 electrically connected to the first ohmic contact portion 41. The electrode 5 is composed of a second ohmic contact 51 and a second plug 52 electrically connected to the second ohmic contact 51. Ohmic contact grooves are provided in the barrier layers 14 on both sides of the cap layer 15. The first ohmic contact 41 and the second ohmic contact 51 respectively fill the ohmic contact grooves on both sides of the cap layer 15. The bottom of the first contact hole exposes the upper surface of the first ohmic contact 41, and the bottom of the second contact hole exposes the upper surface of the second ohmic contact 51. The first plug 42 fills the first contact hole, and the second plug 52 fills the second contact hole.

[0132] Specifically, while ensuring device performance, the distance between the source 4 and the cap layer 15 can be selected according to the actual situation; the distance between the drain 5 and the cap layer 15 can be selected according to the actual situation.

[0133] Specifically, the material of the first plug 42 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the second plug 52 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the first ohmic contact 41 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; and the material of the second ohmic contact 51 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0134] Specifically, a surface reinforcement layer 17 of a preset thickness is provided in a preset area on the upper surface of the cap layer 15, and a groove 22 is provided that penetrates the surface reinforcement layer 17 and has its bottom surface located in the cap layer 15. The gate 3 is located on the upper surface of the surface reinforcement layer 17 and fills the groove 22. The part of the gate 3 that fills the groove 22 forms an ohmic contact with the cap layer 15. As a result, a charge release path for releasing carriers trapped in shallow energy level traps is formed in the gate structure of the device, which ensures the stability of the device threshold and improves the reliability of the device.

[0135] Specifically, by forming a Schottky contact between the gate 3 on the upper surface of the surface reinforcement layer 17, the gate leakage current of the device is reduced and the performance of the device is improved.

[0136] The HEMT device in this embodiment improves the device structure by setting a surface reinforcement layer 17 in a preset area on the upper surface of the cap layer 15, and setting a groove 22 that penetrates the surface reinforcement layer 17 and has its bottom surface located in the cap layer 15. This allows the gate 3 to be located on the upper surface of the surface reinforcement layer 17 and fill the groove 22. The gate 3 forms a Schottky contact with the surface reinforcement layer 17 and an ohmic contact with the cap layer 15 on the bottom surface of the groove 22, which reduces the gate leakage current of the device. The gate 3 in the groove 22 and the cap layer 15 form a charge release path, which ensures the stability of the threshold voltage of the device and improves the reliability of the device.

[0137] In summary, the HEMT device and its fabrication method of the present invention form a surface hardening layer on the upper surface of the cap layer, and form a groove that penetrates the surface hardening layer and has its bottom surface located in the cap layer. Simultaneously, the gate is located on the upper surface of the surface hardening layer and fills the groove. Schottky contacts and ohmic contacts are formed between the gate and the surface hardening layer and the cap layer at the bottom of the groove, respectively. The Schottky contact between the gate and the surface hardening layer reduces gate leakage, while the ohmic contact between the gate and the cap layer at the bottom of the groove creates a charge release path for carriers trapped in shallow energy level traps. This stabilizes the electrical characteristics of the device under long-range stress, avoids threshold drift, and improves the device's performance and reliability. Furthermore, the process is simple. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0138] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a HEMT device, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including a stacked structure, a cap layer, a source and a drain, the stacked structure including a channel layer and a barrier layer stacked sequentially, the cap layer being located on the upper surface of the barrier layer, the source and the drain being electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer; A predetermined area on the upper surface of the cap layer is pre-treated to form a surface reinforcement layer covering the predetermined area; A groove is formed that penetrates the surface reinforcement layer and has its bottom surface located in the cap layer; A gate is formed on the upper surface of the surface reinforcement layer and fills the groove.

2. The method for fabricating a HEMT device according to claim 1, characterized in that: The semiconductor structure also includes a substrate and a buffer layer stacked sequentially, with the channel layer located on the upper surface of the buffer layer.

3. The method for fabricating a HEMT device according to claim 1, characterized in that: The source and the drain are located on the upper surface of the barrier layer and respectively form ohmic contacts with the barrier layer.

4. The method for fabricating a HEMT device according to claim 1, characterized in that: The source and the drain are embedded in the stacked structure and respectively form ohmic contacts with the channel layer; or the source and the drain are respectively embedded in the barrier layer and respectively form ohmic contacts with the barrier layer.

5. The method for fabricating a HEMT device according to claim 1, characterized in that: The methods for pretreating the preset area include surface oxygen pretreatment and surface nitrogen pretreatment.

6. The method for fabricating a HEMT device according to claim 1, characterized in that: In the direction of the source and drain arrangement, the size of the gate is not greater than the size of the surface reinforcement layer.

7. The method for fabricating a HEMT device according to claim 1, characterized in that: The contact type between the bottom surface of the gate filling the groove portion and the cap layer is an ohmic contact, and the contact type between the gate located on the surface of the surface reinforcement layer and the surface reinforcement layer is a Schottky contact.

8. The method for fabricating a HEMT device according to claim 1, characterized in that: The semiconductor structure includes a passivation layer that covers the exposed upper surface of the stacked structure. The source electrode penetrates the passivation layer and is electrically connected to the stacked structure, and the drain electrode penetrates the passivation layer and is electrically connected to the stacked structure.

9. The method for fabricating a HEMT device according to claim 8, characterized in that: Before forming the surface reinforcement layer, the method further includes the step of forming a gate contact hole that penetrates the passivation layer, wherein the bottom surface of the gate contact hole exposes the upper surface of the cap layer, and the size of the gate contact hole is smaller than the size of the cap layer.

10. A HEMT device, characterized in that, include: A semiconductor structure includes a stacked structure, a cap layer, a source, and a drain. The stacked structure includes a channel layer and a barrier layer stacked sequentially. The cap layer is located on the upper surface of the barrier layer. The source and the drain are electrically connected to the stacked structure and located at a predetermined distance on opposite sides of the cap layer. A surface reinforcement layer covers a predetermined area on the upper surface of the cap layer; A groove extends through the surface reinforcement layer and its bottom surface is located within the cap layer; The gate is located on the upper surface of the surface reinforcement layer and fills the groove.

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