Methods of forming semiconductor structures, semiconductor structures, and electronic devices

Abstract

The application discloses a method for forming a semiconductor structure, a semiconductor structure and an electronic device. The method is used for a fin structure in a substrate. A channel material layer of the fin structure is shortened in a second direction perpendicular to the extension direction of the fin structure to form recesses on both sides of the channel material layer. Then, an insulating material with a Young's modulus greater than that of the channel material layer is used to form a rigid insulating material layer filling the recesses, so that the channel material layer is formed with the rigid insulating material layer adjacent to both sides of the channel material layer. Then, a dummy gate structure is formed across the fin structure, and the dummy gate structure is removed. Then, a sacrificial material layer in the fin structure is removed after the removal of the dummy gate structure. Thus, the bending stiffness of the nanochannel layer is increased by using the insulating material with a high Young's modulus, the problems of bending deformation of the nanochannel and sticking between adjacent nanochannels in a subsequent wet process are prevented, and the yield and performance of the formed semiconductor structure are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology

[0002] As the size of semiconductor devices continues to shrink, in order to reduce short-channel effects and improve the performance of semiconductor devices, three-dimensional field-effect transistors with fin structures have emerged, such as the Gate-All-Around Field-Effect Transistor (GAAFET).

[0003] In the front-end of line (FEOL) fabrication of GAAFETs, wet etching is typically used to remove the sacrificial material layer to release the nanochannels and provide filling space for subsequent gate structure replacement. In related technologies, during the formation of long-channel GAAFET devices with nanochannel lengths exceeding 70 nm, issues such as nanochannel bending and deformation, and localized adhesion between adjacent nanochannels often occur, thereby reducing the yield and performance of the formed semiconductor devices. Summary of the Invention

[0004] To address the problems of the prior art, embodiments of this application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. The technical solution is as follows:

[0005] On the one hand, a method for forming a semiconductor structure is provided, comprising:

[0006] A substrate is provided, the substrate including a substrate and a fin structure extending on the substrate along a first direction; the fin structure including alternating stacked layers of channel material and sacrificial material.

[0007] The channel material layer of the fin structure is shortened along the second direction to form recesses on both sides of the channel material layer, wherein the second direction is perpendicular to the first direction;

[0008] A rigid insulating material layer is formed to fill the recess, wherein the Young's modulus of the rigid insulating material layer is greater than that of the channel material layer;

[0009] A pseudo-gate structure is formed across the fin structure, and the pseudo-gate structure is removed, followed by the removal of the sacrificial material layer.

[0010] In one exemplary embodiment, the shortening process of the channel material layer of the fin structure along the second direction includes:

[0011] The fin structure is subjected to isotropic selective etching along the second direction; the selective etching rate on the channel material layer is greater than the etching rate on the sacrificial material layer.

[0012] In one exemplary embodiment, the selective etching selectivity ratio for the channel material layer and the sacrificial material layer is greater than 2.

[0013] In one exemplary embodiment, the depth of the recess in the second direction is 1 to 10 nm.

[0014] In one exemplary embodiment, the rigid insulating material layer forming the recess includes:

[0015] After the shortening process, a liner is deposited on the substrate; the Young's modulus of the liner is greater than that of the channel material layer, and the deposition thickness of the liner on the substrate surface is greater than half the thickness of the channel material layer in the vertical direction.

[0016] Remove part of the liner covering the outer surface of the fin structure, and retain part of the liner filling the recess as the rigid insulating material layer.

[0017] In one exemplary embodiment, removing the portion of the liner covering the outer surface of the fin structure includes:

[0018] A shallow groove material layer is formed on the liner, the top surface of the shallow groove material layer being higher than the top surface of the fin structure;

[0019] The shallow trench material layer is planarized, and then the shallow trench material layer is etched back after planarization until the top surface of the remaining shallow trench material layer is lower than the bottom surface of the fin structure, so that the remaining shallow trench material layer forms a shallow trench isolation structure; wherein, a portion of the liner covering the outer surface of the fin structure is removed during the planarization and the back etching process.

[0020] In one exemplary implementation, the provision of the substrate includes:

[0021] An initial substrate is provided, on which a superlattice structure is formed, the superlattice structure comprising alternating stacked channel material layers and sacrificial material layers;

[0022] The superlattice structure is patterned to form the substrate.

[0023] In one exemplary embodiment, after removing the sacrificial material layer, the method further includes:

[0024] The rigid insulating material layers on both sides of the channel material layer are removed using an isotropic dry etching process;

[0025] A gate structure is formed across the fin structure, the gate structure surrounding the channel material layer.

[0026] In one exemplary embodiment, the rigid insulating material layer comprises one or a combination of two of silicon nitride and silicon carbide.

[0027] In one exemplary embodiment, removing the sacrificial material layer includes removing the sacrificial material layer using a wet etching process.

[0028] In one exemplary embodiment, the channel material layer is a first semiconductor material comprising silicon, and the sacrificial material layer is a second semiconductor material comprising germanium silicon.

[0029] On the other hand, a semiconductor structure is provided, formed using any of the aforementioned methods for forming a semiconductor structure, comprising:

[0030] Substrate;

[0031] A fin structure located on the substrate, the fin structure extending along a first direction;

[0032] Multiple channel structures are spaced apart in the fin structure. Each channel structure includes a channel material layer and a rigid insulating material layer located on both sides of the channel material layer and adjacent to the channel material layer. The Young's modulus of the rigid insulating material layer is greater than that of the channel material layer.

[0033] In one exemplary embodiment, the rigid insulating material layer has a length of 1 to 10 nm in a second direction, which is perpendicular to the first direction.

[0034] In one exemplary implementation, it further includes:

[0035] A gate structure spanning the fin structure, the gate structure surrounding each of the channel material layers.

[0036] On the other hand, an electronic device is provided, the electronic device comprising a semiconductor structure formed using any of the foregoing methods for forming a semiconductor structure.

[0037] In this embodiment, for the fin structure in the substrate, the channel material layer of the fin structure is shortened along a second direction perpendicular to the extension direction of the fin structure to form recesses on both sides of the channel material layer. Then, an insulating material with a Young's modulus greater than that of the channel material layer is used to form a rigid insulating material layer that fills the recesses, so that rigid insulating material layers are formed on both sides of the channel material layer. After that, a pseudo-gate structure is formed across the fin structure, and the pseudo-gate structure is removed. After removing the pseudo-gate structure, the sacrificial material layer in the fin structure is removed. By using an insulating material with a high Young's modulus, the bending rigidity of the nanochannel layer is increased, which can prevent the nanochannel bending deformation or the adhesion between adjacent nanochannels during the subsequent wet process to release the nanochannel, thereby improving the yield and performance of the formed semiconductor structure. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a long-channel GAAFET structure formed in the prior art;

[0040] Figure 2 This is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application;

[0041] Figures 3 to 7 These are some structural cross-sectional views of the semiconductor structure formation process provided in the embodiments of this application;

[0042] Figure 8 This is a partial flowchart illustrating another method for forming a semiconductor structure provided in an embodiment of this application;

[0043] Figures 9 to 10k These are some other structural cross-sectional views of the semiconductor structure formation process provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0047] The formation method of this application embodiment can be used to form GAAFET devices / structures below 3nm. The GAAFET device can be a P-type metal-oxide-semiconductor (PMOS) device, an N-type metal-oxide-semiconductor (NMOS) device, or a complementary metal-oxide-semiconductor (CMOS) device.

[0048] In related technologies, wet etching is typically used to remove the sacrificial material layer (such as the SiGe layer) while retaining the channel material layer (such as the Si layer) to release the nanochannels in the GAAFET structure. However, during the formation of long-channel GAAFET devices with nanochannel lengths exceeding 70 nm, problems such as nanochannel bending and deformation, and local adhesion between adjacent nanochannels often occur. Please refer to [link to relevant documentation]. Figure 1The diagram shown is a schematic of a long-channel GAAFET structure formed in the prior art. This schematic is a cross-sectional view of the nanochannels released after the sacrificial material layer is removed using a wet process. Figure 1 As shown in the dashed box, the nanochannels exhibit bending deformation and local adhesion between adjacent nanochannels, which reduces the yield of the formed semiconductor structure.

[0049] Furthermore, considering that the threshold voltage of GAAFET devices is related to the spatial consistency between adjacent nanochannels, and that the failure of some nanochannels to be surrounded by the gate dielectric layer leads to a loss of effective width (Weff) of the nanochannels, and that the weak control of the gate structure over the bonded nanochannel regions also leads to increased current leakage, the bending deformation of the nanochannels and the local bonding of adjacent nanochannels degrade the performance of the formed semiconductor structure.

[0050] In developing this invention, the inventors discovered that the forces causing bending deformation and adhesion include capillary forces during wet processing and intermolecular attraction after drying. Bending stiffness is typically used to characterize the mechanical properties of graphic structures. Generally, low bending stiffness means the graphic structure is more vulnerable and more likely to suffer bending deformation and adhesion during processing. Therefore, increasing the bending stiffness of the graphic structure can effectively prevent bending deformation and adhesion problems during processing. Based on this, the inventors further discovered that the bending stiffness of the graphic structure is related to the following factors:

[0051]

[0052] Where S represents bending stiffness; E represents Young's modulus; d represents diameter; and h represents height.

[0053] Therefore, it can be seen that the bending stiffness of a graphic structure is positively correlated with Young's modulus. Thus, introducing materials with high Young's modulus into a graphic structure can increase its bending stiffness.

[0054] In view of this, embodiments of the present application provide a method for forming a semiconductor structure. For a fin structure extending in a first direction in a substrate, the fin structure includes alternately stacked channel material layers and sacrificial material layers. The channel material layers of the fin structure are subjected to a shortening treatment in a second direction perpendicular to the first direction, so as to form recesses on both sides of the channel material layers respectively. Furthermore, an insulating material with a Young's modulus greater than that of the channel material layers is used to form rigid insulating material layers filling the recesses, such that the rigid insulating material layers adjacent to the channel material layers are formed on both sides of the channel material layers. Thereafter, a dummy gate structure spanning the fin structure is formed, the dummy gate structure is removed, and the sacrificial material layers in the fin structure are removed after the dummy gate structure is removed. Therefore, the use of the insulating material with a high Young's modulus increases the bending rigidity of the nano-channel layers, which can prevent the problems of bending deformation of the nano-channels or adhesion between adjacent nano-channels when the nano-channels are released in a subsequent wet process, and improve the yield and performance of the formed semiconductor structure.

[0055] To make the above objects, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0056] Please refer to Figure 2 , which shows a schematic flow diagram of a method for forming a semiconductor structure provided by an embodiment of the present application, Figures 3 to 9 which is a structural cross-sectional view during the formation process of a semiconductor structure provided by an embodiment of the present application.

[0057] Please refer to Figure 2 , in step S201, a substrate is provided, and the substrate includes a base and a fin structure extending on the base in a first direction.

[0058] The fin structure includes alternately stacked channel material layers and sacrificial material layers. The sacrificial material layers will be removed in a subsequent process, and the channel material layers will be partially retained to form nano-channels of the semiconductor structure. Specifically, the thicknesses of the channel material layers and the sacrificial material layers may be the same or different, the thicknesses of the respective channel material layers may be the same or different, and the thicknesses of the respective sacrificial material layers may be the same or different.

[0059] In an example, the channel material layers in the fin structure are a first semiconductor material containing silicon, and the sacrificial material layers in the fin structure are a second semiconductor material containing silicon germanium; in another example, the channel material layers in the fin structure are a second semiconductor material containing silicon germanium, and the sacrificial material layers in the fin structure are a first semiconductor material containing silicon. At this time, the silicon germanium Si 1-x Ge x in the second semiconductor material for forming the channel material layers may have a Ge atom concentration of 20% to 40% (0.2<x<0.4), so as to improve the carrier mobility in the channel.

[0060] In specific implementations, the substrate can be a bulk semiconductor or a silicon-on-insulator (SOI) substrate, which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The SOI substrate is a semiconductor material layer formed on an insulating layer, which can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, disposed on a silicon substrate or a glass substrate. In specific implementations, the semiconductor material of the substrate can include one or more of silicon, germanium, compound semiconductors, and alloy semiconductors. The compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor can be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium arsenide phosphide.

[0061] The fin structure can be disposed on the device region of the substrate, which can be a region designed to form an NMOS device or a PMOS device. The region used to form an NMOS device can be a semiconductor region doped with an n-type dopant, such as arsenic (As), antimony (Sb), or phosphorus (P); the region used to form a PMOS device can be a semiconductor region doped with a p-type dopant, such as boron (B).

[0062] like Figure 3 The diagram shows a cross-sectional view of a substrate 300, which includes a substrate 310 and a fin structure 320 located on the substrate 310. The fin structure 320 extends along a first direction parallel to the surface of the substrate 310, hereinafter referred to as the X-axis direction. It is understood that the substrate 310 may have one or more discrete fin structures 320. The fin structure 320 includes alternately stacked channel material layers 321 and sacrificial material layers 322. It should be noted that... Figure 3 Although the bottom layer of the alternating stack is shown as channel material layer 321, in practical applications, sacrificial material layer 322 can also be used as the bottom layer of the alternating stack.

[0063] Based on this, the formation process of the substrate 300 may be as follows: providing an initial substrate, forming a superlattice structure on the initial substrate, the superlattice structure including alternately stacked channel material layers and sacrificial material layers; and patterning the superlattice structure to form the substrate 300.

[0064] In practice, an epitaxial growth process can be used to grow channel material layers and sacrificial material layers from the top surface of the initial substrate to form a superlattice structure. For example, the channel material layers and sacrificial material layers can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and / or other suitable epitaxial growth processes. During epitaxial growth, the crystal structure of the initial substrate extends upwards, thereby producing channel material layers and sacrificial material layers with the same crystal orientation as the initial substrate. Taking a channel material layer containing silicon and a sacrificial material layer containing germanium-silicon as an example, a silicon layer can be epitaxially grown first, then a germanium-silicon layer can be epitaxially grown on that silicon layer, then another silicon layer can be epitaxially grown on that germanium-silicon layer, and so on, thereby forming alternating stacked silicon and germanium-silicon layers on the initial substrate.

[0065] Patterning the superlattice structure to form the substrate 300 can be achieved by: forming a patterned photoresist layer on the superlattice structure, the patterned photoresist layer having a pattern defining the device region of the substrate; then, using the patterned photoresist layer as an etching mask, etching a portion of the channel material layer and the sacrificial material layer as well as a portion of the initial substrate, wherein the unetched channel material layer and the sacrificial material layer form the fin structure 320, and the remaining initial substrate forms the substrate 310; and then, removing the patterned photoresist layer.

[0066] Understandably, in order to protect the fin structure in subsequent processes, one or more mask layers can be formed on the superlattice structure before forming the patterned photoresist layer. Each mask layer can be made of different materials. For example, before forming the patterned photoresist layer, a silicon oxide layer, a silicon nitride layer, etc. can be formed on the superlattice structure. Then, a patterned photoresist layer is formed on the one or more mask layers. When the superlattice structure is patterned, the one or more mask layers are also patterned, and the patterned mask layer is retained on the fin structure 320.

[0067] Continue reading Figure 2 In step S203, the channel material layer of the fin structure is shortened along the second direction to form recesses on both sides of the channel material layer.

[0068] The second direction is parallel to the substrate surface and perpendicular to the first direction, i.e., the X-axis direction. Hereinafter, the second direction will be referred to as the Y-axis direction.

[0069] Specifically, the channel material layer in the fin structure can be shortened along the Y-axis from the two exposed sides of the fin structure, so that the channel material layer is recessed relative to the sacrificial material layer, thereby forming a recess on both sides of each channel material layer. This recess is used to fill the channel material layer with a high Young's modulus insulating material to improve the bending stiffness of the channel material layer.

[0070] like Figure 4 The diagram shows a cross-sectional view of the channel material layer of the fin structure after it has been shortened along the second direction, wherein the recess 401 is formed on both sides of each channel material layer.

[0071] For example, the depth H of the recess 401 in the Y-axis direction is 1 to 10 nm. It can be understood that since the formation of the recess 401 shortens the channel material layer accordingly, the greater the depth of the recess 401 in the Y-axis direction, although it can improve the bending stiffness of the channel material layer to a greater extent, the nanochannel of the semiconductor structure formed subsequently will be relatively shorter. In practical applications, for long-channel GAAFET devices, the required depth of the recess 401 can be set according to the specific length of the nanochannel.

[0072] In one exemplary embodiment, shortening the channel material layer of the fin structure along the second direction may include:

[0073] The fin structure is subjected to isotropic selective etching along the second direction, wherein the etching rate of the channel material layer is greater than the etching rate of the sacrificial material layer.

[0074] Among them, isotropic selective etching can be carried out using wet etching process or isotropic dry etching process.

[0075] For example, the selective etching selectivity ratio for the channel material layer and the sacrificial material layer is greater than 2. Taking a channel material layer containing silicon (Si) and a sacrificial material layer containing germanium-silicon (SiGe) as an example, the Si:SiGe etching selectivity ratio should be greater than 2. If the etching selectivity ratio is too small, the sacrificial layer material will also shorten in the Y and Z directions when etching the channel layer material, failing to form a recess with a certain depth and a small opening. As a result, the subsequent rigid insulating material liner cannot fill the recess, and no liner material can be left in the recess when removing the surface liner.

[0076] Continue reading Figure 2 In step S205, a rigid insulating material layer is formed to fill the recess, wherein the Young's modulus of the rigid insulating material layer is greater than that of the channel material layer.

[0077] like Figure 5The diagram shows a cross-sectional view after each recess 401 is filled with a rigid insulating material layer 501. After filling each recess 401 with the rigid insulating material layer 501, the two sides of each remaining channel material layer are adjacent to the rigid insulating material layer 501. Each remaining channel material layer and the rigid insulating material layers 501 located on both sides and adjacent to it can be considered as the channel structure 510 of this embodiment. The channel material layer 511 in this channel structure 510 is used to form the nanochannel of the GAAFET device. Because the Young's modulus of the rigid insulating material layer 501 is greater than that of the channel material layer, the channel structure 510 of this embodiment has higher bending stiffness.

[0078] For example, the rigid insulating material layer 501 may include one or a combination of silicon nitride and silicon carbide.

[0079] In one exemplary embodiment, forming a rigid insulating material layer that fills the recess may include:

[0080] After the shortening process, a liner is deposited on the substrate; the Young's modulus of the liner is greater than that of the channel material layer, and the deposition thickness of the liner on the substrate surface is greater than half the thickness of the channel material layer in the vertical direction.

[0081] Remove part of the liner covering the outer surface of the fin structure, and retain part of the liner filling the recess as the rigid insulating material layer.

[0082] Specifically, the materials used to form the liner may include silicon nitride, silicon carbide, etc. The liner can be deposited on the substrate by chemical vapor deposition, and the deposition thickness of the liner needs to be greater than half the thickness of the channel material layer.

[0083] Understandably, when depositing a liner on a substrate, the liner can be deposited on the substrate surface and the exposed surface of the fin structure. The exposed surface of the fin structure can include the outer surface (upper surface, sidewall surface) and a portion of the surface of the sacrificial material layer exposed by the recess. The liner deposited in the recess is achieved through a portion of the surface of the sacrificial material layer exposed by the recess. Therefore, by controlling the deposition thickness of the liner on the substrate surface to be greater than half the thickness of the channel material layer in the vertical direction, it can be ensured that the liner deposited in the recess can be combined so that the recess can be filled by the liner. The vertical direction refers to the direction perpendicular to the substrate surface.

[0084] In an exemplary embodiment, the shallow trench isolation structure has not yet been formed in the substrate provided in step S201. Therefore, step S203 can be performed before entering the shallow trench isolation structure formation process, and a rigid insulating material layer filling the recesses can be formed during the shallow trench isolation structure formation process. This allows for the improvement of the bending rigidity of the channel structure without changing the original formation processes of the GAAFET. Based on this, the removal of the portion of the liner covering the outer surface of the fin structure can include:

[0085] A shallow groove material layer is formed on the liner, the top surface of the shallow groove material layer being higher than the top surface of the fin structure;

[0086] The shallow trench material layer is planarized, and then the shallow trench material layer is etched back after planarization until the top surface of the remaining shallow trench material layer is lower than the bottom surface of the fin structure, so that the remaining shallow trench material layer forms a shallow trench isolation structure; wherein, a portion of the liner covering the outer surface of the fin structure is removed during the planarization and the back etching process.

[0087] Specifically, the shallow trench material layer can be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, low-k dielectric material, and / or other suitable insulating material. The shallow trench material layer can be formed on the substrate using deposition processes such as chemical vapor deposition, and the shallow trench material layer fills the gaps between adjacent fin structures and is higher than the fin structures.

[0088] The shallow trench material layer can be planarized using processes such as CMP (Chemical Mechanical Polishing) to make its top surface flush with the top surface of the fin structure. Understandably, during the planarization process, part of the liner on the top surface of the fin structure will be removed. A plasma-based dry etching process can then be used to etch back the shallow trench material layer after planarization. During this back etching process, the liner on the side surface of the fin structure will be removed.

[0089] In the above embodiments, by removing part of the liner covering the outer surface of the fin structure during the formation of the shallow trench isolation structure, and then retaining part of the substrate filling the recess to obtain a rigid insulating material layer that fills the recess, it is possible to improve the bending rigidity of the channel structure without changing the original formation process of GAAFET, thereby reducing the complexity of the semiconductor structure formation process.

[0090] In another exemplary embodiment, a shallow trench isolation structure has been formed in the substrate provided in step S201. Therefore, steps S203 and S205 are performed after the shallow trench isolation structure is formed. Based on this, the removal of the liner covering the outer surface of the fin structure can be done by using a dry etching process to remove the liner covering the upper and side surfaces of the fin structure. In this process, the liner on the surface of the shallow trench isolation structure is also removed, thereby retaining the liner filling the recess as a rigid insulating material layer.

[0091] Continue reading Figure 2 In step S207, a pseudo-gate structure is formed across the fin structure, the pseudo-gate structure is removed, and the sacrificial material layer is removed after the pseudo-gate structure is removed.

[0092] Specifically, the pseudo-gate structure is used to define the location and size of the gate structure that is subsequently formed. This pseudo-gate structure spans the fin structure and covers part of the top surface and part of the sidewall surface of the fin structure.

[0093] like Figure 6 The diagram shows a cross-sectional view of a pseudo-gate structure forming across the fin structure. The pseudo-gate structure 610 includes a pseudo-gate dielectric layer 611 formed on the fin structure 320 and a pseudo-gate electrode 612 formed on the pseudo-gate dielectric layer 611. The pseudo-gate dielectric layer 611 may be formed of silicon oxide (SiO2), and the pseudo-gate electrode 612 may be formed of amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon.

[0094] The formation of the pseudo-gate structure on the fin structure can be achieved by: conformally forming a dielectric layer on a substrate, which covers the fin structure and the shallow trench isolation structure; the dielectric layer material may include silicon oxide; depositing an electrode layer (not shown in the figure) on the dielectric layer; the electrode layer material may include amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon; the deposition process may include chemical vapor deposition (LPCVD); forming a patterned mask on the electrode layer, which defines the location of the channel region on the fin structure; then using the patterned mask as an etching mask, performing one or more etching processes to form a pseudo-gate structure spanning the fin structure in the channel region of the fin structure; and finally removing the patterned mask after the etching process.

[0095] In practical applications, after forming the dummy gate structure, source / drain regions can be formed on both sides of the dummy gate structure on the fin structure. Specifically, forming the source / drain regions can be achieved by epitaxially growing a semiconductor layer to form the source / drain components. For PMOS, the material of the epitaxially grown semiconductor layer can be doped with boron, and for NMOS, the material of the epitaxially grown semiconductor layer can be doped with phosphorus. In specific implementations, the semiconductor layer can be grown using molecular beam epitaxy, chemical vapor deposition, and / or other suitable epitaxial growth processes.

[0096] Removing the dummy gate structure exposes the area on the fin structure covered by it, which will subsequently serve as the channel region of the semiconductor structure. Specifically, removing the dummy gate structure may include removing the dummy gate electrode and the underlying dummy gate dielectric layer, using one or more etching processes, such as wet etching, dry etching, or other etching techniques. The cross-sectional view after removing the dummy gate structure will be similar to that described above. Figure 5 The sectional view shown.

[0097] Next, removing the sacrificial material layer from the fin structure can form a gate opening, such as... Figure 7 As shown, the gate opening 710 is formed in the space between adjacent channel structures 510 of the fin structure. Specifically, since the channel structure 510 of this embodiment includes a shortened channel material layer 511 and rigid insulating material layers 501 located on both sides of and adjacent to the channel material layer, the Young's modulus of the material corresponding to the rigid insulating material layer 501 is greater than that of the material corresponding to the channel material layer, thereby greatly improving the bending rigidity of the channel structure. Therefore, when removing the sacrificial material layer in the fin structure, a wet etching process can be used to remove it to release the nanochannel, and the problems of channel layer bending and adjacent channel adhesion caused by the wet process to release the nanochannel can be effectively avoided.

[0098] The wet etching process can selectively remove the sacrificial material layer in the fin structure. When the sacrificial material layer contains germanium silicon, the wet etchant in the wet etching process can be a mixed solution containing hydrogen peroxide, acetic acid and / or hydrofluoric acid. When the sacrificial material layer contains silicon, the wet etchant in the wet etching process can be a mixed solution of ammonium hydroxide (NH4OH) and hydrogen peroxide, or a tetramethylammonium hydroxide (TMAH) solution.

[0099] In practical applications, after removing the sacrificial material layer, a gate structure spanning the fin structure can be formed. This gate structure can surround the channel structure. Specifically, the gate structure can surround the channel material layer and the rigid insulating material layer in the channel structure.

[0100] In some exemplary embodiments, considering that a rigid insulating material layer in the channel structure may introduce channel impurities or affect channel stress, in order to further improve the performance and yield of the semiconductor structure, such as Figure 8 As shown, after removing the sacrificial material layer in step S207, the method may further include:

[0101] In step S209, an isotropic dry etching process is used to remove the rigid insulating material layers on both sides of the channel material layer.

[0102] In step S211, a gate structure is formed across the fin structure, the gate structure surrounding the channel material layer.

[0103] Specifically, isotropic dry etching processes possess the characteristics of isotropic etching, thereby enabling the etching of rigid insulating material layers on both sides of the channel material layer along the Y-axis. For example, an isotropic dry etching process could be, for instance, a plasma etching process. Figure 9 The diagram shows a cross-sectional view after the rigid insulating material layers on both sides of the channel material layer are removed. The rigid insulating material layer 501 in the channel structure 510 is removed by using an isotropic dry etching process, while the shortened channel material layer 511 in the channel structure 510 is retained. The retained channel material layer 511 will serve as the nanochannel of the semiconductor structure.

[0104] The gate structure spanning the fin structure may include a dielectric layer and a gate electrode. The dielectric layer is formed on the outer surface of the shortened channel material layer 511, and the gate electrode is formed on the dielectric layer and fills the space between adjacent channel material layers 511 to increase control over the nanochannel and reduce the short-channel effect of the device.

[0105] In specific implementations, the dielectric layer may include a high-k dielectric layer, which may include a high-k dielectric material (e.g., a dielectric material with a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, and may be formed using one or a combination of molecular beam deposition (MBD), ALD, PECVD, etc. The gate electrode is deposited on the high-k dielectric layer and may include a liner layer, a work function adjustment layer, and a conductive material. The liner layer may include TiN, TiO, TaN, TaC, combinations thereof, or multilayers thereof, and may be formed using PVD, CVD, ALD, or combinations thereof. The work function adjustment layer may include TiN, WN, TaN, Ru, Co, combinations thereof, or multilayers thereof, and may be formed using PVD, CVD, ALD, or combinations thereof. Conductive materials may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, their alloys, combinations thereof, or multilayers thereof, and may be formed by PVD, CVD, ALD, electroplating, or combinations thereof.

[0106] In the above embodiments, after removing the sacrificial material layer, the rigid insulating material layers on both sides of the channel material layer are removed first, and then the gate structure spanning the fin structure is formed. This avoids channel impurities introduced by the presence of the rigid insulating material layer and their adverse effects on channel stress. Furthermore, when removing the rigid insulating material layers on both sides of the channel material layer, an isotropic dry etching process is used, which effectively avoids the problems of nanochannel bending deformation and adhesion caused by capillary forces in wet processes and intermolecular attraction after drying, thus ensuring the performance and yield of the semiconductor structure.

[0107] The following is combined with Figures 10a to 10d The specific examples shown illustrate the formation process of the semiconductor structure in the embodiments of this application in detail.

[0108] See Figure 10a A superlattice structure 1020 is formed on an initial substrate 1010. The superlattice structure 1020 includes alternating stacked silicon nanomaterial layers 1021 and germanium-silicon nanomaterial layers 1022. The silicon nanomaterial layer 1021 is used to form the nanochannel of the semiconductor structure, i.e., as the channel material layer, and the germanium-silicon nanomaterial layer 1022 is used as the sacrificial material layer.

[0109] See next Figure 10b A mask layer 1030 and a patterned photoresist layer 1040 are sequentially formed on the superlattice structure 1020, wherein the mask layer 1030 can be a multilayer structure of silicon oxide-silicon nitride-silicon oxide.

[0110] See next Figure 10c Using a patterned photoresist layer 1040 as an etching mask, a superlattice structure 1020 and a portion of the initial substrate 1010 are etched to obtain a substrate 1050. The remaining initial substrate 1010 forms substrate 1051 within the substrate 1050, and substrate protrusions 1052 located on substrate 1051. The unetched superlattice structure 1020 forms a fin structure 1060 located on substrate protrusions 1052. The fin structure 1060 includes a silicon nanomaterial layer 1061 and a germanium-silicon nanomaterial layer 1062 stacked on each other. For ease of description, the substrate protrusions 1052, the fin structure 1060 located on substrate protrusions 1052, and the mask layer retained on the fin structure 1060 are referred to as fins.

[0111] See next Figure 10d An isotropic etching process with an etching selectivity ratio of Si:SiGe greater than 2 is used to etch the fins on the substrate 1051 along the Y-axis, thereby shortening the length of the silicon nanomaterial layer 1061 in the fin structure 1060 along the Y-axis, so that recesses 1070 are formed on both sides of the silicon nanomaterial layer 1061.

[0112] See next Figure 10e A silicon nitride liner 1080 is deposited on the substrate, which fills each recess 1070 and covers the exposed surface of the substrate 1051 and the outer surface of the fins. It should be noted that the Young's modulus of silicon (111) is about 190 GPa, and the Young's modulus of silicon nitride is about 323 GPa.

[0113] See next Figure 10f A shallow trench material layer 1090 is deposited on a silicon nitride substrate 1080, the top surface of which is higher than the top surface of the fin.

[0114] See next Figure 10g Excess shallow trench material layer 1090 is removed by planarization and back etching until the top surface of the remaining shallow trench material layer 1090 is lower than the bottom surface of the fin structure 1060. The remaining shallow trench material layer 1090 forms a shallow trench isolation structure 1110. Part of the silicon nitride liner formed on the sidewall surface and top surface of the fin structure 1060 is removed during the planarization and back etching process. The silicon nitride liner filling each recess 1070 is retained as a rigid insulating material layer 1071. The shortened silicon nanomaterial layer and the rigid insulating material layers 1071 adjacent to it on both sides form a channel structure 1120. Since the channel structure 1120 includes the rigid insulating material layer 1071, its bending stiffness is greater than that of the aforementioned silicon nanomaterial layer 1021.

[0115] See next Figure 10hA pseudo-gate structure 1130 is formed across the fin structure 1060. Then, adjacent source / drain regions can be formed on both sides of the pseudo-gate structure 1130, and then the pseudo-gate structure 1130 is removed.

[0116] See next Figure 10i After removing the pseudo gate structure 1130, a wet etching process is used to selectively remove the germanium-silicon nanomaterial layer 1022 to release the channel structure 1120. Since the bending stiffness of the channel structure 1120 is increased, the channel structure 1120 will not bend or deform or have adhesion problems when the channel structure 1120 is released by the wet etching process.

[0117] See next Figure 10j An isotropic dry etching process is used to remove the rigid insulating material layer 1071 in the channel structure 1120, thereby obtaining the silicon nanochannel 1140, ensuring that the silicon nanochannel 1140 will not bend or deform again or have adhesion problems.

[0118] See next Figure 10k A gate structure 1150 is formed across the fin structure 1060, the gate structure 1150 surrounds the silicon nanochannel 1140, and the alternative gate structure 1150 includes a dielectric layer 1151 and a gate electrode 1152.

[0119] The above embodiments pertain to the fabrication process of long-channel GAAFET devices. Before entering the shallow trench isolation structure fabrication process, [the following is used:] ... Figure 10d The process shown shortens the channel material layer in the Y-axis direction to form recesses on both sides. This allows for the filling of each recess with a rigid insulating material layer whose Young's modulus is greater than that of the channel material layer during the subsequent shallow trench isolation structure formation process. Consequently, during the subsequent nanochannel release, issues such as nanochannel bending deformation and localized adhesion between adjacent nanochannels are effectively avoided. This improves the performance and yield of the semiconductor device while significantly reducing the process complexity of this embodiment because it does not alter the original long-channel GAAFET device processes. Furthermore, the rigid insulating material layer can be removed in subsequent steps, thus preventing the introduction of channel impurities or impact on channel stress.

[0120] This application also provides a semiconductor structure formed based on the aforementioned formation method, the semiconductor structure comprising:

[0121] Substrate;

[0122] A fin structure located on the substrate, the fin structure extending along a first direction;

[0123] Multiple channel structures are spaced apart in the fin structure. Each channel structure includes a channel material layer and a rigid insulating material layer located on both sides of the channel material layer and adjacent to the channel material layer. The Young's modulus of the rigid insulating material layer is greater than that of the channel material layer.

[0124] For example, the rigid insulating material layer has a length of 1 to 10 nm in the second direction, which is perpendicular to the first direction.

[0125] For example, the channel material layer is a semiconductor material containing silicon, and the rigid insulating material layer is one or a combination of silicon nitride and silicon carbide.

[0126] In some exemplary embodiments, the semiconductor structure further includes a gate structure spanning the fin structure, the gate structure surrounding each of the channel material layers.

[0127] Accordingly, this application also provides an electronic device, which includes any of the semiconductor structures described above in the embodiments of this application.

[0128] Because semiconductor structures offer superior performance, and the electronic device employs such a structure, its performance is correspondingly improved. The electronic device can be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or it can be an intermediate product incorporating the semiconductor device, such as a motherboard with the semiconductor structure.

[0129] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate and a fin structure extending on the substrate along a first direction; the fin structure including alternating stacked layers of channel material and sacrificial material. The channel material layer of the fin structure is shortened along the second direction to form recesses on both sides of the channel material layer, wherein the second direction is perpendicular to the first direction; A rigid insulating material layer is formed to fill the recess, wherein the Young's modulus of the rigid insulating material layer is greater than that of the channel material layer; A pseudo-gate structure is formed across the fin structure, and the pseudo-gate structure is removed, followed by the removal of the sacrificial material layer.

2. The method according to claim 1, characterized in that, The shortening process of the channel material layer of the fin structure along the second direction includes: The fin structure is subjected to isotropic selective etching along the second direction; the selective etching rate on the channel material layer is greater than the etching rate on the sacrificial material layer.

3. The method according to claim 2, characterized in that, The selective etching selectivity ratio for the channel material layer and the sacrificial material layer is greater than 2.

4. The method according to claim 1, characterized in that, The depth of the recess in the second direction is 1 to 10 nm.

5. The method according to claim 1, characterized in that, The rigid insulating material layer that fills the recess includes: After the shortening process, a liner is deposited on the substrate; the Young's modulus of the liner is greater than that of the channel material layer, and the deposition thickness of the liner on the substrate surface is greater than half the thickness of the channel material layer in the vertical direction. Remove part of the liner covering the outer surface of the fin structure, and retain part of the liner filling the recess as the rigid insulating material layer.

6. The method according to claim 5, characterized in that, The removal of the portion of the liner covering the outer surface of the fin structure includes: A shallow groove material layer is formed on the liner, the top surface of the shallow groove material layer being higher than the top surface of the fin structure; The shallow trench material layer is planarized, and then the shallow trench material layer is etched back after planarization until the top surface of the remaining shallow trench material layer is lower than the bottom surface of the fin structure, so that the remaining shallow trench material layer forms a shallow trench isolation structure; wherein, a portion of the liner covering the outer surface of the fin structure is removed during the planarization and the back etching process.

7. The method according to claim 1, characterized in that, The substrate provided includes: An initial substrate is provided, on which a superlattice structure is formed, the superlattice structure comprising alternating stacked channel material layers and sacrificial material layers; The superlattice structure is patterned to form the substrate.

8. The method according to any one of claims 1 to 7, characterized in that, After removing the sacrificial material layer, the method further includes: The rigid insulating material layers on both sides of the channel material layer are removed using an isotropic dry etching process; A gate structure is formed across the fin structure, the gate structure surrounding the channel material layer.

9. The method according to claim 1, characterized in that, The rigid insulating material layer includes one or a combination of two of silicon nitride and silicon carbide.

10. The method according to claim 1, characterized in that, The removal of the sacrificial material layer includes removing the sacrificial material layer using a wet etching process.

11. The method according to claim 1, characterized in that, The channel material layer is a first semiconductor material containing silicon, and the sacrificial material layer is a second semiconductor material containing germanium silicon.

12. A semiconductor structure, characterized in that, Formed using any one of claims 1 to 11, comprising: Substrate; A fin structure located on the substrate, the fin structure extending along a first direction; Multiple channel structures are spaced apart in the fin structure. Each channel structure includes a channel material layer and a rigid insulating material layer located on both sides of the channel material layer and adjacent to the channel material layer. The Young's modulus of the rigid insulating material layer is greater than that of the channel material layer.

13. The semiconductor structure according to claim 12, characterized in that, The rigid insulating material layer has a length of 1 to 10 nm in the second direction, which is perpendicular to the first direction.

14. The semiconductor structure according to claim 12, characterized in that, Also includes: A gate structure spanning the fin structure, the gate structure surrounding each of the channel material layers.

15. An electronic device, characterized in that, The electronic device includes a semiconductor structure formed using the method described in any one of claims 1 to 11.

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