All-around gate field-effect transistor and its fabrication method and manufacturing equipment

Abstract

This application provides an all-around gate field-effect transistor and its fabrication method and apparatus. The fabrication method includes the following steps: providing a preform, the preform including a substrate and structural units disposed on the substrate, the structural units including a stacked structure and a functional structure, the stacked structure being located between the functional structure and the substrate, the stacked structure including alternating channel layers and sacrificial layers in a first direction, and forming an amorphous film layer on the side of the stacked structure; converting the amorphous film layer into a monocrystalline film layer using an annealing process; and growing a monocrystalline portion in the monocrystalline film layer to obtain a monocrystalline source / drain. This significantly reduces the generation of defects during the formation of the monocrystalline source / drain, and the monocrystalline source / drain can provide stress to the channel layer, thereby improving the carrier mobility of the all-around gate field-effect transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a fully all-around gate field-effect transistor and its fabrication method and manufacturing equipment. Background Technology

[0002] In a traditional gate all-around field effect transistor (GAAFET) integration process, the source and drain electrodes need to be grown in the source-drain region. Typically, the difference in lattice constants between the source and drain materials is used to generate compressive stress in the channel direction, thereby improving the carrier mobility in the GAAFET. GAAFETs include a stacked structure, with internal spacers on both sides of the sacrificial layer to prevent short circuits between the gate and the source / drain. Due to the presence of these internal spacers, the sides of the stacked structure to which the source and drain electrodes are attached during growth are not completely single-crystal interfaces. Therefore, a large number of defects are usually generated during the growth of the source and drain electrodes, making it impossible to provide compressive stress to the channel. Taking a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) as an example, if the source and drain electrodes do not provide pressure to the channel, it will affect the hole mobility in the PMOSFET, thus affecting the performance of the PMOSFET. Summary of the Invention

[0003] This application provides a fully all-around gate field-effect transistor that can reduce source-drain-gate growth defects, as well as its fabrication method and manufacturing equipment.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a fully all-around gate field-effect transistor, the method comprising the following steps:

[0005] A prefabricated body is provided, the prefabricated body comprising a base and structural units stacked in a first direction, the structural units comprising a stacked structure and a functional structure in the first direction, the stacked structure being located between the functional structure and the base, the stacked structure comprising a channel layer and a sacrificial layer alternately disposed in the first direction, the sacrificial layer comprising a sacrificial portion and an internal isolation portion, the internal isolation portion being disposed on the side of the sacrificial portion in a second direction different from the first direction;

[0006] The preform is pre-cleaned;

[0007] An amorphous film layer is formed on the side surface and internal isolation portion of the channel layer in the second direction, on the side surface of the channel layer that is opposite to the sacrificial portion in the second direction.

[0008] An annealing process is used to convert the amorphous film layer on the stacked structure into a monocrystalline film layer;

[0009] Single crystal portions are grown in the single crystal film layer to obtain single crystal source and drain electrodes.

[0010] First, an amorphous film layer is formed on the side of the channel layer in the second direction and on the side of the internal isolation portion away from the sacrificial portion in the second direction. Then, the amorphous film layer is transformed into a monocrystalline film layer through an annealing process. Finally, a monocrystalline portion is grown on the monocrystalline film layer to form a monocrystalline source / drain. Since a monocrystalline film layer is grown on the interface of the stacked structure to which the monocrystalline portion is attached during the growth process, the generation of defects during the formation of the monocrystalline source / drain is greatly reduced. The monocrystalline source / drain can provide stress to the channel layer, thereby improving the carrier mobility of the all-around gate field-effect transistor.

[0011] Pre-cleaning the preform before forming an amorphous film layer on the stacked structure reduces the natural oxidation of oxides and impurities at the epitaxial growth interface, which helps to achieve defect-free epitaxial growth of the source and drain regions of the all-around gate field-effect transistor and ensures the performance of the prepared transistor.

[0012] According to the first aspect, in one possible implementation of this application, the number of structural units is at least two, a groove is formed between each pair of adjacent structural units, the substrate includes a first interface disposed toward the groove, the side of the channel layer in the second direction is a second interface disposed toward the groove, the second interface is disposed toward the groove, the internal isolation portion includes a third interface disposed toward the groove, and the first interface, the second interface and the third interface form at least a portion of the side of the groove.

[0013] Because trenches exist between adjacent structural units, when fabricating a fully all-around gate field-effect transistor, an amorphous film layer can first be formed on the side of the trench, transforming the amorphous film layer into a monocrystalline film layer, and then a monocrystalline source / drain electrode can be grown on the monocrystalline film layer. The monocrystalline thin film interface on the trench is conducive to the growth of the monocrystalline source / drain electrode, thereby achieving defect-free source / drain electrode growth.

[0014] According to the first aspect, in one possible implementation of this application, the number of channel layers is at least two, and the formation of an amorphous film layer on the side of the channel layer in the second direction and on the side of the internal isolation portion away from the sacrificial portion in the second direction includes forming the amorphous film layer on the second interface using an epitaxial growth process; merging the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer, and converting the amorphous film layer on the stacked structure into a monocrystalline film layer using an annealing process, including converting the continuous amorphous film layer into a monocrystalline film layer using an annealing process.

[0015] Epitaxial growth can be selectively performed. By selectively forming an amorphous film layer on the side of the channel layer, merging the discontinuous amorphous film layers on at least two channel layers into a continuous amorphous film layer, and then converting the continuous amorphous film layer into a single crystal film layer, it is possible to grow a high-quality single crystal epitaxial film on the inner wall of the channel.

[0016] According to a first aspect, in one possible implementation of this application, the preparation method further includes forming a single-crystal film layer on the first interface using the epitaxial growth process; merging the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer further includes connecting the continuous amorphous film layer to the single-crystal film layer on the first interface; growing a single-crystal portion on the single-crystal film layer to obtain a single-crystal source / drain electrode includes growing a single-crystal portion on the single-crystal film layers on the first interface, the second interface, and the third interface.

[0017] Single-crystal portions are grown on the single-crystal film layers of the first, second, and third interfaces. That is, the interfaces that the single-crystal portions contact are all single-crystal structure interfaces, which further helps to reduce defects in the growth process of single-crystal source and drain electrodes and improves the quality of single-crystal source and drain electrodes.

[0018] According to a first aspect, in one possible implementation of this application, the formation of an amorphous film layer on the side of the trench layer in the second direction and on the side of the internal isolation portion facing away from the sacrificial portion in the second direction includes forming an amorphous film layer on the second interface, the third interface, the side of the functional structure facing away from the substrate, and the side of the functional structure facing the trench using a deposition process; the conversion of the amorphous film layer on the stacked structure into a monocrystalline film layer using an annealing process includes converting the amorphous film layer on the second interface and the third interface into a monocrystalline film layer; after converting the amorphous film layer on the second interface and the third interface into a monocrystalline film layer, the preparation method further includes removing the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench.

[0019] According to the first aspect, in one possible implementation of this application, the step of forming an amorphous film layer on the second interface, the third interface, the side of the functional structure facing away from the substrate, and the side of the functional structure facing the trench using a deposition process further includes forming an amorphous film layer on the first interface using a deposition process. The step of converting the amorphous film layer on the second interface and the third interface into a monocrystalline film layer further includes converting the amorphous film layer on the first interface into a monocrystalline film layer.

[0020] According to a first aspect, in one possible implementation of this application, the substrate includes a substrate and a dielectric layer stacked in a first direction, the dielectric layer being located between the substrate and the stacked structure, the first interface being located on the side of the dielectric layer facing the trench, the step of forming an amorphous film layer on the second interface, the third interface, the side of the functional structure away from the substrate, and the side of the functional structure facing the trench using a deposition process further includes forming an amorphous film layer on the first interface using a deposition process, and the step of removing the amorphous film layer on the side of the functional structure away from the substrate and the side of the functional structure facing the trench further includes removing the amorphous film layer on the first interface.

[0021] According to a first aspect, in one possible implementation of this application, removing the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench includes using a back-etching process to remove the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench to form an intermediate structure. After removing the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench, and before growing a single crystal portion on the single crystal film layer to obtain a single crystal source / drain electrode, the fabrication method further includes pre-cleaning the intermediate structure.

[0022] Pre-cleaning the intermediate structure before forming the source and drain electrodes on the single crystal film reduces the oxides and impurities generated by oxidation at the epitaxial growth interface, which helps to achieve defect-free epitaxial growth of the source and drain regions of the all-around gate field-effect transistor.

[0023] According to the first aspect, in one possible implementation of this application, the first interface is Si(100) and the second interface is Si(110).

[0024] According to the first aspect, in one possible implementation of this application, the sacrificial portion includes at least one of Si, Ge, compound semiconductor, and alloy semiconductor.

[0025] According to the first aspect, in one possible implementation of this application, the amorphous film layer includes one of Si, Ge, compound semiconductor, and alloy semiconductor.

[0026] According to the first aspect, in one possible implementation of this application, the functional structure includes a functional part and a main isolation part, the functional part is disposed on the side of the stacked structure away from the substrate, the main isolation part covers the functional part, and the functional part is either a gate or a dummy gate.

[0027] According to the first aspect, in one possible implementation of this application, when the functional part is a dummy gate, the fabrication method further includes removing the dummy gate; forming a gate at the original position of the dummy gate, the gate being disposed on the side of the stacked structure away from the substrate, and the main isolation portion covering the gate.

[0028] Secondly, embodiments of this application provide a fully all-around gate field-effect transistor, which is fabricated using the fabrication method described in the first aspect.

[0029] Thirdly, embodiments of this application provide a fully all-around gate field-effect transistor, including a substrate, a structural unit, and a monocrystalline source and drain. The structural unit and the substrate are stacked along a first direction. The structural unit includes a stacked structure and a functional structure stacked along the first direction. The stacked structure is located between the functional structure and the substrate. The stacked structure includes a sacrificial layer and a channel layer alternately disposed along the first direction. The sacrificial layer includes a sacrificial portion and an internal isolation portion. The internal isolation portion is disposed on the side of the sacrificial portion in a second direction different from the first direction. The monocrystalline source and drain are attached to the side of the channel layer in the second direction, and the monocrystalline source and drain are attached to the side of the internal isolation portion in the second direction opposite to the sacrificial portion.

[0030] According to a third aspect, in one possible implementation of this application, the number of structural units is at least two, a trench is formed between two adjacent structural units, the substrate includes a first interface disposed toward the trench, the side of the trench layer in the second direction is a second interface, the second interface is disposed toward the trench, the internal isolation portion includes a third interface disposed toward the trench, the first interface, the second interface and the third interface surround at least a portion of the side of the trench, and the single crystal source and drain are attached to the first interface, the second interface and the third interface.

[0031] According to a third aspect, in one possible implementation of this application, the sacrificial portion includes at least one of Si, Ge, compound semiconductor, and alloy semiconductor.

[0032] According to a third aspect, in one possible implementation of this application, the single-crystal source and drain electrodes include at least one of Si, Ge, compound semiconductors, and alloy semiconductors.

[0033] Fourthly, embodiments of this application provide a manufacturing apparatus for fabricating a preform into a gate-all-around field-effect transistor. The preform includes a substrate and structural units stacked in a first direction. The structural units include a stacked structure and a functional structure in the first direction. The stacked structure is located between the functional structure and the substrate. The stacked structure includes a channel layer and a sacrificial layer alternately disposed in the first direction. The sacrificial layer includes a sacrificial portion and an internal isolation portion. The internal isolation portion is disposed on the side of the sacrificial portion in a second direction different from the first direction. The manufacturing apparatus includes a pre-cleaning device, a growth device, and an annealing device. The pre-cleaning device is used to pre-clean the preform. The growth device is used to form an amorphous film layer on the side of the channel layer in the second direction and on the side of the internal isolation portion facing away from the sacrificial portion in the second direction.

[0034] The annealing device is used to convert the amorphous film layer on the stacked structure into a monocrystalline film layer.

[0035] The growth apparatus is also used to grow single crystal portions in the single crystal film layer to obtain single crystal source and drain electrodes.

[0036] The manufacturing equipment provided in this application first forms an amorphous film layer on the side of the channel layer in the second direction and the side of the internal isolation portion away from the sacrificial portion in the second direction using a growth device. Then, the amorphous film layer is converted into a monocrystalline film layer using an annealing device. Finally, a monocrystalline portion is grown on the monocrystalline film layer using a growth device to form a monocrystalline source and drain. This reduces the generation of defects during the formation of the monocrystalline source and drain. The monocrystalline source and drain can provide stress to the channel layer, thereby improving the carrier mobility of the all-around gate field-effect transistor.

[0037] The pre-cleaning device pre-cleans the preform before forming an amorphous film layer on the stacked structure, which reduces the natural oxidation of oxides and impurities on the epitaxial growth interface. This helps to achieve defect-free epitaxial growth of the source and drain regions of the all-around gate field-effect transistor, ensuring the performance of the prepared transistor.

[0038] According to the fourth aspect, in one possible implementation of this application, the number of structural units is at least two, a groove is formed between each pair of adjacent structural units, the substrate includes a first interface disposed toward the groove, the side of the channel layer in the second direction is a second interface disposed toward the groove, the second interface is disposed toward the groove, the internal isolation portion includes a third interface disposed toward the groove, and the first interface, the second interface and the third interface form at least a portion of the side of the groove.

[0039] The number of channel layers is at least two.

[0040] The growth apparatus is used to: form the amorphous film layer on the second interface and the monocrystalline film layer on the first interface using an epitaxial growth process; merge the amorphous film layers on the at least two channel layers at the first interface and the third interface to form a continuous amorphous film layer, wherein the continuous amorphous film layer is connected to the monocrystalline film layer.

[0041] According to the fourth aspect, in one possible implementation of this application, the growth apparatus is further configured to form a monocrystalline film layer on the first interface using the epitaxial growth process, and the step of merging the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer further includes connecting the continuous amorphous film layer to the monocrystalline film layer on the first interface.

[0042] According to the fourth aspect, in one possible implementation of this application, the number of structural units is at least two, a groove is formed between each pair of adjacent structural units, the substrate includes a first interface disposed toward the groove, the side of the channel layer in the second direction is a second interface disposed toward the groove, the second interface is disposed toward the groove, the internal isolation portion includes a third interface disposed toward the groove, and the first interface, the second interface and the third interface form at least a portion of the side of the groove.

[0043] The growth apparatus includes a first growth module and a second growth module. The first growth module is used to form an amorphous film layer on the first interface, the second interface, the third interface, the side of the functional structure facing away from the substrate, and the side of the functional structure facing the trench using a deposition process.

[0044] The manufacturing equipment further includes a removal device for removing the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench to form an intermediate structure.

[0045] The pre-cleaning device is also used to pre-clean the intermediate structure.

[0046] The second growth module is used to grow single crystal portions in the single crystal film layer to obtain single crystal source and drain electrodes.

[0047] According to the fourth aspect, in one possible implementation of this application, the first growth module is further configured to form an amorphous film layer on the first interface, and the annealing device is further configured to convert the amorphous film layer on the first interface into a monocrystalline film layer.

[0048] According to the fourth aspect, in one possible implementation of this application, the substrate includes a substrate and a dielectric layer stacked in a first direction, the dielectric layer being located between the substrate and the stacked structure, the first interface being located on the side of the dielectric layer facing the trench, the first growth module being further configured to form an amorphous film layer on the first interface, and the removal device being further configured to remove the amorphous film layer on the first interface. Attached Figure Description

[0049] Figure 1 A schematic diagram of the structure of a circuit device provided in one embodiment of this application;

[0050] Figure 2 A schematic diagram of the structure of a fully all-around gate field-effect transistor provided in one embodiment of this application;

[0051] Figure 3 A schematic diagram of the structure of a fully all-around gate field-effect transistor provided in one embodiment of this application;

[0052] Figure 4a A schematic diagram of the structure of a fully all-around gate field-effect transistor provided in one embodiment of this application;

[0053] Figure 4b A schematic diagram of the structure of a fully all-around gate field-effect transistor provided in one embodiment of this application;

[0054] Figure 5 A schematic flowchart illustrating a method for fabricating a fully all-around gate field-effect transistor according to the first embodiment of this application;

[0055] Figure 6 This is a schematic diagram of the structure of the preform provided in the first embodiment of this application;

[0056] Figure 7 for Figure 5 A schematic diagram of the structure formed by step S104 in the preparation method shown;

[0057] Figure 8 for Figure 5 A schematic diagram of the structure formed by step S106 of the preparation method shown;

[0058] Figure 9 for Figure 5 A schematic diagram of the structure formed by step S108 of the preparation method shown;

[0059] Figure 10 A structural block diagram of a manufacturing apparatus for a fully all-around gate field-effect transistor provided in the first embodiment of this application;

[0060] Figure 11A schematic flowchart illustrating a method for fabricating a fully all-around gate field-effect transistor according to the second embodiment of this application;

[0061] Figure 12 for Figure 11 A schematic diagram of the structure formed by S206 in the preparation method shown;

[0062] Figure 13a for Figure 11 A schematic diagram of the structure formed by S208 in the preparation method shown;

[0063] Figure 13b for Figure 11 A schematic diagram of the structure formed in step S210 of the preparation method shown;

[0064] Figure 13c for Figure 11 A schematic diagram of the structure formed in step S212 of the preparation method shown;

[0065] Figure 14 A structural block diagram of a manufacturing apparatus for a fully all-around gate field-effect transistor provided for the second embodiment of this application;

[0066] Figure 15 A schematic flowchart illustrating a method for fabricating a fully all-around gate field-effect transistor according to the third embodiment of this application;

[0067] Figure 16 for Figure 15 A schematic diagram of the structure formed by S306 in the preparation method shown;

[0068] Figure 17 for Figure 15 A schematic diagram of the structure formed by S308 in the preparation method shown;

[0069] Figure 18a for Figure 15 A schematic diagram of the structure formed in step S310 of the preparation method shown;

[0070] Figure 18b for Figure 15 A schematic diagram of the structure formed in step S312 of the preparation method shown;

[0071] Figure 19 A structural block diagram of a manufacturing apparatus for a fully all-around gate field-effect transistor provided in the third embodiment of this application;

[0072] Figure 20 A schematic flowchart illustrating a method for fabricating a fully all-around gate field-effect transistor according to the fourth embodiment of this application;

[0073] Figure 21This is a schematic diagram of the structure of the preform provided in the fourth embodiment of this application;

[0074] Figure 22 for Figure 20 A schematic diagram of the structure formed by step S506 of the preparation method shown;

[0075] Figure 23 for Figure 20 A schematic diagram of the structure formed by step S508 of the preparation method shown;

[0076] Figure 24 for Figure 20 A schematic diagram of the structure formed in step S510 of the preparation method shown;

[0077] Figure 25 for Figure 20 A schematic diagram of the structure formed in step S514 of the preparation method shown;

[0078] Figure 26 A schematic flowchart illustrating a method for fabricating a fully all-around gate field-effect transistor according to the fourth embodiment of this application;

[0079] Figure 27 for Figure 26 A schematic diagram of the structure formed by S606 in the preparation method shown;

[0080] Figure 28 for Figure 26 A schematic diagram of the structure formed by S608 of the preparation method shown. Detailed Implementation

[0081] In the integration process of a gate all-around field-effect transistor (GAAFET), epitaxial growth (EPI) is required to form the source and drain regions. Taking the growth of SiGe source and drain as an example, the difference in lattice constants between Ge and Si is used to generate compressive stress in the channel direction, thereby improving the carrier mobility in the GAAFET. For example, at room temperature, the lattice constants of Ge and Si are... and There is approximately 4% lattice mismatch between Ge and Si. The GAA structure includes a stacked structure comprising a Si channel layer and a sacrificial layer. The sacrificial layer includes a SiGe sacrificial portion and inner spacers located on either side of the SiGe sacrificial portion to prevent short circuits between the gate and source / drain. Based on this structure, the source / drain region is defined by the inner spacers, the sides of the Si channel layer, and a portion of the exposed Si substrate. Due to the presence of the inner spacers, the sides of the stacked structure to which the source / drain grows are not completely single-crystal interfaces. Therefore, a large number of defects are typically generated during the growth of the source / drain, preventing the provision of compressive stress to the channel. Taking a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) as an example, if the source / drain does not provide pressure to the channel, it will affect the hole mobility in the PMOSFET, thus affecting the performance of the PMOSFET.

[0082] Based on this, this application provides a fully all-around gate field-effect transistor with reduced source-drain growth defects, as well as its fabrication method and manufacturing equipment.

[0083] Please see Figure 1 This application provides a circuit device 3, including a substrate 2 and an all-around gate field-effect transistor 1 disposed on the substrate 2. The substrate 2 can be a printed circuit board, a chip, or other carrier capable of supporting the all-around gate field-effect transistor 1. Circuitry can be disposed on the substrate 2. The all-around gate field-effect transistor 1 can be a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) or an N-type metal-oxide-semiconductor field-effect transistor. The circuit device 3 can include various other devices and components, such as other types of devices, including additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, SRAM, and / or other logic circuits.

[0084] Please see Figure 2This application provides an all-around gate field-effect transistor 1, which includes a substrate 101, a structural unit 103, and a monocrystalline source / drain 105. The structural unit 103 and the substrate 101 are stacked in a first direction. The structural unit 103 includes a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the substrate 101. The stacked structure 31 includes a channel layer 311 and a sacrificial layer 313 alternately arranged in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133, and the internal isolation portion 3133 is disposed on the side of the sacrificial portion 3131 in a second direction different from the first direction. The monocrystalline source / drain 105 is attached to the side of the channel layer 311 in the second direction, and the monocrystalline source / drain 105 is attached to the side of the internal isolation portion 3133 in the second direction away from the sacrificial portion 3131. The first direction can be as follows: Figure 2 The Y direction is shown, and the second direction can be as follows: Figure 2 The X direction is shown.

[0085] The structure of stacked structure 31 is similar to that of superlattice structure.

[0086] The single-crystal source-drain 105 can reduce parasitic resistance and provide the compressive stress required by the channel layer 311, thereby improving the carrier mobility in the all-around gate field-effect transistor and thus significantly improving the device performance of the all-around gate field-effect transistor 1.

[0087] In this embodiment, in the first direction, the layer of the stacked structure 31 closest to the functional structure 33 is the channel layer 311. It can be understood that, in the first direction, the layer of the stacked structure 31 closest to the functional structure 33 can also be the sacrificial layer 313.

[0088] Please see Figure 3 In one embodiment of this application, a fully all-around gate field-effect transistor 1 is provided, wherein the number of structural units 103 can be multiple, and the number of single-crystal source-drain electrodes 105 can be multiple. In a first direction, one of two adjacent single-crystal source-drain electrodes 105 can serve as a source, and the other of two adjacent single-crystal source-drain electrodes 105 can serve as a drain.

[0089] Multiple structural units 103 are spaced apart on a substrate 101 along a second direction, and a trench 100 is formed between each pair of adjacent structural units 103. The substrate 101 includes a first interface 1011 facing the trench 100, a second interface 3111 on the side of the channel layer 311 in the second direction, the second interface 3111 facing the trench 100, and an internal isolation portion 3133 including a third interface 3135 facing the trench 100. The first interface 1011, the second interface 3111, and the third interface 3135 form at least a portion of the side surface of the trench 100. A single-crystal source / drain 105 is housed within the trench 100 and is attached to the first interface 1011, the second interface 3111, and the third interface 3135. The single-crystal source / drain 105 can also be attached to other areas of the trench 100, for example, the single-crystal source / drain 105 can also be attached to the side surface of the functional structure 33 facing the trench 100.

[0090] Since a trench 100 is provided between two adjacent structural units 103, when fabricating the all-around gate field-effect transistor 1, an amorphous film layer can first be formed on the side of the trench 100, then the amorphous film layer can be converted into a monocrystalline film layer, and then a monocrystalline material can be grown on the monocrystalline film layer to form a monocrystalline source / drain 105. The trench 100 guides the growth of the monocrystalline source / drain 105, which is beneficial to improving the growth quality of the monocrystalline source / drain 105.

[0091] For example, in some embodiments of this application, a monocrystalline film layer is formed on the first interface 1011, and an amorphous film layer is formed on the second interface 3111. Discontinuous amorphous film layers on multiple channel layers 311 are merged to form a continuous amorphous film layer; that is, an amorphous film layer is also formed on the side of the internal isolation portion 3133 facing away from the sacrificial portion 3131 in the second direction. The continuous amorphous film layer and the monocrystalline film layer are connected to form a complete crystal plane. Through an annealing process, the continuous amorphous film layer is transformed into a monocrystalline film layer by solid-state crystallization at the interface of the monocrystalline material on the side of the channel layer 311. A monocrystalline material is grown on the monocrystalline film layer to form a monocrystalline source / drain electrode 105. Because a monocrystalline film layer is formed first, and then a monocrystalline material is grown on the monocrystalline film layer to form the monocrystalline source / drain electrode 105, defects in the growth process of the monocrystalline source / drain electrode 105 are reduced. The single-crystal source-drain 105 can reduce parasitic resistance and provide the compressive stress required by the channel layer 311, thereby significantly improving the device performance of the all-around gate field-effect transistor 1.

[0092] In some embodiments of this application, the substrate 101 is a silicon (Si) substrate, the sacrificial portion 3131 is made of epitaxial germanium silicide (SiGe), the channel layer 311 is made of epitaxial Si, the single crystal source and drain 105 is made of single crystal SiGe, the first interface 1011 is made of Si (100), and the second interface 3111 is made of Si (110).

[0093] In some embodiments of this application, substrate 101 may include various layers, including conductive or insulating layers formed on a semiconductor substrate. Substrate 101 may include various doping configurations. For example, different doping profiles (e.g., n-wells, p-wells) may be formed on substrate 101 in regions designed for different device types (e.g., n-type GAA transistors, p-type GAA transistors). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 101 may have isolation components between regions providing different device types. Substrate 101 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 101 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 101 may optionally include an epitaxial layer (epi layer) that can be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and / or may have other suitable enhancement components.

[0094] In some embodiments of this application, either the channel layer 311 or the sacrificial portion 3131 may include at least one of Si, Ge (germanium), compound semiconductors, and alloy semiconductors. Compound semiconductors include silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors include SiGeC, SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof.

[0095] In some embodiments of this application, the internal isolation portion 3133 is typically SiO2. x C y N z , where x, y, and z can be zero.

[0096] In some embodiments of this application, the material of the single-crystal source / drain 105 includes at least one of Si, Ge (germanium), compound semiconductors, and alloy semiconductors. Compound semiconductors include silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors include SiGeC, SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The single-crystal source / drain 105 may also be doped with elements such as B; for example, the single-crystal source / drain 105 may be SiGe:B.

[0097] The channel layer 311 can be a nanosheet or a nanowire, and the sacrificial layer 313 can be a nanosheet or a nanowire.

[0098] The functional structure 33 includes a functional part 331 and a main isolation part 333. The functional part 331 is disposed on the side of the stacked structure 31 away from the substrate 101, and the main isolation part 333 covers the functional part 331. The functional part 331 is a gate or a dummy gate.

[0099] For some embodiments of this application, please refer to Figure 4a The substrate 101 includes a substrate 1013 and a dielectric layer 1015 stacked together, with the dielectric layer 1015 located between the structural unit 103 and the substrate 1013. The dielectric layer 1015 is used to reduce leakage current. The substrate 1013 can be made of Si, and the dielectric layer 1015 can be made of SiO2 or SiOCN. A first interface 1011 is provided on the side of the dielectric layer 1015 facing the trench 100. In this embodiment, in the first direction, the layer of the stacked structure 31 closest to the functional structure 33 is the channel layer 311. In one possible implementation, during fabrication, an amorphous film layer is first formed on the second interface 3111 by an epitaxial growth process, and then the discontinuous amorphous film layers on multiple channel layers 311 are merged to form a continuous amorphous film layer, that is, the internal isolation portion 3133 also forms an amorphous film layer on the side facing away from the sacrificial portion 3131 in the second direction. Through an annealing process, the continuous amorphous film layer is transformed into a single-crystal film layer by solid-state crystallization at the interface of the single-crystal material on the side of the channel layer 311. Single-crystal material is then grown on the single-crystal film layer to form a single-crystal source / drain 105. Since a single-crystal film layer is formed first, and then the single-crystal material is grown on the single-crystal film layer to form the single-crystal source / drain 105, defects during the growth process of the single-crystal source / drain 105 are reduced. The single-crystal source / drain 105 can reduce parasitic resistance and provide the compressive stress required by the channel layer 311, thereby significantly improving the device performance of the all-around gate field-effect transistor 1. In one possible implementation, during fabrication, an amorphous film layer is first formed at the first interface 1011, the second interface 3111, and the third interface 3135 through a deposition process. The amorphous film layers on the second interface 3111 and the third interface 3135 are then transformed into single-crystal film layers, and the amorphous film layer on the first interface 1011 is removed. Single crystal portions are then grown on the single crystal film layers on the second interface 3111 and the third interface 3135 to obtain single crystal source and drain electrodes.

[0100] Please see Figure 5 The first embodiment of this application provides a method for fabricating a fully all-around gate field-effect transistor 1, the method comprising the following steps.

[0101] S102, provides prefabricated body 300, please refer to Figure 6 The prefabricated body 300 includes a base 101 and structural units 103 stacked in a first direction. The structural unit 103 includes a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the base 101. The stacked structure 31 includes channel layers 311 and sacrificial layers 313 alternately arranged in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is disposed on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0102] S103, pre-cleaning the preform 300. Pre-cleaning the preform 300 reduces the formation of oxides and impurities from natural oxidation at the interface of the preform 300, which helps to achieve defect-free epitaxial growth of the source and drain regions of the all-around gate field-effect transistor, ensuring the performance of the fabricated transistor.

[0103] S104, please refer to Figure 7 An amorphous film layer 71 is formed on the side surface of the channel layer 311 in the second direction and on the side surface of the internal isolation portion 3133 away from the sacrificial portion 3131 in the second direction.

[0104] S106, please refer to Figure 8 The amorphous film layer 71 on the stacked structure 31 is transformed into a monocrystalline film layer 73 by annealing.

[0105] S108, please refer to Figure 9 A single crystal portion 75 is grown in the single crystal film layer 73 to obtain a single crystal source / drain electrode 105. The single crystal portion 75 is made of the same material as the single crystal film layer 73. Figure 9 The interface between the single crystal film layer 73 and the single crystal portion 75 shown is merely exemplary. The interfaces between the single crystal film layer 73 and the single crystal portion 75 in other figures in this document are also exemplary. During the fabrication process, there may not be an interface between the single crystal film layer 73 and the single crystal portion 75.

[0106] Since an amorphous film layer 71 is first formed on the side surface of the channel layer 311 in the second direction and on the side surface of the internal isolation portion 3133 away from the sacrificial portion 3131 in the second direction, and then the amorphous film layer 71 is transformed into a single crystal film layer 73 through an annealing process, and then a single crystal portion 75 is grown on the single crystal film layer 73 to form a single crystal source / drain 105, the generation of defects during the formation of the single crystal source / drain 105 is reduced. The single crystal source / drain 105 can provide stress to the channel layer 311, thereby improving the carrier mobility of the all-around gate field-effect transistor 1.

[0107] The material of the single-crystal portion 75 can be the same as the material of the single-crystal film layer 73. The concentration of each element in the material of the single-crystal portion 75 can be the same as or different from the concentration of the corresponding element in the material used to make the single-crystal film layer 73. For example, in one possible implementation, both the single-crystal portion 75 and the single-crystal film layer 73 are made of SiGe, but the concentration of Ge in the single-crystal portion 75 can be different from the concentration of Ge in the single-crystal film layer 73. For example, in one possible implementation, both the single-crystal portion 75 and the single-crystal film layer 73 are made of SiGe:B, that is, SiGe is doped with element B, and the doping concentration of B in the single-crystal portion 75 can be different from the doping concentration of B in the single-crystal film layer 73. For example, in one possible implementation, both the single-crystal portion 75 and the single-crystal film layer 73 are made of SiGe, the single-crystal portion 75 is doped with element B, but the single-crystal film layer 73 is not doped with element B.

[0108] In some embodiments of this application, both the single crystal portion 75 and the single crystal film layer 73 are SiGe, and the concentration of Ge in the single crystal film layer 73 may not be greater than the concentration of Ge in the single crystal portion 75.

[0109] Please refer to the following: Figure 10 The first embodiment of this application provides a manufacturing apparatus 400a for fabricating a preform 300 into a gate-all-around field-effect transistor 1. The preform 300 includes a substrate 101 and structural units 103 stacked in a first direction. The structural units 103 include a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the substrate 101. The stacked structure 31 includes a channel layer 311 and a sacrificial layer 313 alternately arranged in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is disposed on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0110] Manufacturing equipment 400a includes a pre-cleaning device 401, a growth device 402, and an annealing device 404.

[0111] The pre-cleaning device 401 is used to clean the preform 300.

[0112] The growth apparatus 402 is used to form an amorphous film layer 71 on the side surface and the internal isolation portion 3133 of the channel layer 311 in the second direction, on the side surface opposite to the sacrificial portion 3131 in the second direction. Please refer to [link / reference]. Figure 7 .

[0113] Annealing apparatus 404 is used to convert amorphous film layer 71 into monocrystalline film layer 73. Please refer to [link / reference]. Figure 8 .

[0114] The growth apparatus 402 is also used to grow a single crystal portion 75 on the single crystal film layer 73 to obtain a single crystal source / drain electrode 105. Please refer to [link to relevant documentation]. Figure 9 The single crystal portion 75 is made of the same material as the single crystal film layer 73.

[0115] Please see Figure 11 The second embodiment of this application provides a method for fabricating a fully all-around gate field-effect transistor 1, the method comprising the following steps.

[0116] S202, a preform 300 is provided. The structure of the preform 300 provided in the second embodiment may be the same as that of the preform 300 in the first embodiment. Please refer to [link / reference]. Figure 6 The prefabricated body 300 includes a base 101 and structural units 103 stacked in a first direction. The structural unit 103 includes a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the base 101. The stacked structure 31 includes alternating channel layers 311 and sacrificial layers 313 in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is located on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0117] The number of structural units 103 is at least two. A trench 100 is formed between each pair of adjacent structural units 103. The substrate 101 includes a first interface 1011 facing the trench 100, the side of the channel layer 311 in the second direction is a second interface 3111, the second interface 3111 is facing the trench 100, and the internal isolation portion 3133 includes a third interface 3135 facing the trench 100. The first interface 1011, the second interface 3111, and the third interface 3135 form at least a portion of the side of the trench 100. A single-crystal source / drain 105 is housed within the trench 100 and is attached to the first interface 1011, the second interface 3111, and the third interface 3135. The single-crystal source / drain 105 can also be attached to some other areas of the trench 100, for example, the single-crystal source / drain 105 can also be attached to the side of the functional structure 33 facing the trench 100.

[0118] In this embodiment, the substrate 101 is made of Si, the sacrificial portion 3131 is made of SiGe, the channel layer 311 is made of Si, the first interface 1011 can be Si(100), and the second interface 3111 can be Si(110). This application does not limit the first interface 1011 to Si(100), nor does it limit the second interface 3111 to Si(110). Different crystal forms can be grown on different crystal planes through the process. It is understood that this application does not limit the substrate 101 to Si, nor does it limit the sacrificial portion 3131 to SiGe, nor does it limit the channel layer 311 to Si. For specific materials, please refer to the foregoing.

[0119] S204, Pre-cleaning of preform 300. Pre-cleaning is a cleaning process performed on the surface of the structure, mainly to remove oxides and impurities that may exist at the interface due to natural growth caused by exposure to air.

[0120] S206, an amorphous film layer 71 is formed on the second interface 3111 and a monocrystalline film layer 73 is formed on the first interface 1011. Please refer to [link / reference]. Figure 12 .

[0121] In this embodiment, forming an amorphous film layer 71 on the second interface 3111 and a monocrystalline film layer 73 on the first interface 1011 includes forming the amorphous film layer 71 on the second interface 3111 and the monocrystalline film layer 73 on the first interface 1011 using an epitaxial growth process. The temperature range of the epitaxial growth process can be selected, but is not limited to, 300℃-500℃.

[0122] S208, at least two amorphous film layers 71 on the channel layers 311 are merged to form a continuous amorphous film layer 76. The continuous amorphous film layer 76 is connected to the single crystal film layer 73, forming a complete crystal plane within the trench 100. Please refer to [link to relevant documentation]. Figure 13a .

[0123] In this embodiment, a selective epitaxial growth process is used to merge the continuous amorphous film layer 76 at the second interface 3111 and the third interface 3135 of the trench 100 into a single continuous amorphous film layer 76. Because the continuous amorphous film layer 76 has amorphous properties and does not exhibit a preferred orientation during growth, it possesses good surface smoothness.

[0124] S210, the continuous amorphous film layer 76 is transformed into a single-crystal film layer 73 using an annealing process. Please refer to [link / reference]. Figure 13b .

[0125] In this embodiment, an annealing process is used to utilize the solid-state crystallization of the single-crystal Si interface on the side of the channel layer 311, thereby transforming the continuous amorphous film layer 76 into a single-crystal film layer 73.

[0126] Annealing, or annealing treatment, mainly refers to a heat treatment process in which materials are exposed to high temperatures for an extended period followed by cooling. Its primary purposes are stress relief, increasing material ductility and toughness, and creating unique microstructures. For example, treating a continuous amorphous film at 76°C for a period followed by cooling can transform the amorphous material into a single crystal. The specific high-temperature treatment and cooling times will vary depending on the chosen annealing process.

[0127] The annealing process can be one of in-situ heat treatment (RTP), flash annealing, or laser annealing. It is understood that this application does not limit the type of annealing process, as long as it achieves the purpose of converting the amorphous film layer into a monocrystalline film layer through high-temperature treatment.

[0128] Rapid heat treatment is a heat treatment method that involves heating up very quickly and holding the temperature for a very short time.

[0129] Flash annealing: another leading option in millisecond annealing, which can heat the entire workpiece. Millisecond annealing refers to an annealing process where the annealing time reaches the millisecond level.

[0130] Laser annealing uses a laser to scan the entire workpiece, generating heat only in a small area for a very short time.

[0131] S212, A single-crystal portion 75 is grown on the single-crystal film layer 73 to obtain a single-crystal source / drain electrode 105. Please refer to [link / reference]. Figure 13c .

[0132] In this embodiment, growing a single crystal portion 75 on a single crystal film layer 73 to obtain a single crystal source / drain electrode 105 includes growing the single crystal portion 75 on the single crystal film layer 73 and the single crystal film layer 73 using an epitaxial growth process.

[0133] Because a single-crystal film layer 73 is first formed on the side of the trench 100, defects in the single-crystal source / drain 105 during growth or formation are reduced. The defect-free or low-defect single-crystal source / drain 105 can reduce parasitic resistance and provide the compressive stress required by the channel layer 311, thereby significantly improving device performance.

[0134] The functional structure 33 includes a functional part 331 and a main isolation part 333. The functional part 331 is disposed on the side of the stacked structure 31 away from the substrate 101, and the main isolation part 333 covers the functional part 331. The functional part 331 is either a gate or a dummy gate.

[0135] When the functional part 331 is a dummy gate, the fabrication method further includes removing the dummy gate; forming a gate at the original position of the dummy gate, the gate being disposed on the side of the stacked structure 31 away from the substrate 101, and the main isolation part 333 covering the gate.

[0136] Please see Figure 14This application provides a second embodiment of a manufacturing apparatus 400b for fabricating a preform 300 into a gate-all-around field-effect transistor 1. The preform 300 includes a substrate 101 and structural units 103 stacked in a first direction. The structural units 103 include a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the substrate 101. The stacked structure 31 includes a channel layer 311 and a sacrificial layer 313 alternately arranged in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is disposed on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0137] The number of structural units 103 is at least two, and a groove 100 is formed between each pair of adjacent structural units 103. The base 101 includes a first interface 1011 facing the groove 100. The side of the channel layer 311 in the second direction is a second interface 3111, which faces the groove 100. The internal isolation portion 3133 includes a third interface 3135 facing the groove 100. The first interface 1011, the second interface 3111, and the third interface 3135 form at least a portion of the side of the groove 100. The number of channel layers 311 is at least two.

[0138] Manufacturing equipment 400b includes a pre-cleaning device 401, a growth device 402, and an annealing device 404.

[0139] The pre-cleaning device 401 is used to pre-clean the precast body 300.

[0140] Growth apparatus 402 includes a first growth module 4021 and a second growth module 4023. The first growth module 4021 is an epitaxial growth apparatus. The first growth module 4021 is used to form an amorphous film layer 71 on the second interface 3111 and a single-crystal film layer 73 on the first interface 1011 using epitaxial growth processes. (See also...) Figure 12 The first growth module 4021 is also used to merge at least two amorphous film layers 71 on the channel layers 311 to form a continuous amorphous film layer 76, the continuous amorphous film layer 76 being connected to the single crystal film layer 73. (See also...) Figure 13a .

[0141] Annealing apparatus 404 is used to convert continuous amorphous film layer 76 into single crystal film layer 73. Please refer to [link / reference]. Figure 13b .

[0142] The second growth module 4023 is used to grow a single crystal portion 75 on the single crystal film layer 73 to obtain a single crystal source / drain electrode 105. Please refer to [link / reference]. Figure 13c The single crystal portion 75 is made of the same material as the single crystal film layer 73.

[0143] In some embodiments of this application, one of the first growth module 4021 and the second growth module 4023 may be omitted. That is, the same growth module is used to form an amorphous film layer 71 on the second interface 3111 and a monocrystalline film layer 73 on the first interface 1011. The amorphous film layers 71 on at least two channel layers 311 are merged at the first interface 1011 and the third interface 3135 to form a continuous amorphous film layer 76.

[0144] Please see Figure 15 The third embodiment of this application also provides a method for fabricating a fully all-around gate field-effect transistor 1, the method comprising the following steps.

[0145] S302, a preform 300 is provided. The structure of the preform 300 provided in the third embodiment may be the same as the structure of the preform 300 in the first embodiment. Please refer to [link / reference]. Figure 6 The prefabricated body 300 includes a base 101 and structural units 103 stacked in a first direction. The structural unit 103 includes a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the base 101. The stacked structure 31 includes alternating channel layers 311 and sacrificial layers 313 in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is located on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0146] The number of structural units 103 is at least two. A groove 100 is formed between each pair of adjacent structural units 103. The substrate 101 includes a first interface 1011 facing the groove 100, the side of the channel layer 311 in the second direction is a second interface 3111, the second interface 3111 is facing the groove 100, and the internal isolation portion 3133 includes a third interface 3135 facing the groove 100. The first interface 1011, the second interface 3111 and the third interface 3135 form at least a portion of the side of the groove 100.

[0147] In this embodiment, the material of the layer of substrate 101 closest to the stacked structure 31 is the same as the material of the channel layer 311. The material of substrate 101 is Si, the sacrificial portion 3131 is SiGe, and the material of channel layer 311 is Si. It is understood that the material of substrate 101 is not limited to Si, the material of sacrificial portion 3131 is SiGe, and the material of channel layer 311 is not limited to Si. For specific materials, please refer to the foregoing.

[0148] In this embodiment, the first interface 1011 can be Si (100), and the second interface 3111 can be Si (110). This application does not limit the first interface 1011 to Si (100), nor does it limit the second interface 3111 to Si (110). Through the process, the growth of different crystal forms on different crystal surfaces can be achieved.

[0149] S304, Precleaning of preform 300. Precleaning is a cleaning process performed on the surface of the structure, mainly to remove oxides and impurities that may exist at the interface due to natural growth caused by exposure to air.

[0150] S306, an amorphous film layer 71 is formed using a deposition process on the first interface 1011, the second interface 3111, the third interface 3135, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100. (See also...) Figure 16 .

[0151] This application does not limit the specific form of the deposition process. Any process that can deposit an amorphous film layer 71 on the side of the trench 100 is acceptable. That is, by using physical or chemical reactions, the structure is exposed to one or more precursor environments in the chamber to achieve the deposition and growth of a thin film on the surface.

[0152] S308, an annealing process is used to convert the amorphous film layer 71 on the first interface 1011, the second interface 3111, and the third interface 3135 into a single-crystal film layer 73. Please refer to [link / reference]. Figure 17 The amorphous film layer 71 on the side of the functional structure 33 facing the trench 100 and near the end of the stacked structure 31 can also be converted into a monocrystalline film layer 73.

[0153] The annealing process is used to solidify the amorphous film layer 71 by solid-state crystallization of the side surface of the channel layer 311 and the single-crystal Si interface of the first interface 1011. This transforms the amorphous film layer 71 into a single-crystal film layer 73.

[0154] S310, remove the amorphous film layer 71 on the side of functional structure 33 facing away from substrate 101 and the side of functional structure 33 facing trench 100 to form intermediate structure 500. Please refer to [link to relevant documentation]. Figure 18a .

[0155] In this embodiment, removing the amorphous film layer 71 on the side of the functional structure 33 facing away from the substrate 101 and the side of the functional structure 33 facing the trench 100 includes removing the amorphous film layer 71 on the side of the functional structure 33 facing away from the substrate 101 and the side of the functional structure 33 facing the trench 100 using a back-etching process.

[0156] By taking advantage of the different etching rates of amorphous and single crystal, with the etching rate of amorphous being higher than that of single crystal, after the amorphous film layer 71 in the preset area is completely etched, a single crystal film layer 73 of a certain thickness can still be retained.

[0157] S312, Pre-cleaning of intermediate structure 500. Pre-cleaning is a cleaning process performed on the surface of the structure, mainly to remove oxides and impurities that may exist at the interface due to natural growth caused by exposure to air.

[0158] S314, a single-crystal portion 75 is grown on the single-crystal film layer 73 to obtain the single-crystal source / drain electrode 105. Please refer to [link / reference]. Figure 18b .

[0159] In this embodiment, growing a single crystal portion 75 on a single crystal film layer 73 to obtain a single crystal source / drain electrode 105 includes growing the single crystal portion 75 on a single crystal film layer 73 using an epitaxial growth process.

[0160] The material of the single-crystal portion 75 can be the same as the material of the single-crystal film layer 73. The concentration of each element in the material of the single-crystal portion 75 can be the same as or different from the concentration of the corresponding element in the material used to make the single-crystal film layer 73. For example, in one possible implementation, both the single-crystal portion 75 and the single-crystal film layer 73 are made of SiGe, but the concentration of Ge in the single-crystal portion 75 can be different from the concentration of Ge in the single-crystal film layer 73. For example, in one possible implementation, both the single-crystal portion 75 and the single-crystal film layer 73 are made of SiGe:B, that is, SiGe is doped with element B, and the doping concentration of B in the single-crystal portion 75 can be different from the doping concentration of B in the single-crystal film layer 73. For example, in one possible implementation, both the single-crystal portion 75 and the single-crystal film layer 73 are made of SiGe, the single-crystal portion 75 is doped with element B, but the single-crystal film layer 73 is not doped with element B.

[0161] Please see Figure 19 This application provides a third embodiment of a manufacturing apparatus 400c for fabricating a preform 300 into a gate-all-around field-effect transistor 1. The preform 300 includes a substrate 101 and structural units 103 stacked in a first direction. The structural units 103 include a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the substrate 101. The stacked structure 31 includes a channel layer 311 and a sacrificial layer 313 alternately arranged in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is disposed on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0162] The number of structural units 103 is at least two, and a groove 100 is formed between each pair of adjacent structural units 103. The base 101 includes a first interface 1011 facing the groove 100. The side of the channel layer 311 in the second direction is a second interface 3111, which faces the groove 100. The internal isolation portion 3133 includes a third interface 3135 facing the groove 100. The first interface 1011, the second interface 3111, and the third interface 3135 form at least a portion of the side of the groove 100. The number of channel layers 311 is at least two.

[0163] This application also provides a manufacturing apparatus 400c including a pre-cleaning device 401, a growth device 402, an annealing device 404, and a removal device 407.

[0164] The pre-cleaning device 401 includes a first pre-cleaning module 4011 and a second pre-cleaning module 4013. The first pre-cleaning module 4011 is used to pre-clean the preform 300.

[0165] The growth apparatus 402 includes a first growth module 4021 and a second growth module 4023. The first growth module 4021 is a deposition apparatus, used to form an amorphous film layer 71 on the first interface 1011, the second interface 3111, the third interface 3135, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100 using a deposition process. (See also...) Figure 16 .

[0166] Annealing apparatus 404 is used to convert amorphous film layer 71 into monocrystalline film layer 73 using an annealing process. Please refer to [link / reference]. Figure 17 .

[0167] The removal device 407 is used to remove the amorphous film layer 71 on the side of the functional structure 33 facing away from the substrate 101 and on the side of the functional structure 33 facing the trench 100 to form an intermediate structure 500. Please refer to [link to relevant documentation]. Figure 18a The removal device 407 is an etching device, which is used to remove the amorphous film layer 71 on the side of the functional structure 33 facing away from the substrate 101 and the side of the functional structure 33 facing the trench 100 by means of a back etching process to form an intermediate structure 500.

[0168] The second pre-cleaning module 4013 is used to pre-clean the intermediate structure 500 to remove impurities and other contaminants from the intermediate structure 500.

[0169] The second growth module 4023 is used to grow a single crystal portion 75 on the single crystal film layer 73 to obtain a single crystal source / drain electrode 105. Please refer to [link / reference]. Figure 18bThe single-crystal portion 75 is made of the same material as the single-crystal film layer 73. In this embodiment, the second growth module 4023 is used to grow the single-crystal portion 75 on the single-crystal film layer 73 using an epitaxial growth process to obtain the single-crystal source / drain electrode 105.

[0170] It is understood that the pre-cleaning device 401 may include a pre-cleaning module, which is used to pre-clean the precast body 300 and the intermediate structure 500.

[0171] Please refer to the following: Figure 4b and Figure 20 The fourth embodiment of this application also provides a method for fabricating a fully all-around gate field-effect transistor 1, the method comprising the following steps:

[0172] S502, provides prefabricated body 300, please refer to Figure 21 The prefabricated body 300 includes a base 101 and structural units 103 stacked in a first direction. The structural unit 103 includes a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the base 101. The stacked structure 31 includes alternating channel layers 311 and sacrificial layers 313 in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is located on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0173] The number of structural units 103 is at least two, and a groove 100 is formed between each pair of adjacent structural units 103. The substrate 101 includes a first interface 1011 disposed toward the groove 100, the side of the channel layer 311 in the second direction is a second interface 3111 disposed toward the groove 100, and the internal isolation portion 3133 includes a third interface 3135 disposed toward the groove 100. The first interface 1011, the second interface 3111 and the third interface 3135 form at least a portion of the side of the groove 100.

[0174] The substrate 101 includes a substrate 1013 and a dielectric layer 1015 stacked in a first direction. The dielectric layer 1015 is located between the substrate 1013 and the stacked structure 31, and the first interface 1011 is located on the side of the dielectric layer 1015 facing the trench 100.

[0175] S504, Precleaning of preform 300. Precleaning is a cleaning process performed on the surface of the structure, mainly to remove oxides and impurities that may exist at the interface due to natural growth caused by exposure to air.

[0176] S506, an amorphous film layer 71 is formed using a deposition process on the first interface 1011, the second interface 3111, the third interface 3135, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100. (See also...) Figure 22 .

[0177] This application does not limit the specific form of the deposition process. Any process that can deposit an amorphous film layer 71 on the side of the trench 100 is acceptable. That is, by using physical or chemical reactions, the structure is exposed to one or more precursor environments in the chamber to achieve the deposition and growth of a thin film on the surface.

[0178] S508, an annealing process is used to convert the amorphous film layer 71 on the second interface 3111 and the third interface 3135 into a single-crystal film layer 73. Please refer to [link / reference]. Figure 23 The amorphous film layer 71 on the side of the functional structure 33 facing the trench 100 and near the end of the stacked structure 31 can also be converted into a monocrystalline film layer 73.

[0179] The annealing process is used to solidify the single-crystal Si interface on the side of the channel layer 311, so that the amorphous film layer 71 on the second interface 3111 and the third interface 3135 is transformed into a single-crystal film layer 73.

[0180] S510, remove the amorphous film layer 71 on the first interface 1011, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100 to form an intermediate structure 500. Please refer to [link to relevant documentation]. Figure 24 .

[0181] In this embodiment, removing the amorphous film layer 71 on the first interface 1011, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100 includes removing the amorphous film layer 71 on the first interface 1011, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100 using a back-etching process.

[0182] S512, pre-cleaning of intermediate structure 500. Pre-cleaning is a cleaning process performed on the surface of the structure, mainly to remove oxides and impurities that may exist at the interface due to natural growth caused by exposure to air.

[0183] S514, a single-crystal portion 75 is grown on the single-crystal film layer 73 to obtain the single-crystal source / drain electrode 105. Please refer to [link / reference]. Figure 25 .

[0184] This application also provides a manufacturing apparatus, which includes a pre-cleaning device, a growth device, an annealing device, and a removal device.

[0185] The pre-cleaning device includes a first pre-cleaning module and a second pre-cleaning module. The first pre-cleaning module is used to pre-clean the precast body 300.

[0186] The growth apparatus includes a first growth module and a second growth module. The first growth module is a deposition apparatus, used to form an amorphous film layer 71 on the first interface 1011, the second interface 3111, the third interface 3135, the side of the functional structure 33 facing away from the substrate 101, and the side of the functional structure 33 facing the trench 100 using a deposition process. Please refer to [link to relevant documentation]. Figure 22 .

[0187] The annealing apparatus is used to convert the amorphous film layer 71 on the second interface 3111 and the third interface 3135 into a single crystal film layer 73 using an annealing process. Please refer to [link / reference]. Figure 23 .

[0188] The removal device is used to remove the first interface 1011, the side of the functional structure 33 facing away from the substrate 101, and the amorphous film layer 71 on the side of the functional structure 33 facing the trench 100 to form an intermediate structure 500. Please refer to [link to relevant documentation]. Figure 24 The removal device is an etching device, which is used to remove the amorphous film layer 71 on the side of the functional structure 33 facing away from the substrate 101 and the side of the functional structure 33 facing the trench 100 by means of a back etching process to form an intermediate structure 500.

[0189] The second pre-cleaning module is used to pre-clean the intermediate structure 500 to remove impurities and other contaminants from the intermediate structure 500.

[0190] The second growth module is used to grow a single-crystal portion 75 on the single-crystal film layer 73 to obtain a single-crystal source / drain electrode 105. Please refer to [link / reference]. Figure 25 In this embodiment, the second growth module 4023 is used to grow a single crystal portion 75 on the single crystal film layer 73 using an epitaxial growth process to obtain a single crystal source / drain electrode 105.

[0191] It is understood that the pre-cleaning device 401 may include a pre-cleaning module, which is used to pre-clean the precast body 300 and the intermediate structure 500.

[0192] Please refer to the following: Figure 4b and Figure 26 The fifth embodiment of this application also provides a method for fabricating a fully all-around gate field-effect transistor 1, the method comprising the following steps:

[0193] S602, a preform 300 is provided. The preform 300 provided in the fifth embodiment has the same structure as the preform 300 provided in the fourth embodiment. Please refer to [link / reference]. Figure 21The prefabricated body 300 includes a base 101 and structural units 103 stacked in a first direction. The structural unit 103 includes a stacked structure 31 and a functional structure 33 stacked in the first direction. The stacked structure 31 is located between the functional structure 33 and the base 101. The stacked structure 31 includes alternating channel layers 311 and sacrificial layers 313 in the first direction. The sacrificial layer 313 includes a sacrificial portion 3131 and an internal isolation portion 3133. The internal isolation portion 3133 is located on the side of the sacrificial portion 3131 in a second direction different from the first direction.

[0194] The number of structural units 103 is at least two, and a groove 100 is formed between each pair of adjacent structural units 103. The substrate 101 includes a first interface 1011 disposed toward the groove 100, the side of the channel layer 311 in the second direction is a second interface 3111 disposed toward the groove 100, and the internal isolation portion 3133 includes a third interface 3135 disposed toward the groove 100. The first interface 1011, the second interface 3111 and the third interface 3135 form at least a portion of the side of the groove 100.

[0195] The substrate 101 includes a substrate 1013 and a dielectric layer 1015 stacked in a first direction. The dielectric layer 1015 is located between the substrate 1013 and the stacked structure 31, and the first interface 1011 is located on the side of the dielectric layer 1015 facing the trench 100.

[0196] S604, Precleaning of preform 300. Precleaning is a cleaning process performed on the surface of the structure, mainly to remove oxides and impurities that may exist at the interface due to natural growth caused by exposure to air.

[0197] S606, an amorphous film layer 71 is formed on the second interface 3111. Please refer to [link / reference]. Figure 27 In this embodiment, forming an amorphous film layer 71 on the second interface 3111 includes forming the amorphous film layer 71 on the second interface 3111 using an epitaxial growth process. The temperature range of the epitaxial growth process can be selected, but is not limited to, 300℃-500℃.

[0198] S608, at least two amorphous film layers 71 on the channel layers 311 are merged to form a continuous amorphous film layer 76. Please refer to [link / reference]. Figure 28 .

[0199] In this embodiment, a selective epitaxial growth process is used to merge the continuous amorphous film layer 76 at the second interface 3111 and the third interface 3135 of the trench 100 into a single continuous amorphous film layer 76. Because the continuous amorphous film layer 76 has amorphous properties and does not exhibit a preferred orientation during growth, it possesses good surface smoothness.

[0200] In S610, an annealing process is used to transform the continuous amorphous film layer 76 into a single-crystal film layer 73. The structure formed in S610 is similar to... Figure 24 The structure shown.

[0201] In this embodiment, an annealing process is used to utilize the solid-state crystallization of the single-crystal Si interface on the side of the channel layer 311, thereby transforming the continuous amorphous film layer 76 into a single-crystal film layer 73.

[0202] In S612, a single-crystal portion 75 is grown on the single-crystal film layer 73 to obtain a single-crystal source / drain electrode 105. The structure formed in S612 is similar to... Figure 25 The structure shown.

[0203] This application also provides a manufacturing apparatus, which includes a pre-cleaning device, a growth device, an annealing device, and a removal device.

[0204] The pre-cleaning device is used to pre-clean the precast body 300.

[0205] The growth apparatus includes a first growth module and a second growth module. The first growth module is an epitaxial growth apparatus, used to form an amorphous film layer 71 on the second interface 3111 using an epitaxial growth process. Please refer to [link to relevant documentation]. Figure 27 The first growth module is also used to merge at least two amorphous film layers 71 on the channel layers 311 to form a continuous amorphous film layer 76.

[0206] The annealing apparatus is used to convert the continuous amorphous film layer 76 into a monocrystalline film layer 73 using an annealing process.

[0207] The second growth module is used to grow a single crystal portion 75 on the single crystal film layer 73 to obtain a single crystal source / drain electrode 105. In this embodiment, the second growth module is used to grow a single crystal portion 75 on the single crystal film layer 73 using an epitaxial growth process to obtain a single crystal source / drain electrode 105.

[0208] In the embodiments described above in this application, combinations thereof are possible without conflict or contradiction. It should be understood that expressions such as "comprising" and "may include" used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "comprising" and / or "having" are to be interpreted as indicating a specific characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0209] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0210] In this application, expressions including ordinal numbers such as "first" and "second" may modify the elements. However, such elements are not limited by the foregoing expressions. For example, the foregoing expressions do not limit the order and / or importance of the elements. The foregoing expressions are only used to distinguish one element from other elements. For example, "first user equipment" and "second user equipment" refer to different user equipment, although both "first user equipment" and "second user equipment" are user equipment. Similarly, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0211] When a component is referred to as "connected" or "accessed" to other components, it should be understood that this component not only connects directly to or accesses other components, but also that another component may exist between this component and other components. On the other hand, when a component is referred to as "directly connected" or "directly accessed" to other components, it should be understood that no component exists between them.

[0212] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a fully all-around gate field-effect transistor, characterized in that, The preparation method includes the following steps: A prefabricated body is provided, the prefabricated body comprising a base and structural units stacked in a first direction, the structural units comprising a stacked structure and a functional structure stacked in the first direction, the stacked structure being located between the functional structure and the base, the stacked structure comprising a channel layer and a sacrificial layer alternately disposed in the first direction, the sacrificial layer comprising a sacrificial portion and an internal isolation portion, the internal isolation portion being disposed on the side of the sacrificial portion in a second direction different from the first direction; The preform is pre-cleaned; An amorphous film layer is formed on the side of the channel layer in the second direction and on the side of the internal isolation portion in the second direction away from the sacrificial portion; An annealing process is used to convert the amorphous film layer on the stacked structure into a monocrystalline film layer. Single crystal portions are grown in the single crystal film layer to obtain single crystal source and drain electrodes.

2. The preparation method according to claim 1, characterized in that, The number of structural units is at least two, and a groove is formed between each pair of adjacent structural units. The substrate includes a first interface facing the groove, and the side of the channel layer in the second direction is a second interface facing the groove. The internal isolation portion includes a third interface facing the groove, and the first interface, the second interface, and the third interface form at least a portion of the side of the groove.

3. The preparation method according to claim 2, characterized in that, The number of channel layers is at least two, and the amorphous film layer is formed on the side of the channel layer in the second direction and on the side of the internal isolation portion away from the sacrificial portion in the second direction, including forming the amorphous film layer on the second interface using an epitaxial growth process; and merging the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer; The process of converting the amorphous film layer on the stacked structure into a monocrystalline film layer by means of annealing includes converting the continuous amorphous film layer into a monocrystalline film layer by means of annealing.

4. The preparation method according to claim 3, characterized in that, The preparation method further includes forming a single-crystal film layer at the first interface using the epitaxial growth process; The step of merging the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer further includes connecting the continuous amorphous film layer to the monocrystalline film layer on the first interface. Growing a single crystal portion in the single crystal film layer to obtain a single crystal source / drain electrode includes growing a single crystal portion on a single crystal film layer on the first interface, the second interface, and the third interface.

5. The preparation method according to claim 2, characterized in that, The formation of an amorphous film layer on the side of the trench layer in the second direction and on the side of the internal isolation portion away from the sacrificial portion in the second direction includes forming an amorphous film layer on the second interface, the third interface, the side of the functional structure away from the substrate, and the side of the functional structure facing the trench using a deposition process. The step of using an annealing process to convert the amorphous film layer on the stacked structure into a monocrystalline film layer includes converting the amorphous film layer on the second interface and the third interface into a monocrystalline film layer. After converting the amorphous film layers on the second interface and the third interface into monocrystalline film layers, the preparation method further includes removing the amorphous film layers on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench.

6. The preparation method according to claim 5, characterized in that, The deposition process is used to form an amorphous film layer on the second interface, the third interface, the side of the functional structure facing away from the substrate, and the side of the functional structure facing the trench. This includes forming an amorphous film layer at the first interface using a deposition process; The step of converting the amorphous film layer on the second interface and the third interface into a monocrystalline film layer also includes converting the amorphous film layer on the first interface into a monocrystalline film layer.

7. The preparation method according to claim 5, characterized in that, The substrate includes a substrate and a dielectric layer stacked in a first direction, the dielectric layer being located between the substrate and the stacked structure, the first interface being located on the side of the dielectric layer facing the trench, and an amorphous film layer being formed using a deposition process on the second interface, the third interface, the side of the functional structure facing away from the substrate, and the side of the functional structure facing the trench. This includes forming an amorphous film layer at the first interface using a deposition process. The removal of the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench further includes removing the amorphous film layer on the first interface.

8. The preparation method according to claim 5, characterized in that, The removal of the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench includes using a back-etching process to remove the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench to form an intermediate structure. After removing the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench, and before growing a single crystal portion on the single crystal film layer to obtain a single crystal source and drain, the fabrication method further includes pre-cleaning the intermediate structure.

9. The preparation method according to any one of claims 2-8, characterized in that, The first interface is Si(100), and the second interface is Si(110).

10. The preparation method according to claim 9, characterized in that, The sacrificial part includes at least one of Si, Ge, compound semiconductor, and alloy semiconductor.

11. The preparation method according to claim 9, characterized in that, The amorphous film layer includes one of Si, Ge, compound semiconductor, and alloy semiconductor.

12. A fully all-around gate field-effect transistor, characterized in that, The all-around gate field-effect transistor is prepared by the preparation method according to any one of claims 1-11.

13. A manufacturing apparatus, characterized in that, The manufacturing equipment is used to fabricate a preform into a gate-all-around field-effect transistor. The preform includes a substrate and structural units stacked in a first direction. The structural units include a stacked structure and a functional structure stacked in the first direction. The stacked structure is located between the functional structure and the substrate. The stacked structure includes a channel layer and a sacrificial layer alternately arranged in the first direction. The sacrificial layer includes a sacrificial portion and an internal isolation portion. The internal isolation portion is disposed on the side of the sacrificial portion in a second direction different from the first direction. The manufacturing equipment includes a pre-cleaning device, a growth device, and an annealing device. The pre-cleaning device is used to pre-clean the preform. The growth apparatus is used to form an amorphous film layer on the side of the channel layer in the second direction and on the side of the internal isolation portion in the second direction away from the sacrificial portion. The annealing device is used to convert the amorphous film layer on the stacked structure into a monocrystalline film layer. The growth apparatus is also used to grow single crystal portions in the single crystal film layer to obtain single crystal source and drain electrodes.

14. The manufacturing equipment according to claim 13, characterized in that, The number of structural units is at least two, and a groove is formed between each pair of adjacent structural units. The substrate includes a first interface facing the groove, and the side of the channel layer in the second direction is a second interface facing the groove. The internal isolation portion includes a third interface facing the groove. The first interface, the second interface, and the third interface form at least a portion of the side of the groove. The number of channel layers is at least two; The growth apparatus is used to: form the amorphous film layer on the second interface using an epitaxial growth process; and merge the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer. The annealing apparatus is used to convert the continuous amorphous film layer on the stacked structure into a monocrystalline film layer.

15. The manufacturing equipment according to claim 14, characterized in that, The growth apparatus is also used to form a single-crystal film layer at the first interface using the epitaxial growth process; The step of merging the amorphous film layers on the at least two channel layers to form a continuous amorphous film layer further includes connecting the continuous amorphous film layer to the monocrystalline film layer on the first interface.

16. The manufacturing equipment according to claim 13, characterized in that, The number of structural units is at least two, and a groove is formed between each pair of adjacent structural units. The substrate includes a first interface facing the groove, and the side of the channel layer in the second direction is a second interface facing the groove. The internal isolation portion includes a third interface facing the groove. The first interface, the second interface, and the third interface form at least a portion of the side of the groove. The growth apparatus includes a first growth module and a second growth module. The first growth module is used to form an amorphous film layer on the second interface, the third interface, the side of the functional structure facing away from the substrate, and the side of the functional structure facing the trench using a deposition process. The manufacturing equipment further includes a removal device for removing the amorphous film layer on the side of the functional structure facing away from the substrate and the side of the functional structure facing the trench to form an intermediate structure; The pre-cleaning device is also used to pre-clean the intermediate structure; The second growth module is used to grow single crystal portions in the single crystal film layer to obtain single crystal source and drain electrodes.

17. The manufacturing equipment according to claim 16, characterized in that, The first growth module is further configured to form an amorphous film layer on the first interface, and the annealing device is further configured to convert the amorphous film layer on the first interface into a monocrystalline film layer.

18. The manufacturing equipment according to claim 17, characterized in that, The substrate includes a substrate and a dielectric layer stacked in a first direction, the dielectric layer being located between the substrate and the stacked structure, the first interface being located on the side of the dielectric layer facing the trench, the first growth module being further configured to form an amorphous film layer on the first interface, and the removal device being further configured to remove the amorphous film layer on the first interface.

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