MOSFET device with integrated protection and method of manufacturing the same
Patent Information
- Application Number
- CN202611015908.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-08
- Publication Date
- 2026-10-27
AI Technical Summary
[0007]本发明的目的在于提供一种屏蔽栅沟槽型集成保护装置的MOSFET器件及其制造方法，以解决现有的MOSFET器件在工作过程中以及过流时积累的热量严重影响到电子产品的使用寿命和可靠性、现有的具有散热保护结构的MOSFET器件的制造成本较高以及占用芯片面积较大等问题中的至少一个问题
[0034]综上所述，本发明提供的集成保护装置的MOSFET器件的制造方法中，在衬底增设一保护区，在栅极引出区形成第二沟槽以及有源区形成第三沟槽的同时，在保护区形成第一沟槽，随后在第一至第三沟槽中形成栅氧化层和掺杂多晶硅层，接着形成层间介质层，随后在保护区形成两个第一导电插塞、在栅极引出区形成第二导电插塞以及在有源区形成第三导电插塞，最后形成第一至第四金属电极，其中，所述保护区的所述第一金属电极、所述第二金属电极、所述第一导电插塞和所述第一沟槽内的所述掺杂多晶硅层构成电阻值可调的电阻器。本申请通过在制备栅极沟槽的同时制备保护区的电阻器，没有增加额外的光刻、刻蚀、离子注入等任何工序，在没有额外成本增加的情况下，沟槽电阻器可以与第三金属电极（栅极电极）或与第四金属电极（源区电极）串联使用，实现电路的保护及检测功能，防止MOS器件过流烧毁，提高了电子产品的可靠性，延长了电子产品的使用寿命和。
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Figure CN122995176A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a MOSFET device with integrated protection and its manufacturing method. Background Technology
[0002] The heat generated and accumulated by MOSFET devices in a circuit during operation, or the heat generated due to overcurrent, seriously affects the lifespan and reliability of electronic products.
[0003] Currently, there are generally two improvement methods in existing technologies:
[0004] The first improvement method is to add circuit structures such as resistors, current detection circuits, and logic comparison circuits to the circuit to provide overcurrent protection for MOSFET devices.
[0005] The second improvement method is to use a thermistor in the circuit to detect and protect the temperature of the MOSFET semiconductor device.
[0006] While both methods improve the lifespan and reliability of MOSFET devices to some extent, they require additional passive components and new processes such as photolithography, etching, and ion implantation, increasing manufacturing costs. Furthermore, both methods require expansion of the layout module, leading to an increase in chip area, which is not in line with the development trend of integrated circuits. Summary of the Invention
[0007] The purpose of this invention is to provide a MOSFET device with a shielded gate trench integrated protection device and its manufacturing method, so as to solve at least one of the following problems: the heat accumulated by existing MOSFET devices during operation and overcurrent seriously affects the service life and reliability of electronic products; the manufacturing cost of existing MOSFET devices with heat dissipation protection structures is high; and the chip area occupied is large.
[0008] To address the aforementioned technical problems, in one aspect, the present invention provides a method for manufacturing a MOSFET device with an integrated protection device, comprising:
[0009] A substrate is provided, the substrate comprising a protection zone, a gate lead-out region and an active region, and a hard mask layer and a photoresist layer are sequentially formed on the substrate;
[0010] A first trench pattern, a second trench pattern, and a third trench pattern are defined on the photoresist layer using a photolithography process to obtain a patterned photoresist layer.
[0011] Using a patterned photoresist layer as a mask, the hard mask layer and a substrate of a certain thickness are etched to form a first trench in the substrate of the protected area, a second trench in the gate lead-out area, and at least one third trench in the active area.
[0012] Remove the patterned photoresist layer and the hard mask layer;
[0013] A gate oxide layer is formed, which covers the substrate surface and the sidewalls and bottom walls of the first to third trenches;
[0014] A doped polysilicon layer is formed, which covers the gate oxide layer in the first to third trenches and fills the first to third trenches;
[0015] An interlayer dielectric layer is formed, which covers the substrate and the gate oxide layer and the doped polysilicon layer in the first to third trenches;
[0016] Two first conductive plugs, one second conductive plug, and at least one third conductive plug are formed, wherein the two first conductive plugs penetrate the interlayer dielectric layer of the protected area and a portion of the thickness of the doped polysilicon layer in the first trench; the second conductive plug penetrates the interlayer dielectric layer of the gate lead-out region and a portion of the thickness of the doped polysilicon layer in the second trench; and the third conductive plug penetrates a portion of the thickness of the substrate between the interlayer dielectric layer of the active region and the third trench and contacts the source electrode in the substrate, wherein the two first conductive plugs are spaced apart.
[0017] First to fourth metal electrodes are formed, wherein the first metal electrode covers the first first conductive plug, the second metal electrode covers the second first conductive plug, the third metal electrode covers the second conductive plug, and the fourth metal electrode covers all the third conductive plugs, wherein the first metal electrode, the second metal electrode, the first conductive plug, and the doped polycrystalline silicon layer in the first trench of the protected area constitute a resistor with adjustable resistance value.
[0018] Optionally, in the manufacturing method of the MOSFET device of the integrated protection device, the resistance value of the resistor is adjusted by adjusting the spacing between the two first conductive plugs.
[0019] Optionally, in the manufacturing method of the MOSFET device of the integrated protection device, the doping type of the doped polysilicon layer is N-type or P-type.
[0020] Optionally, in the manufacturing method of the MOSFET device of the integrated protection device, the first to third conductive plugs are all made of copper or tungsten.
[0021] Optionally, in the manufacturing method of the MOSFET device of the integrated protection device, the first to fourth metal electrodes are all made of copper or aluminum.
[0022] Optionally, in the manufacturing method of the MOSFET device of the integrated protection device, the material of the interlayer dielectric layer is silicon dioxide.
[0023] Optionally, in the manufacturing method of the MOSFET device of the integrated protection device, the material of the hard mask layer is silicon nitride.
[0024] Optionally, in the method for manufacturing the MOSFET device of the integrated protection device, after forming the first to third conductive plugs, the method further includes: forming at least one fourth conductive plug, the fourth conductive plug extending from the back side of the substrate through a portion of the thickness of the substrate between the third trenches of the active region and contacting the drain in the substrate.
[0025] Optionally, in the method for manufacturing the MOSFET device of the integrated protection device, after forming at least one fourth conductive plug, the method further includes: forming a drain metal electrode that covers the back side of the substrate and the fourth conductive plug.
[0026] On the other hand, the present invention also provides a MOSFET device with an integrated protection device, comprising:
[0027] A substrate, the substrate comprising a protection zone, a gate lead-out region, and an active region;
[0028] A first trench, a second trench, and at least one third trench, wherein the first trench is located in a substrate of a portion thickness of the protected area, the second trench is located in a substrate of a portion thickness of the gate lead-out region, and the third trench is located in a substrate of a portion thickness of the active region.
[0029] A gate oxide layer, the gate oxide layer covering the substrate surface and the sidewalls and bottom walls of the first to third trenches;
[0030] A doped polysilicon layer, the doped polysilicon layer covering the gate oxide layer in the first to third trenches and filling the first to third trenches;
[0031] An interlayer dielectric layer, the interlayer dielectric layer covering the substrate and the gate oxide layer and the doped polysilicon layer in the first to third trenches;
[0032] Two first conductive plugs, one second conductive plug, and at least one third conductive plug, wherein the two first conductive plugs penetrate the interlayer dielectric layer of the protected zone and a portion of the doped polysilicon layer in the first trench; the second conductive plug penetrates the interlayer dielectric layer of the gate lead-out region and a portion of the doped polysilicon layer in the second trench; and the third conductive plug penetrates a portion of the substrate between the interlayer dielectric layer of the active region and the third trench and contacts the source electrode in the substrate, wherein the two first conductive plugs are spaced apart.
[0033] The first to fourth metal electrodes, wherein the first metal electrode covers the first first conductive plug, the second metal electrode covers the second first conductive plug, the third metal electrode covers the second conductive plug, and the fourth metal electrode covers all the third conductive plugs, wherein the first metal electrode, the second metal electrode, the first conductive plug and the doped polycrystalline silicon layer in the first trench of the protected area constitute a resistor with adjustable resistance value.
[0034] In summary, the manufacturing method of the MOSFET device with integrated protection provided by this invention involves adding a protection zone to the substrate, forming a second trench in the gate lead-out region and a third trench in the active region, while simultaneously forming a first trench in the protection zone. Subsequently, a gate oxide layer and a doped polysilicon layer are formed in the first to third trenches, followed by the formation of an interlayer dielectric layer. Then, two first conductive plugs are formed in the protection zone, a second conductive plug is formed in the gate lead-out region, and a third conductive plug is formed in the active region. Finally, first to fourth metal electrodes are formed. The first metal electrode, the second metal electrode, the first conductive plug, and the doped polysilicon layer in the first trench of the protection zone constitute a resistor with an adjustable resistance value. This application, by simultaneously fabricating the resistor in the protection zone with the gate trench, avoids any additional photolithography, etching, ion implantation, or other processes. Without increasing costs, the trench resistor can be used in series with the third metal electrode (gate electrode) or the fourth metal electrode (source electrode) to achieve circuit protection and detection functions, prevent overcurrent burnout of the MOSFET device, improve the reliability of electronic products, and extend the service life of electronic products.
[0035] Furthermore, trench resistors are formed in the circuit through the trench polysilicon structure of the protected area. The trench resistors can flexibly adjust the distance between the contact holes (two first conductive plugs) to change the resistance value, adapt to the protection threshold of different power devices, and have a small area, which is convenient for on-chip integration, in line with the development trend of further miniaturization of integrated circuits.
[0036] In addition, the trench resistor is embedded in the substrate and close to the heating channel. It can use the temperature resistance characteristics of polysilicon to detect the chip junction temperature in real time. When the temperature exceeds the limit, it can trigger the protection to shut down the MOS device, avoid high temperature breakdown of gate oxide and metal electromigration failure, and realize the overheat protection of the device. Attached Figure Description
[0037] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0038] Figure 1 This is a flowchart of a method for manufacturing a MOSFET device for an integrated protection device according to an embodiment of the present invention;
[0039] Figures 2-8 This is a schematic diagram of the semiconductor structure in each process step of manufacturing the MOSFET device of the integrated protection device according to an embodiment of the present invention;
[0040] The reference numerals in the attached figures are explained as follows:
[0041] 10-Substrate, 11-Source, 20-Hard mask layer, 30-Patterned photoresist layer, 31-First trench pattern, 32-Second trench pattern, 33-Third trench pattern, 41-First trench, 42-Second trench, 43-Third trench, 60-Gate oxide layer, 70-Doped polysilicon layer, 80-Interlayer dielectric layer, 81-First conductive plug, 82-Second conductive plug, 83-Third conductive plug, 91-First metal electrode, 92-Second metal electrode, 93-Third metal electrode, 94-Fourth metal electrode. Detailed Implementation
[0042] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0043] This invention provides a method for manufacturing a MOSFET device with integrated protection, referring to... Figure 1 , Figure 1This is a flowchart of a method for manufacturing a MOSFET device for an integrated protection device according to an embodiment of the present invention. The method for manufacturing the MOSFET device for the integrated protection device includes:
[0044] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after the formation of a first trench pattern, a second trench pattern, and a third trench pattern according to an embodiment of this application. A substrate 10 is provided, the substrate 10 including a protection zone, a gate lead-out region, and an active region. A hard mask layer 20 and a photoresist layer 30 are sequentially formed on the substrate 10.
[0045] In this embodiment, the hard mask layer 20 is made of silicon nitride.
[0046] Then, proceed to step S2: Continue to refer to Figure 2 Through photolithography, a first trench pattern 31, a second trench pattern 32, and a third trench pattern 33 are defined on the photoresist layer to obtain a patterned photoresist layer 30.
[0047] Next, proceed to step S3: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the first trench, the second trench and the third trench in an embodiment of this application. Using a patterned photoresist layer 30 as a mask, the hard mask layer 20 and a substrate 10 of a certain thickness are etched to form a first trench 41 in the substrate 10 of the protected area, a second trench 42 in the gate lead-out region and at least one third trench 43 in the active region.
[0048] Further, proceed to step S4: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after removing the patterned photoresist layer and the hard mask layer according to an embodiment of this application, showing the removal of the patterned photoresist layer 30 and the hard mask layer 20.
[0049] In this embodiment, an ashing process is used to remove the patterned photoresist layer 30.
[0050] Preferably, the hard mask layer 20 is removed using a dry etching process.
[0051] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the gate oxide layer according to an embodiment of this application. The gate oxide layer 60 is formed, and the gate oxide layer 60 covers the surface of the substrate 10 and the sidewalls and bottom walls of the first trench 41, the second trench 42 and the third trench 43.
[0052] Preferably, the gate oxide layer 60 is formed using a CVD process or a thermal oxidation process.
[0053] Further, proceed to step S6: Refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of a doped polysilicon layer according to an embodiment of this application. A doped polysilicon layer 70 is formed, which covers the gate oxide layer 60 in the first trench 41, the second trench 42 and the third trench 43 and fills the first trench 41, the second trench 42 and the third trench 43.
[0054] Preferably, the doped polycrystalline silicon layer 70 is formed using LPCVD (low-pressure chemical vapor deposition) process.
[0055] Depending on the doping type requirements of the gate polysilicon for PMOS or NMOS devices, the doping type of the doped polysilicon layer 70 can be selected as N-type or P-type.
[0056] Next, proceed to step S7: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the first to third conductive plugs according to an embodiment of this application. An interlayer dielectric layer 80 is formed, which covers the gate oxide layer 60 and the doped polysilicon layer 70 in the substrate 10 and the first trench 41, the second trench 42 and the third trench 43.
[0057] In this embodiment, the interlayer dielectric layer 80 is made of silicon dioxide.
[0058] Further, proceed to step S8: Continue to refer to Figure 7 Two first conductive plugs 81, one second conductive plug 82, and at least one third conductive plug 83 are formed. The two first conductive plugs 81 penetrate the interlayer dielectric layer 80 and a portion of the doped polysilicon layer 70 in the first trench 41 of the protected area. The second conductive plug 82 penetrates the interlayer dielectric layer 80 and a portion of the doped polysilicon layer 70 in the second trench 42 of the gate lead-out region. The third conductive plug 83 penetrates a portion of the substrate 10 between the interlayer dielectric layer 80 and the third trench 43 of the active region and contacts the source 11 in the substrate 10. The two first conductive plugs 81 are spaced apart.
[0059] Preferably, the first conductive plug 81, the second conductive plug 82 and the third conductive plug 83 are all made of copper or tungsten.
[0060] Finally, proceed to step S9: (Refer to...) Figure 8 , Figure 8This is a schematic diagram of the semiconductor structure after the formation of the first to fourth metal electrodes according to an embodiment of this application. The first metal electrode 91, the second metal electrode 92, the third metal electrode 93, and the fourth metal electrode 94 are formed using PVD and dry etching processes. The first metal electrode 91 covers the first first conductive plug 81, the second metal electrode 92 covers the second first conductive plug 81, the third metal electrode 93 covers the second conductive plug 82, and the fourth metal electrode 94 covers all the third conductive plugs 83. The doped polysilicon layer 70 in the protected area, including the first metal electrode 91, the second metal electrode 92, the first conductive plug 81, and the first trench 41, constitutes a resistor with an adjustable resistance value.
[0061] Preferably, the first metal electrode 91, the second metal electrode 92, the third metal electrode 93 and the fourth metal electrode 94 are all made of copper or aluminum.
[0062] The resistance value of the resistor is adjusted by adjusting the spacing between the two first conductive plugs 81.
[0063] The third metal electrode 93, the second conductive plug 82, and the doped polysilicon layer 70 of the gate lead-out region are connected to the doped polysilicon layer 70 of the active region, thereby leading out the doped polysilicon layer 70 (gate) in the active region.
[0064] Furthermore, after forming the first conductive plug 81, the second conductive plug 82, and the third conductive plug 83, the method for manufacturing the MOSFET device of the integrated protection device may further include:
[0065] At least one fourth conductive plug (not shown) is formed, the fourth conductive plug extending from the back side of the substrate through a portion of the thickness of the substrate between the third trenches of the active region and contacting the drain (not shown) in the substrate;
[0066] A drain metal electrode (not shown) is formed, which covers the back side of the substrate and the fourth conductive plug.
[0067] In this application, by fabricating the protection zone resistor simultaneously with the gate trench, no additional photolithography, etching, ion implantation, or other processes are added. Without increasing costs, the trench resistor can be used in series with either the third metal electrode (gate electrode) or the fourth metal electrode (source electrode) to achieve circuit protection and detection functions, preventing MOS devices from burning out due to overcurrent and improving the lifespan and reliability of electronic products. Furthermore, by forming a trench polysilicon structure in the protection zone, a trench resistor is formed in the circuit. The trench resistor allows for flexible adjustment of the spacing between the contact holes (two first conductive plugs) to change the resistance value, adapting to the protection thresholds of different power devices. Its small area facilitates on-chip integration, aligning with the trend of further miniaturization of integrated circuits. In addition, the trench resistor is embedded in the substrate, close to the heating channel, allowing for real-time detection of the chip junction temperature using the polysilicon temperature resistance characteristics. When the temperature exceeds the limit, it triggers protection to shut down the MOS device, preventing high-temperature gate oxide breakdown and metal electromigration failure, thus achieving overheat protection of the device.
[0068] Based on the same inventive concept, the present invention also provides a MOSFET device with an integrated protection device, see reference. Figure 8 The MOSFET device of the integrated protection device includes:
[0069] Substrate 10, the substrate 10 including a protection zone, a gate lead-out region and an active region;
[0070] A first trench 41, a second trench 42, and at least one third trench 43, wherein the first trench 41 is located in a portion of the thickness of the substrate 10 of the protected area, the second trench 42 is located in a portion of the thickness of the substrate 10 of the gate lead-out region, and the third trench 43 is located in a portion of the thickness of the substrate 10 of the active region.
[0071] A gate oxide layer 60 covers the surface of the substrate 10 and the sidewalls and bottom walls of the first trench 41, the second trench 42 and the third trench 43;
[0072] A doped polysilicon layer 70 covers the gate oxide layer 60 within the first trench 41, the second trench 42, and the third trench 43 and fills the first trench 41, the second trench 42, and the third trench 43.
[0073] Interlayer dielectric layer 80, which covers the gate oxide layer 60 and the doped polysilicon layer 70 in the substrate 10 and the first trench 41, the second trench 42 and the third trench 43;
[0074] Two first conductive plugs 81, one second conductive plug 82, and at least one third conductive plug 83, wherein the two first conductive plugs 81 penetrate the interlayer dielectric layer 80 of the protected zone and a portion of the thickness of the doped polysilicon layer 70 in the first trench 41; the second conductive plug 82 penetrates the interlayer dielectric layer 80 of the gate lead-out region and a portion of the thickness of the doped polysilicon layer 70 in the second trench; and the third conductive plug 83 penetrates a portion of the thickness of the substrate 10 between the interlayer dielectric layer 80 and the third trench 43 in the active region and contacts the source 11 in the substrate 10, wherein the two first conductive plugs 81 are spaced apart;
[0075] The first metal electrode 91, the second metal electrode 92, the third metal electrode 93, and the fourth metal electrode 94, wherein the first metal electrode 91 covers the first first conductive plug 81, the second metal electrode 92 covers the second first conductive plug 81, the third metal electrode 93 covers the second conductive plug 82, and the fourth metal electrode 94 covers all the third conductive plugs 83. The first metal electrode 91, the second metal electrode 92, the first conductive plug 81, and the doped polycrystalline silicon layer 70 in the first trench 41 of the protected area constitute a resistor with adjustable resistance.
[0076] In this application, a protection device is integrated into the device by forming a trench polysilicon structure in the protected area. Specifically, a trench resistor is formed in the circuit. The trench resistor can flexibly adjust the resistance value by adjusting the spacing between the contact holes (two first conductive plugs) to adapt to the protection threshold of different power devices. Its small area facilitates on-chip integration, aligning with the trend of further miniaturization of integrated circuits. Furthermore, the trench resistor is embedded in the substrate, close to the heating channel, allowing for real-time detection of the chip junction temperature using the polysilicon temperature resistance characteristics. If the temperature exceeds the limit, it triggers protection to shut down the MOS device, preventing high-temperature gate oxide breakdown and metal electromigration failure, thus achieving overheat protection for the device.
[0077] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for manufacturing a MOSFET device with integrated protection, characterized in that, include: A substrate is provided, the substrate comprising a protection zone, a gate lead-out region and an active region, and a hard mask layer and a photoresist layer are sequentially formed on the substrate; A first trench pattern, a second trench pattern, and a third trench pattern are defined on the photoresist layer using a photolithography process to obtain a patterned photoresist layer. Using a patterned photoresist layer as a mask, the hard mask layer and a substrate of a certain thickness are etched to form a first trench in the substrate of the protected area, a second trench in the gate lead-out area, and at least one third trench in the active area. Remove the patterned photoresist layer and the hard mask layer; A gate oxide layer is formed, which covers the substrate surface and the sidewalls and bottom walls of the first to third trenches; A doped polysilicon layer is formed, which covers the gate oxide layer in the first to third trenches and fills the first to third trenches; An interlayer dielectric layer is formed, which covers the substrate and the gate oxide layer and the doped polysilicon layer in the first to third trenches; Two first conductive plugs, one second conductive plug, and at least one third conductive plug are formed, wherein the two first conductive plugs penetrate the interlayer dielectric layer of the protected area and a portion of the thickness of the doped polysilicon layer in the first trench; the second conductive plug penetrates the interlayer dielectric layer of the gate lead-out region and a portion of the thickness of the doped polysilicon layer in the second trench; and the third conductive plug penetrates a portion of the thickness of the substrate between the interlayer dielectric layer of the active region and the third trench and contacts the source electrode in the substrate, wherein the two first conductive plugs are spaced apart. First to fourth metal electrodes are formed, wherein the first metal electrode covers the first first conductive plug, the second metal electrode covers the second first conductive plug, the third metal electrode covers the second conductive plug, and the fourth metal electrode covers all the third conductive plugs, wherein the first metal electrode, the second metal electrode, the first conductive plug, and the doped polycrystalline silicon layer in the first trench of the protected area constitute a resistor with adjustable resistance value.
2. The method for manufacturing the MOSFET device of the integrated protection device according to claim 1, characterized in that, The resistance value of the resistor is adjusted by adjusting the spacing between the two first conductive plugs.
3. The method for manufacturing the MOSFET device of the integrated protection device according to claim 1, characterized in that, The doping type of the polycrystalline silicon layer is N-type or P-type.
4. The method for manufacturing the MOSFET device of the integrated protection device according to claim 1, characterized in that, The first to third conductive plugs are all made of copper or tungsten.
5. The method for manufacturing a MOSFET device with an integrated protection device according to claim 1, characterized in that, The first to fourth metal electrodes are all made of copper or aluminum.
6. The method for manufacturing a MOSFET device with an integrated protection device according to claim 1, characterized in that, The interlayer dielectric layer is made of silicon dioxide.
7. The method for manufacturing a MOSFET device with an integrated protection device according to claim 1, characterized in that, The hard mask layer is made of silicon nitride.
8. A method for manufacturing a MOSFET device with an integrated protection device according to claim 1, characterized in that, After forming the first to third conductive plugs, the method for manufacturing the MOSFET device of the integrated protection device further includes: At least one fourth conductive plug is formed, the fourth conductive plug extending from the back side of the substrate through a portion of the thickness of the substrate between the third trenches of the active region and contacting the drain in the substrate.
9. A method for manufacturing a MOSFET device with an integrated protection device according to claim 8, characterized in that, After forming at least one fourth conductive plug, the method for manufacturing the MOSFET device of the integrated protection device further includes: A drain metal electrode is formed, which covers the back side of the substrate and the fourth conductive plug.
10. A MOSFET device with integrated protection, characterized in that, include: A substrate, the substrate comprising a protection zone, a gate lead-out region, and an active region; A first trench, a second trench, and at least one third trench, wherein the first trench is located in a substrate of a portion thickness of the protected area, the second trench is located in a substrate of a portion thickness of the gate lead-out region, and the third trench is located in a substrate of a portion thickness of the active region. A gate oxide layer, the gate oxide layer covering the substrate surface and the sidewalls and bottom walls of the first to third trenches; A doped polysilicon layer, the doped polysilicon layer covering the gate oxide layer in the first to third trenches and filling the first to third trenches; An interlayer dielectric layer, the interlayer dielectric layer covering the substrate and the gate oxide layer and the doped polysilicon layer in the first to third trenches; Two first conductive plugs, one second conductive plug, and at least one third conductive plug, wherein the two first conductive plugs penetrate the interlayer dielectric layer of the protected zone and a portion of the doped polysilicon layer in the first trench; the second conductive plug penetrates the interlayer dielectric layer of the gate lead-out region and a portion of the doped polysilicon layer in the second trench; and the third conductive plug penetrates a portion of the substrate between the interlayer dielectric layer of the active region and the third trench and contacts the source electrode in the substrate, wherein the two first conductive plugs are spaced apart. The first to fourth metal electrodes, wherein the first metal electrode covers the first first conductive plug, the second metal electrode covers the second first conductive plug, the third metal electrode covers the second conductive plug, and the fourth metal electrode covers all the third conductive plugs, wherein the first metal electrode, the second metal electrode, the first conductive plug and the doped polycrystalline silicon layer in the first trench of the protected area constitute a resistor with adjustable resistance value.