Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: preparing a protection layer above a substrate, the protection layer comprising a pad oxide layer and a barrier layer which are arranged in a stack manner, the pad oxide layer comprising a to-be-grown region and a sacrifice region; performing a patterning treatment on the barrier layer to form a patterned barrier layer with a first window, the to-be-grown region being exposed through the first window to obtain a first intermediate device; performing a thermal oxidation treatment on the first intermediate device in a first gas atmosphere to make the to-be-grown region epitaxially grow to form a thick oxygen structure, and obtain a second intermediate device, a part of the thick oxygen structure in the second intermediate device being exposed through the first window, the first gas atmosphere comprising at least one of a nitrogen element and a fluorine element; removing the sacrifice region and the patterned barrier layer above the sacrifice region to expose the thick oxygen structure and an exposed surface of the substrate distributed around the thick oxygen structure; and forming a thin oxygen structure on the exposed surface of the substrate.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of good conductors and insulators. They utilize the unique electrical properties of semiconductor materials to perform specific functions, such as switching control, signal processing, and power conversion in modern electronic systems. It is understandable that the performance of semiconductor devices has a significant and undeniable impact on the performance of the electronic systems they operate in.

[0003] Improving the reliability of semiconductor devices is one of the ongoing research directions in the semiconductor field. Summary of the Invention

[0004] This application provides a semiconductor device and a method for fabricating the same, which can improve the quality of the gate oxide layer of the semiconductor device to optimize the voltage withstand performance and reliability of the semiconductor device.

[0005] On one hand, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: A protective layer is prepared on top of the substrate. The protective layer includes a pad oxide layer and a barrier layer stacked together. The pad oxide layer includes a region to be grown and a sacrificial region. The barrier layer is patterned to form a patterned barrier layer with a first window, and the area to be grown is exposed through the first window to obtain the first intermediate device; The first intermediate device is subjected to thermal oxidation to allow epitaxial growth of the region to be grown, forming a thick oxygen structure, to obtain a second intermediate device. A portion of the thick oxygen structure in the second intermediate device is exposed through a first window. The second intermediate device is then subjected to annealing. At least one of the thermal oxidation and annealing processes is carried out in a first gas atmosphere, which includes at least one of nitrogen and fluorine. Remove the sacrificial region and the patterned barrier layer above the sacrificial region to expose the thick oxide structure and the exposed surface of the substrate distributed around the thick oxide structure. A thin oxide structure is formed on the exposed surface of the substrate to obtain a third intermediate device. The third intermediate device has a front side and a back side separated along the thickness direction. The thick oxide structure and the thin oxide structure are located on the front side of the third intermediate device. A gate electrode and a source electrode are formed on the positive side of the third intermediate device. After flipping the third intermediate device, a drain electrode is formed on the back side of the third intermediate device to obtain a semiconductor device.

[0006] In some embodiments, thermal oxidation of the first intermediate device includes: The first intermediate device is subjected to dry oxidation treatment to thicken the area to be grown to form the first sub-part, thus obtaining a first-processed device; A wet oxidation process is performed on the primary processed device to thicken the first sub-part and form the second sub-part, thus obtaining a secondary processed device. The secondary processing device is subjected to dry oxidation treatment to thicken the second sub-part to form a thick oxygen structure, thus obtaining the second intermediate device; At least one of the dry oxidation treatment of the first intermediate device and the dry oxidation treatment of the secondary processing device is performed under the first gas atmosphere.

[0007] In some of these embodiments, the first gas atmosphere is introduced simultaneously with or before the oxygen atmosphere.

[0008] In some of these embodiments, the first gas atmosphere includes at least one of nitrous oxide, nitric oxide, ammonia, nitrogen trifluoride, and carbon tetrafluoride.

[0009] In some embodiments, the substrate includes a JFET region, and the area to be grown in the pad oxide layer at least partially overlaps with the JFET region. The fabrication method further includes: Before thermal oxidation of the first intermediate device, fluorine ions are implanted in the JFET region.

[0010] In some embodiments, the barrier layer includes a buffer layer and an oxide barrier layer, wherein the coefficient of thermal expansion of the buffer layer is between that of the pad oxide layer and the oxide barrier layer, and the thickness of the pad oxide layer is less than that of the oxide barrier layer.

[0011] In some of these embodiments, the pad oxide layer comprises silicon dioxide, the oxide barrier layer comprises silicon nitride, and the buffer layer comprises at least one of polysilicon and silicon oxynitride.

[0012] In some embodiments, the buffer layer comprises silicon oxynitride, and the coefficient of thermal expansion of the buffer layer remains unchanged or increases in the direction away from the pad oxide layer.

[0013] In some of these embodiments, the thickness of the pad oxide layer is 100–300 angstroms; and / or, the thickness of the buffer layer is 300–700 angstroms; and / or, the thickness of the oxide barrier layer is 1000–1300 angstroms.

[0014] In some embodiments, patterning the barrier layer to form a patterned barrier layer with a first window includes: The oxide barrier layer is patterned using a first mask to form a first opening, through which a portion of the buffer layer is exposed. The buffer layer exposed through the first opening is patterned using a second mask to form a second opening. The area to be grown is exposed through the second opening, and the orthographic projection of the second opening on the substrate falls within the orthographic projection range of the first opening on the substrate.

[0015] On the other hand, this application provides a semiconductor device, which is fabricated using the fabrication method provided in any of the foregoing embodiments. The semiconductor device includes a substrate, an epitaxial layer, a gate oxide layer, and a gate electrode. The epitaxial layer is disposed on one side of the substrate along the thickness direction. A plurality of well regions are formed on the side of the epitaxial layer away from the substrate, spaced apart along a first direction. A source region is provided inside the well region on the side away from the substrate. The source region, the epitaxial layer, and the substrate are P-type semiconductors, and the well regions are N-type semiconductors. The gate oxide layer is disposed on the side of the epitaxial layer away from the substrate. The gate oxide layer includes a thick oxide structure and a thin oxide structure. The thin oxide structure overlaps at least partially with the well region. The gate electrode is disposed on the side of the gate oxide layer away from the substrate.

[0016] In some embodiments, the thick oxide structure includes a first sublayer, a second sublayer, and a third sublayer stacked in a direction away from the substrate, wherein the first sublayer includes silicon oxynitride and the third sublayer includes silicon oxynitride.

[0017] According to the semiconductor device fabrication method provided in this application, by providing a first gas atmosphere containing nitrogen and / or fluorine elements during at least one process of thick oxide structure growth and annealing, fluorine ions or nitrogen ions can passivate the dangling bonds caused by stress concentration during the thick oxide structure forming process, forming high-energy Si-F or Si-N bonds. This reduces the probability of device performance degradation due to the combination of defect states, represented by dangling bonds, with charge carriers during the use of the semiconductor device, thereby improving the breakdown voltage performance and reliability of the semiconductor device. Furthermore, the improvement in device performance can be achieved simply by changing the gas atmosphere, resulting in lower process costs and difficulty, and making it easy to implement. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figures 1 to 6 This is a schematic diagram of the process structure of a semiconductor device fabrication method according to some embodiments of this application; Figure 7 This is a schematic diagram of the structure of the first intermediate device in the method for fabricating a semiconductor device according to some embodiments of this application; Figure 8 This is a schematic diagram of the structure of the first intermediate device in the fabrication method of the semiconductor device in some other embodiments of this application; Figures 9 to 10 for Figure 8 A schematic diagram of a fabrication process for the first intermediate device is shown. Figures 11 to 12 for Figure 8 A schematic diagram of another fabrication process for the first intermediate device is shown. Figure 13 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of this application.

[0020] The accompanying drawings may not be drawn to scale.

[0021] The specific marking information in the attached diagram is as follows: 01. Drain; 02. Source; 03. Gate; 101. Exposed surface; 110. Substrate; 120. Epitaxial layer; 121. Well region; 122. Source region; 210, Oxide Pad; 220, Barrier Layer; 221, Buffer Layer; 222, Oxide Barrier Layer; 310. Thick oxygen structure; 320. Thin oxygen structure; 400. Interlayer dielectric layer; Thickness direction Z; First direction X. Detailed Implementation

[0022] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0024] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0028] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0029] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0030] Semiconductor devices are electronic devices whose conductivity lies between that of good conductors and insulators. They utilize the unique electrical properties of semiconductor materials to perform specific functions, such as switching control, signal processing, and power conversion in modern electronic systems. It is understandable that the performance of semiconductor devices has a significant and undeniable impact on the performance of the electronic systems they operate in.

[0031] Among them, the Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor (VDMOS) occupies an irreplaceable position in fields such as low- and medium-voltage power management, automotive electronics, and motor drives due to its significant advantages such as high input impedance, nanosecond-level switching speed, easy voltage drive, and excellent parallel current sharing capability brought by positive temperature coefficient.

[0032] In VDMOS devices, the gate oxide layer is an insulating dielectric film located between the gate and the channel region. Its thickness and quality directly determine the threshold voltage, transconductance, and blocking characteristics of the device, making it the functional heart of the entire device. To improve single-event total dose reliability, VDMOS often introduces a locally thick oxide layer structure, that is, an oxide layer thicker than that in the channel region is grown at the gate edge or under the field plate. This is used to withstand lateral voltage drops, reduce gate-drain Miller capacitance, and prevent premature surface breakdown.

[0033] However, the fabrication of localized thick oxide regions typically relies on prolonged high-temperature thermal oxidation or complex processes combined with chemical vapor deposition. Since silicon expands nearly twice in volume when oxidized to silicon dioxide, and given the significant difference in their coefficients of thermal expansion, substantial mechanical stress and lattice mismatch inevitably accumulate at the interface between the thick oxide and silicon. This process disrupts the regular bonds of silicon atoms at the interface, forming numerous unsaturated dangling bonds. Subsequent patterning etching and wet cleaning also introduce additional damage to the interface, resulting in a significantly higher interface state density in the localized thick oxide region compared to the thin gate oxide region above the channel.

[0034] These dangling bonds, acting as interface trap centers, continuously capture and release channel carriers, causing threshold voltage drift, transconductance degradation, and a surge in low-frequency noise. More seriously, under high electric field and high temperature operating stress, dangling bonds can act as "stepping stones" for charge trapping, accelerating the accumulation of defects and the formation of penetration paths within the gate oxide layer, significantly exacerbating the risk of breakdown over time, and severely deteriorating long-term reliability indicators such as negative bias temperature instability.

[0035] To address the problems of the prior art, this application provides a semiconductor device and its fabrication method, which can improve the quality of the gate oxide layer of the semiconductor device, thereby optimizing the breakdown voltage performance and reliability of the semiconductor device. The fabrication method of the semiconductor device provided in this application is described below.

[0036] Firstly, please refer to Figures 1 to 6 This application provides a method for fabricating a semiconductor device, the method comprising: S100. A protective layer is prepared on the top of the substrate. The protective layer includes a pad oxide layer 210 and a barrier layer 220 stacked together. The pad oxide layer 210 includes a region to be grown and a sacrificial region. S200: The barrier layer 220 is patterned to form a patterned barrier layer 220 with a first window. The area to be grown is exposed through the first window to obtain the first intermediate device. S300. The first intermediate device is subjected to thermal oxidation treatment to allow the region to be grown to grow epitaxially and form a thick oxygen structure 310 to obtain a second intermediate device. A portion of the thick oxygen structure 310 in the second intermediate device is exposed through the first window. The second intermediate device is subjected to annealing treatment. At least one of the thermal oxidation treatment and annealing treatment is carried out in a first gas atmosphere, which includes at least one of nitrogen and fluorine elements. S400, Remove the sacrificial region and the patterned blocking layer 220 above the sacrificial region to expose the thick oxide structure 310 and the exposed surface 101 of the substrate distributed around the thick oxide structure 310. S500, a thin oxide structure 320 is formed on the exposed surface 101 of the substrate to obtain a third intermediate device. The third intermediate device has a front side and a back side separated along the thickness direction Z. The thick oxide structure 310 and the thin oxide structure 320 are located on the front side of the third intermediate device. S600. A gate electrode 03 and a source electrode 02 are formed on the positive side of the third intermediate device. After flipping the third intermediate device, a drain electrode 01 is formed on the back side of the third intermediate device to obtain a semiconductor device.

[0037] Specifically, in step S100, the substrate includes a semiconductor material, which may be silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). It is understood that the substrate may also include, but is not limited to, the aforementioned semiconductor materials.

[0038] Optionally, the substrate includes a substrate 110 and an epitaxial layer 120 stacked together. A well region 121 is formed on the side of the epitaxial layer 120 facing away from the substrate 110, and an active region 122 is formed on the side of the well region 121 facing away from the substrate 110. The thick oxide structure 310 and the thin oxide structure 320 are fabricated after the well region 121 and the active region 122. The substrate 110, the epitaxial layer 120, and the active region 122 are semiconductors of a first conductivity type, and the well region 121 is a semiconductor of a second conductivity type. In other words, the semiconductor device employs a post-gate oxide process.

[0039] Optionally, the substrate includes a substrate 110 and an epitaxial layer 120 stacked together, with thick oxide structure 310 and thin oxide structure 320 fabricated before the well region 121 and the source region 122, wherein the epitaxial layer 120 and the substrate 110 are semiconductors of a first conductivity type. In other words, the semiconductor device employs a gate oxide first process.

[0040] For ease of explanation, the first conductivity type semiconductor will be described as a P-type silicon-based semiconductor, and the second conductivity type semiconductor as an N-type silicon-based semiconductor. It will be understood that in other embodiments, the first conductivity type semiconductor will be an N-type semiconductor, and the second conductivity type semiconductor will be a P-type semiconductor.

[0041] It is understood that in step S100, the pad oxide layer 210 is disposed between the substrate and the barrier layer 220. The pad oxide layer 210 is used to absorb the stress difference between the substrate and the barrier layer 220 in subsequent process flows to achieve physical buffering and reduce process damage to the substrate.

[0042] Optionally, the pad oxide layer 210 includes silicon dioxide or silicon oxynitride, and the barrier layer 220 includes silicon nitride. The pad oxide layer 210 prevents the silicon in the substrate from forming weak areas of localized nitridation due to the reaction of oxygen or moisture with silicon nitride during thermal oxidation, thus avoiding degradation of the breakdown performance of the semiconductor device; it also prevents silicon nitride from directly contacting silicon and causing crystal defects.

[0043] Optionally, in step S200, the barrier layer 220 is patterned by a partial removal process through etching to form a first window that exposes part of the area to be grown in the pad oxide layer 210.

[0044] Optionally, in step S200, the orthographic projection of the first window on the substrate falls within the orthographic projection range of the area to be grown on the substrate.

[0045] Optionally, in step S300, the thermal oxidation process includes at least one dry oxidation process performed under a first gas atmosphere. That is, the first intermediate device is heated at least with oxygen and the first gas atmosphere introduced to grow new silicon dioxide at the interface between the substrate and the pad oxide layer 210, thereby thickening the area to be grown through the first window to obtain a thick oxide structure 310. Since oxygen can pass through the pad oxide layer 210, the interface between the pad oxide layer 210 and the substrate at the bottom edge of the first window can also form new silicon dioxide under oxygen and the first gas atmosphere. That is, a part of the thick oxide structure 310 is exposed through the first window, and another part is covered by the barrier layer 220.

[0046] Optionally, in step S300, the annealing process is performed under a first gas atmosphere, by providing a first gas atmosphere so that at least a portion of the nitrogen atoms or fluorine atoms can be bonded by silicon dangling bonds at the interface between the substrate and the pad oxide layer through the thick oxide structure 310, so as to passivate the thick oxide structure 310 with nitrogen or fluorine.

[0047] Optionally, in step S300, the annealing process includes multiple segmented annealing processes, wherein at least one annealing process is performed under a first gas atmosphere.

[0048] Specifically, in step S300, the first gas atmosphere including at least one of nitrogen and fluorine means that the first gas atmosphere includes at least one of elemental nitrogen, nitrogen ions, elemental fluorine, and fluorine ions.

[0049] Optionally, in step S300, the first gas atmosphere includes nitrogen ions, and / or, the first gas atmosphere includes fluoride ions. The first gas atmosphere can facilitate the formation of high-energy Si-N and Si-F bonds during thermal oxidation treatment to reduce defect states inside the thick oxygen structure 310 and improve the forming quality of the thick oxygen structure 310.

[0050] Specifically, in step S400, the patterned barrier layer 220 and the sacrificial area of ​​the pad oxide layer 210 are removed sequentially by at least two etching processes, so as to expose the thick oxide structure 310 and the portion of the substrate not covered by the thick oxide structure 310, and the portion of the substrate not covered by the thick oxide structure 310 forms the exposed surface 101.

[0051] Subsequently, in step S500, a thin oxide structure 320 is prepared above the exposed surface 101 of the substrate to form a gate oxide layer including a thick oxide structure 310 and a thin oxide structure 320, thereby obtaining a third intermediate device with a gate oxide layer formed above the substrate. The third intermediate device has a front side and a back side separated along the thickness direction Z, and the gate oxide layer is located on the front side of the third intermediate device.

[0052] It is understandable that in step S600, the source electrode 02 is prepared after the gate electrode 03, and the thin oxide structure 320 needs to be patterned before the source electrode 02 is prepared so that the source region 122 in the substrate is exposed, so that the source electrode 02 can form an electrical connection with the source region 122 after preparation.

[0053] In step S600, the order of fabrication of the gate electrode 03 and the drain electrode 01 can be adjusted. That is, in the actual execution of step S600, the gate electrode 03 and the source electrode 02 can be fabricated on the positive side of the third intermediate device first, and then the third intermediate device can be flipped to fabricate the drain electrode 01 on the back side. Alternatively, the third intermediate device can be flipped to the back side to fabricate the drain electrode 01 first, and then flipped again to form the third intermediate device with the drain electrode 01, and the gate electrode 03 and the source electrode 02 can be fabricated sequentially on the positive side.

[0054] It is understood that step S600 also includes preparing an interlayer dielectric layer 400 between the gate electrode 03 and the source electrode 02 to provide an insulating gap between the gate electrode 03 and the source electrode 02.

[0055] According to the semiconductor device fabrication method provided in the first aspect of this application, firstly, in step S100, a protective layer composed of a pad oxide layer 210 and a barrier layer 220 is formed on the substrate. The pad oxide layer 210 protects the substrate and reduces process damage while providing a growth basis for the subsequent thick oxide structure 310. The barrier layer 220 above the pad oxide layer 210 is used to limit the growth range of the pad oxide layer 210. In step S200, the barrier layer 220 is patterned to form a patterned barrier layer 220 with a first window. The area to be grown is exposed through the first window to obtain a first intermediate device. The barrier layer 220 can prevent the sacrificial area of ​​the lower pad oxide layer 210 from contacting oxygen, while the area to be grown of the pad oxide layer 210 exposed through the first window can contact oxygen to achieve a local thickening effect. In step S300, the first intermediate device is... Thermal oxidation is performed to thicken the growth area under a first gas atmosphere to obtain a second intermediate device, and / or the second intermediate device is annealed under a first gas atmosphere. In this process, at least a portion of the defect states inside the thick oxide structure 310 react with the first gas atmosphere to convert into high-energy bonds, thus giving the thick oxide structure 310 better quality. Through steps S400 and S500, the barrier layer 220 and the sacrificial region of the unthickened pad oxide layer 210 are removed, and a new thin oxide structure 320 is formed above and below the substrate to obtain a third intermediate device. The thick oxide structure 310 and the thin oxide structure 320 can achieve an insulating gap on the upper surface of the substrate to facilitate the subsequent fabrication of the gate electrode 03 and the source electrode 02 of the semiconductor device. Finally, through step S600, the gate electrode 03, the source electrode 02, and the drain electrode 01 are fabricated on the front and back sides of the third intermediate device, respectively, to obtain a semiconductor device with excellent withstand voltage performance and low fabrication difficulty.

[0056] According to the semiconductor device provided in the first aspect of this application, by providing a first gas atmosphere containing nitrogen and / or fluorine elements during at least one process of thermal oxidation growth and annealing of the thick oxide structure 310, fluorine ions or nitrogen ions can form high-energy Si-F or Si-N bonds on the dangling bonds caused by stress concentration during the forming process of the thick oxide structure 310. This reduces the probability of device performance degradation due to the combination of defect states, represented by dangling bonds, with charge carriers during the use of the thick oxide structure 310, thereby improving the breakdown voltage performance and reliability of the semiconductor device. Furthermore, the improvement in device performance can be achieved simply by changing the gas atmosphere, resulting in lower process costs and difficulty, and making it easier to implement.

[0057] According to some embodiments of the first aspect of this application, the substrate includes a JFET region, and the area to be grown in the pad oxide layer at least partially overlaps with the JFET region. The fabrication method includes: S011. Fluorine ions are implanted into the JFET region of the substrate.

[0058] Step 011 is executed before step 200.

[0059] Optionally, step S011 is executed before step S100, or step S011 is executed after step S100.

[0060] Optionally, in step S011, boron difluoride or boron trifluoride is implanted into the JFET region of the substrate to achieve fluoride ion implantation.

[0061] Optionally, the preparation method further includes: S012, Anneal the substrate.

[0062] Therefore, fluoride ions in the JFET region are activated and diffuse to the interface between the substrate and the pad oxide layer to form high-energy Si-F bonds, thereby reducing the dangling bonds inside the pad oxide layer. This reduces the probability of dangling bonds being occupied by hydrogen ions and forming low-energy Si-H bonds during subsequent fabrication, thus improving the quality of the thick oxide structure 310.

[0063] According to some embodiments of the first aspect of this application, please refer to Figure 7 In step S100, the barrier layer 220 includes a buffer layer 221 and an oxide barrier layer 222. The coefficient of thermal expansion of the buffer layer 221 is between the coefficient of thermal expansion of the pad oxide layer and the coefficient of thermal expansion of the oxide barrier layer 222.

[0064] It is understandable that the pad oxide layer 210, which has a high oxygen permeability, and the oxide barrier layer 222, which has a low oxygen permeability, are made of different materials and have different coefficients of thermal expansion. During the subsequent thermal oxidation process, the interface between the pad oxide layer 210 and the oxide barrier layer 222 is prone to warping due to the difference in thermal deformation. This thermal stress mismatch is particularly noticeable at the edge of the first window and causes the edge of the thick oxygen structure 310 to be stretched, forming a steep slope with poor interface quality.

[0065] By introducing a buffer layer 221 with a thermal expansion coefficient between the pad oxide layer 210 and the oxide barrier layer 222, a thermal expansion coefficient gradient design can be formed inside the protective layer. The thermal deformation of the buffer layer 221 is between that of the pad oxide layer 210 and the oxide barrier layer 222, thereby suppressing the warping trend at the interface between the barrier layer 220 and the pad oxide layer 210. This alleviates the pulling effect of the barrier layer 220 on the pad oxide layer 210, reduces the slope of the steep slope, and improves the interface quality at the edge of the thick oxide structure 310, thereby improving the quality of the thick oxide structure 310 and making the final semiconductor device have better voltage resistance and reliability.

[0066] The thickness of the pad oxide layer 210 is less than the thickness of the oxide barrier layer 222, which allows the oxide barrier layer 222 to more effectively reduce the contact between the sacrificial area and oxygen during the subsequent thermal oxidation process, and to more precisely control the forming range of the thick oxide structure 310.

[0067] Optionally, the thickness of the buffer layer 221 is greater than the thickness of the pad oxide layer 210 to form a better thermal buffering effect and further improve the interface quality of the thick oxide structure 310 at the edge location.

[0068] Alternatively, the thickness of the buffer layer 221 may be less than the thickness of the oxide barrier layer 222, in order to reduce the difficulty of subsequent patterning of the barrier layer 220.

[0069] According to some embodiments of the first aspect of this application, the pad oxide layer 210 includes silicon dioxide, and the oxide barrier layer 222 includes silicon nitride.

[0070] Among them, silicon dioxide has relatively low density, which can play a partial flexible buffer role when warping occurs at the interface between the substrate and the barrier layer 220, preventing further deterioration of the quality at the edge of the thick oxide structure 310; while silicon nitride has high structural consistency at high temperature, which can maintain good oxygen barrier ability during thermal oxidation process. In addition, the etching selectivity between silicon nitride and silicon dioxide is relatively high, which facilitates the patterning process of the barrier layer 220.

[0071] Optionally, the buffer layer 221 includes at least one of polycrystalline silicon and silicon oxynitride to achieve thermal stress buffering between silicon dioxide and silicon nitride.

[0072] In some examples, the buffer layer 221 includes a polysilicon layer disposed between the pad oxide layer 210 and the oxide barrier layer 222 to form a thermal stress buffering effect.

[0073] In other examples, the buffer layer 221 includes a polycrystalline silicon layer and a silicon oxynitride layer stacked together. The polycrystalline silicon layer is disposed above the pad oxide layer 210, and the silicon oxynitride layer is disposed above the polycrystalline silicon layer. The polycrystalline silicon layer and the silicon oxynitride layer can form multiple thermal expansion coefficient gradients between the pad oxide layer 210 and the oxide barrier layer 222 to further alleviate the warping phenomenon caused by the thermal expansion coefficient mismatch between the pad oxide layer 210 and the oxide barrier layer 222. The polycrystalline silicon layer can be directly fabricated above the pad oxide layer 210, or, before step S300 is executed, the barrier layer 220 includes a monocrystalline silicon layer, a silicon oxynitride layer, and an oxide barrier layer 222 stacked together. During step S300, the monocrystalline silicon layer is transformed into a polycrystalline silicon layer and absorbs part of the thermal stress.

[0074] In some other examples, the buffer layer 221 includes a silicon oxynitride layer. This silicon oxynitride layer is a single, continuous layer, or it is divided into multiple sublayers along the thickness direction Z, each sublayer having a different nitrogen-to-oxygen ratio and therefore a different coefficient of thermal expansion. Specifically, along the direction away from the substrate, the nitrogen content increases and the oxygen content decreases within the sublayers.

[0075] For example, the buffer layer includes SiO x N y Along the direction away from the pad oxide layer, the ratio of x to y, x / y, remains constant or decreases, so that the coefficient of thermal expansion of the buffer layer near the pad oxide layer is closer to that of the pad oxide layer, and the coefficient of thermal expansion of the buffer layer near the oxide barrier layer is closer to that of the oxide barrier layer. As an example, the change in the ratio of x to y in the thickness direction Z can be achieved by adjusting the flow ratio of N2O gas to NH3 gas during the buffer layer forming process.

[0076] According to some embodiments of the first aspect of this application, the thickness of the pad oxide layer 210 is 100 to 300 angstroms.

[0077] Specifically, the thickness of the pad oxide layer 210 can be selected as one of 100 angstroms, 125 angstroms, 150 angstroms, 175 angstroms, 200 angstroms, 225 angstroms, 250 angstroms, 275 angstroms, 300 angstroms or a value falling within any two of the aforementioned ranges.

[0078] Optionally, the thickness of the pad oxide layer 210 is less than the thickness of the thin oxide structure 320. The pad oxide layer 210 not only protects the substrate below, but also improves the surface quality of the exposed surface 101 of the substrate after the subsequent removal of the sacrificial area, improves the interface quality between the thin oxide structure 320 and the substrate, and enhances the reliability of the gate oxide layer, while minimizing the consumption of the implantation thickness.

[0079] Therefore, by limiting the thickness of the pad oxide layer 210 to the above range, the substrate can be effectively protected from process damage, while mitigating the interface quality degradation caused by the pulling of the barrier layer 220 during the growth of the area to be grown of the pad oxide layer 210.

[0080] According to some embodiments of the first aspect of this application, the first window includes a communicating first opening and a second opening, see [reference needed]. Figures 11 to 12 Step S200 includes: S210A: The oxide barrier layer 222 is patterned using a first mask to form a first opening, and a portion of the buffer layer 221 is exposed through the first opening. S220A: The buffer layer 221 exposed through the first opening is patterned using a second mask to form a second opening. A portion of the area to be grown is exposed through the second opening, and the orthographic projection of the second opening on the substrate falls within the orthographic projection range of the first opening on the substrate.

[0081] The first intermediate device prepared through the above steps can be found in [reference]. Figure 8 .

[0082] In particular, by forming a stepped structure of buffer layer 221 and oxide barrier layer 222 inside the barrier layer, the tensile force of oxide barrier layer 222 on the thick oxide structure 310 during growth is reduced, and the deformation at the edge of the thick oxide structure 310 is further alleviated.

[0083] According to other embodiments of the first aspect of this application, the first window includes a communicating first opening and a second opening, see [reference needed]. Figures 9 to 10 Step S220 includes: S210B: The barrier layer 220 is patterned using a second mask to form a second opening, and a portion of the area to be grown is exposed through the second opening. S220B, The oxide barrier layer 222 with the second opening is patterned using a first mask to form the first opening, and the orthogonal projection of the second opening on the substrate falls within the orthogonal projection range of the first opening on the substrate.

[0084] The first intermediate device prepared through the above steps can be found in [reference]. Figure 8 .

[0085] The preparation of the second opening first facilitates the alignment of the first window and helps improve the preparation accuracy of the thick oxygen structure 310.

[0086] According to some embodiments of the first aspect of this application, step S300 includes: S310. The first intermediate device is subjected to dry oxidation treatment to thicken the area to be grown to form the first sub-part, thus obtaining a primary processed device. S320. Perform wet oxidation treatment on the primary processing device to thicken the first sub-part to form the second sub-part, thus obtaining the secondary processing device. S330. The secondary processing device is subjected to dry oxidation treatment to thicken the second sub-part to form a thick oxygen structure 310, thereby obtaining the second intermediate device.

[0087] At least one of steps S310 and S330 is performed in a first gas atmosphere to form high-energy Si-N or Si-F bonds in the final thick oxide structure 310, thereby reducing the number of dangling bonds inside the thick oxide structure 310, improving the quality of the thick oxide structure 310, and optimizing the reliability of the semiconductor device.

[0088] Optionally, when performing the dry oxidation process under the first gas atmosphere, the first gas atmosphere is introduced before oxygen, or the first gas atmosphere and oxygen are introduced simultaneously.

[0089] Optionally, the first gas atmosphere includes at least one of nitrous oxide, nitrogen monoxide, ammonia, nitrogen trifluoride, and carbon tetrafluoride.

[0090] It should be noted that performing at least one of steps S310 and S330 in the first gas atmosphere means that step S310 is performed in a nitrogen-containing gas atmosphere or a fluorine-containing gas atmosphere, and / or step S330 is performed in a nitrogen-containing gas atmosphere or a fluorine-containing gas atmosphere.

[0091] For ease of distinction, the first gas atmosphere in step S310 is referred to as the first atmosphere, and the first gas atmosphere in step S320 is referred to as the second atmosphere.

[0092] Optionally, the first atmosphere and the second atmosphere have the same composition, or the first atmosphere and the second atmosphere have different compositions.

[0093] Optionally, the concentrations of the first atmosphere and the second atmosphere are the same, or the concentrations of the first atmosphere and the second atmosphere are different.

[0094] Optionally, the flow rates of the first atmosphere and the second atmosphere are the same, or the flow rates of the first atmosphere and the second atmosphere are different.

[0095] Optionally, the first atmosphere and the second atmosphere may be introduced at the same time, or the first atmosphere and the second atmosphere may be introduced at different times.

[0096] Optionally, the first atmosphere includes nitrogen ions, and the second atmosphere includes either nitrogen ions or fluoride ions. To reduce the degradation of the first substructure caused by the formation of hydrofluoric acid from the contact between fluoride ions and water vapor during the wet oxidation process, the fluoride-containing gas atmosphere is introduced after the wet oxidation process. This optimizes the quality of the thick oxygen structure 310 while fluoride ions occupy dangling bonds.

[0097] Alternatively, the second atmosphere may be introduced simultaneously with oxygen to simplify the process flow of step S330.

[0098] Alternatively, the second atmosphere is introduced after the oxygen to reduce the probability of fluoride ions reacting with water vapor, which would lead to performance degradation of the thick oxygen structure 310.

[0099] Therefore, by providing a first atmosphere and a second atmosphere respectively in the two dry oxidation processes, the internal defect states of the thick oxide structure 310 are further reduced and the withstand voltage performance of the semiconductor device is optimized.

[0100] According to some embodiments of the first aspect of this application, step S300 includes: S340. Anneal the second intermediate device under a first gas atmosphere.

[0101] It should be noted that the purpose of step S340 is to provide a nitrogen-containing gas atmosphere or a fluorine-containing gas atmosphere during the annealing process of the second intermediate device, so that at least some of the dangling bonds inside the thick oxygen structure 310 can be passivated to form high-energy Si-N or Si-F bonds.

[0102] For ease of distinction, the first gas atmosphere in step S340 will be referred to as the third atmosphere.

[0103] Optionally, the third atmosphere may have a different composition from both the first and second atmospheres, or the third atmosphere may have the same composition as at least one of the first and second atmospheres.

[0104] Optionally, the concentration of the third atmosphere is different from both the first and second atmospheres, or the concentration of the third atmosphere is the same as that of at least one of the first and second atmospheres.

[0105] Optionally, the flow rate of the third atmosphere is different from that of the first atmosphere and the second atmosphere, or the flow rate of the third atmosphere is the same as that of at least one of the first atmosphere and the second atmosphere.

[0106] Optionally, the timing of the introduction of the third atmosphere is different from that of the first atmosphere and the second atmosphere, or the timing of the introduction of the third atmosphere is the same as that of at least one of the first atmosphere and the second atmosphere.

[0107] According to some embodiments of the first aspect of this application, in step S400, the barrier layer 220 and the pad oxide layer 210 are selectively removed by a wet etching process to reduce the unintended removal of the thick oxide structure 310.

[0108] Optionally, the oxide barrier layer 222 includes a silicon nitride layer, which is selectively removed by phosphoric acid.

[0109] Optionally, the buffer layer 221 includes a polysilicon layer, and the pad oxide layer 210 includes a silicon dioxide layer, wherein the polysilicon layer and the silicon dioxide layer are selectively removed by hydrofluoric acid.

[0110] According to some embodiments of the first aspect of this application, in step S500, the thin oxide structure 320 is prepared by a thermal growth process, and the growth temperature of the thin oxide structure 320 is lower than the push-in temperature of the substrate, so as to reduce the probability of damage defects forming in the well region 121 during the preparation of the thin oxide structure 320, reduce the generation of defect states, and improve the reliability of the gate oxide layer and the withstand voltage performance of the semiconductor device.

[0111] Secondly, please refer to Figure 13 This application provides a semiconductor device fabricated using the fabrication method provided in any of the preceding embodiments. The semiconductor device includes a substrate 110, an epitaxial layer 120, a gate oxide layer, and a gate electrode 03. The epitaxial layer 120 is disposed on one side of the substrate 110 along the thickness direction Z. A plurality of well regions 121 are formed on the side of the epitaxial layer 120 away from the substrate 110, spaced apart along a first direction X. A source region 122 is provided inside the well region 121 on the side away from the substrate 110. The gate oxide layer is disposed on the side of the epitaxial layer 120 away from the substrate 110. The gate oxide layer includes a thick oxide structure 310 and a thin oxide structure 320. The thin oxide structure 320 overlaps at least partially with the well region 121. The gate electrode 03 is disposed on the side of the gate oxide layer away from the substrate 110.

[0112] Optionally, the source region 122, the epitaxial layer 120 and the substrate 110 are P-type semiconductors, and the well region 121 is an N-type semiconductor.

[0113] Optionally, the source region 122, the epitaxial layer 120 and the substrate 110 are N-type semiconductors, and the well region 121 is a P-type semiconductor.

[0114] Optionally, the thick oxide structure 310 includes silicon dioxide and silicon oxynitride. It is understood that, due to the introduction of a nitrogen-containing first gas atmosphere during the thermal oxidation growth of the thick oxide structure 310, the final thick oxide structure 310 will include silicon oxynitride as a byproduct.

[0115] It is understood that the semiconductor device also includes a source electrode 02 disposed on the same side as the gate electrode 03, a drain electrode 01 disposed on the opposite side of the gate electrode 03, and an interlayer dielectric layer 400 for insulating the gate electrode 03 and the source electrode 02.

[0116] Optionally, the gate electrode 03 comprises a polycrystalline silicon material, or the gate electrode 03 comprises a metallic material.

[0117] According to some embodiments of the second aspect of this application, the thick oxide structure 310 includes a first sublayer, a second sublayer and a third sublayer stacked along a direction away from the substrate 110, wherein the first sublayer is prepared by step S310, the second sublayer is prepared by step S320 and the third sublayer is prepared by step S330.

[0118] Optionally, the first sublayer includes silicon oxynitride. Specifically, the first intermediate device is first subjected to dry oxidation treatment in a first gas atmosphere to optimize the interface quality between the thick oxide structure 310 and the substrate, reduce defect states of the thick oxide structure 310 near the substrate, thereby improving the quality of the thick oxide structure 310 and enhancing the breakdown voltage performance of the semiconductor device.

[0119] Optionally, the second sublayer is silicon dioxide. Specifically, the primary processing device is subjected to wet oxidation to accelerate the fabrication of the thick oxide structure 310 and shorten the semiconductor device fabrication process.

[0120] Optionally, the third sublayer comprises silicon oxynitride or fluorinated silicon oxynitride. Specifically, the secondary processed device after wet oxidation is subjected to dry oxidation under a second gas atmosphere to reduce defect states in the subsequent contact portion between the thick oxide structure 310 and the gate electrode 03, thereby further improving the quality of the thick oxide structure 310 and optimizing the breakdown voltage performance of the semiconductor device.

[0121] According to some embodiments of the second aspect of this application, to simplify the process flow, the thick oxide structure 310 includes a first sublayer and a second sublayer stacked along a direction away from the substrate 110. That is, the thick oxide structure 310 is formed in the semiconductor fabrication process by only one dry oxidation process and one wet oxidation process.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A protective layer is prepared on top of the substrate. The protective layer includes a pad oxide layer and a barrier layer stacked together. The pad oxide layer includes a region to be grown and a sacrificial region. The barrier layer is patterned to form a patterned barrier layer with a first window, and the area to be grown is exposed through the first window to obtain a first intermediate device; The first intermediate device is subjected to thermal oxidation to allow the region to be grown to grow epitaxially and form a thick oxygen structure, thereby obtaining a second intermediate device. A portion of the thick oxygen structure in the second intermediate device is exposed through the first window. The second intermediate device is then subjected to annealing. At least one of the thermal oxidation and annealing processes is carried out in a first gas atmosphere, which includes at least one of nitrogen and fluorine. Remove the sacrificial region and the patterned barrier layer above the sacrificial region to expose the thick oxide structure and the exposed surface of the substrate distributed around the thick oxide structure; A thin oxide structure is formed on the exposed surface of the substrate to obtain a third intermediate device. The third intermediate device has a front side and a back side separated along the thickness direction. The thick oxide structure and the thin oxide structure are located on the front side of the third intermediate device. A gate electrode and a source electrode are formed on the positive side of the third intermediate device. After flipping the third intermediate device, a drain electrode is formed on the back side of the third intermediate device to obtain a semiconductor device.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thermal oxidation treatment of the first intermediate device includes: The first intermediate device is subjected to dry oxidation treatment to thicken the area to be grown to form the first sub-part, thus obtaining a primary processed device; A wet oxidation process is performed on the primary processing device to thicken the first sub-part and form the second sub-part, thus obtaining a secondary processing device. The secondary processing device is subjected to dry oxidation treatment to thicken the second sub-part to form a thick oxygen structure, thereby obtaining the second intermediate device. The process of dry oxidation of the first intermediate device and dry oxidation of the secondary processing device are performed under a first gas atmosphere.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The first gas atmosphere is introduced simultaneously with or before oxygen; and / or, the first gas atmosphere includes at least one of nitrous oxide, nitric oxide, ammonia, nitrogen trifluoride, and carbon tetrafluoride.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate includes a JFET region, and the area to be grown in the pad oxide layer at least partially overlaps with the JFET region. The fabrication method further includes: Before thermal oxidation of the first intermediate device, fluorine ions are implanted in the JFET region.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The barrier layer includes a buffer layer and an oxide barrier layer. The coefficient of thermal expansion of the buffer layer is between that of the pad oxide layer and the oxide barrier layer. The thickness of the pad oxide layer is less than that of the oxide barrier layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The pad oxide layer includes silicon dioxide, the oxide barrier layer includes silicon nitride, and the buffer layer includes at least one of polycrystalline silicon and silicon oxynitride. Preferably, the buffer layer comprises silicon oxynitride, and the coefficient of thermal expansion of the buffer layer remains unchanged or increases in the direction away from the pad oxide layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The thickness of the oxide layer is 100–300 angstroms; and / or the thickness of the oxide barrier layer is 1000–1300 angstroms; and / or the thickness of the buffer layer is 300–700 angstroms.

8. The method for fabricating a semiconductor device according to claim 5, characterized in that, The process of patterning the barrier layer to form a patterned barrier layer with a first window includes: The oxide barrier layer is patterned using a first mask to form a first opening, through which a portion of the buffer layer is exposed. The buffer layer exposed through the first opening is patterned using a second mask to form a second opening. The area to be grown is exposed through the second opening, and the orthographic projection of the second opening on the substrate falls within the orthographic projection range of the first opening on the substrate.

9. A semiconductor device, characterized in that, The semiconductor device is prepared by the preparation method according to any one of claims 1 to 8, and comprises: Substrate; An epitaxial layer is disposed on one side of the substrate along the thickness direction. A plurality of well regions are formed on the side of the epitaxial layer away from the substrate and spaced apart along a first direction. A source region is provided inside the well region on the side away from the substrate. The source region, the epitaxial layer and the substrate are P-type semiconductors and the well regions are N-type semiconductors. A gate oxide layer is disposed on the side of the epitaxial layer opposite to the substrate. The gate oxide layer includes a thick oxide structure and a thin oxide structure, and the thin oxide structure overlaps at least partially with the well region. The gate electrode is disposed on the side of the gate oxide layer opposite to the substrate.

10. The semiconductor device according to claim 9, characterized in that, The thick oxide structure includes a first sublayer, a second sublayer, and a third sublayer stacked along a direction away from the substrate, wherein the first sublayer includes silicon oxynitride, and the third sublayer includes silicon oxynitride.

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