A method for manufacturing a low on-resistance fin structure MOS transistor

Abstract

The application relates to the technical field of semiconductor device manufacturing and process data processing, in particular to a manufacturing method of a low-conduction-resistance fin structure MOS tube. The method collects process, intermediate characterization and on-chip electrical property data of fin structure etching, surface treatment, source-drain injection, annealing, gate dielectric and contact formation processes, establishes an associated index according to wafer regions, device positions and process time sequences, constructs a conduction resistance causal contribution chain, and decomposes the conduction resistance into channel resistance, source-drain extension region resistance, gate interface additional resistance and contact resistance contribution; according to a prediction interval, a dominant out-of-tolerance causal path is determined, a cross-process compensation parameter combination is generated in combination with a remaining process adjustable range, and a subsequent process path is determined under the constraints of threshold voltage, leakage, gate dielectric reliability and junction thermal budget. The application can implement subsequent compensation on previous irreversible deviation, reduce reverse superposition of resistance contribution, and reduce conduction resistance and wafer and batch dispersion.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing and process data processing technology, specifically to a method for manufacturing a finned MOSFET with low on-resistance. Background Technology

[0002] Fin-structured metal-oxide-semiconductor field-effect transistors (MOSFETs) enhance the gate's electrostatic control over the channel by forming raised fins on a semiconductor substrate and extending the gate along the top and sides of the fins. Existing manufacturing processes typically involve sequentially performing fin pattern transfer, anisotropic etching, sidewall cleaning or repair, gate dielectric formation, gate material deposition, source / drain ion implantation, thermal annealing, and contact hole and metal contact formation. To achieve lower on-resistance, conventional processes control fin width, fin height, sidewall tilt angle, source / drain doping concentration, impurity activation level, and contact interface state, and adjust the corresponding equipment formulation based on online measurement results for each step. For example, the fin etching process adjusts etching time or gas ratio based on critical dimension measurements; the ion implantation process sets implantation energy and dose based on the target junction depth; the annealing process sets temperature and time trajectories based on impurity activation requirements; and the contact formation process adjusts pre-cleaning and metallization conditions based on contact resistance test results. Each step typically has independent control targets and allowable ranges; as long as intermediate dimensions, material states, or electrical sampling results fall within the corresponding window, subsequent standard processes continue.

[0003] Current low on-resistance manufacturing control often employs correlation analysis or statistical process control based on historical batches. This establishes a regression relationship between the final on-resistance and several process parameters, and corrects highly sensitive parameters when the on-resistance is too high. Some schemes also utilize virtual measurements to estimate undetected fin sidewall damage, doping activation levels, or contact states, and then select subsequent process conditions from a pre-set set of formulations. This type of control typically treats fin channel resistance, source / drain extension region resistance, gate interface additional resistance, and contact resistance as parallel influencing factors of the overall on-resistance, without clearly distinguishing the specific paths through which previous process deviations are transmitted to each resistive component via intermediate states. When fin width shrinks, sidewall roughness increases, or etching damage accumulates, common solutions include increasing the source / drain injection dose, increasing annealing intensity, or strengthening pre-contact cleaning. However, the same adjustment may simultaneously change channel carrier mobility, junction diffusion range, interface defects, and contact reaction states. Because each process is still optimized separately according to local indicators, subsequent adjustments easily cover the surface results of previous deviations without identifying the transmission direction of deviations throughout the entire manufacturing chain.

[0004] There is a lack of a causal relationship between preceding deviations and the final on-resistance in fin structure manufacturing that can be used for subsequent process control. Fin geometric deviations, sidewall damage, doping activation changes, gate interface states, and contact states are continuously transmitted between different processes, forming channel resistance, source / drain extension region resistance, gate interface additional resistance, and contact resistance, respectively. When manufacturing control adjusts parameters based solely on single-process measurement results or overall on-resistance correlation, it is impossible to determine which resistance contribution is primarily causing the current deviation, or which preceding state and process path led to that contribution. Consequently, subsequent processes may compensate for non-dominant factors, or amplify one resistance contribution while reducing another, resulting in intermediate indicators within acceptable ranges for each process, but the final on-resistance remaining high. Especially when fin sidewall damage and fin width deviations are irreversible, without a resistance contribution allocation mechanism that allows for adjustable capabilities in remaining processes, it is difficult for the manufacturing process to achieve targeted cross-process compensation within the constraints of threshold voltage, leakage current, gate dielectric reliability, and junction thermal budget. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a finned MOSFET with low on-resistance, which can solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for manufacturing a fin-structured MOSFET with low on-resistance includes: collecting process data, intermediate characterization data, and on-chip electrical data for each step of fin etching, surface treatment, source / drain injection, annealing, gate dielectric formation, and contact formation; and establishing an associated index according to wafer region, device location, and process sequence. Based on the aforementioned correlation index, a causal contribution chain for on-resistance is constructed, decomposing the on-resistance into contributions from the fin channel resistance, source / drain extension region resistance, gate interface additional resistance, and contact resistance. After the key process is completed, update the prediction range of each resistance contribution and determine the dominant out-of-tolerance causal path; Based on the dominant cause-and-effect path of the deviation and the adjustable range of the remaining processes, a combination of cross-process compensation parameters is generated; Under the constraints of threshold voltage, leakage current, gate dielectric reliability and junction thermal budget, the final values ​​of each resistance contribution of the standard process path and the compensated process path are calculated with the current intermediate state as a common starting point, and the control parameters of the subsequent process are selected and executed. The on-resistance causal contribution chain is corrected based on the final electrical test results.

[0007] Preferably, constructing the on-resistance causal contribution chain includes: classifying fin width, fin height, sidewall tilt angle, and sidewall roughness into the fin geometry; classifying etching damage density and surface defect density into the sidewall damage state; classifying doping concentration distribution and activation ratio into the doping activation state; classifying interface state density and equivalent dielectric state into the gate interface state; and classifying pre-contact surface residue and contact resistance into the contact state. Establish directed connections according to the sequential relationship of each state in the process sequence; Based on the corresponding records of process variable disturbances and state changes in historical batches, the direct connections from process variables to the resistance contribution and the indirect connections transmitted through intermediate states are determined respectively, and mutual exclusion constraints are set for connections sharing intermediate states to form a set of causal paths traceable to specific manufacturing processes.

[0008] Preferably, updating the prediction range of each resistance contribution includes: for each completed key process of the current wafer, mapping the corresponding intermediate characterization data and equipment process data to the state node in the on-resistance causal contribution chain; Call up historical samples that match the current equipment chamber status, material batch, and fin structure layout density to calculate the conditional distribution of each state node; The measurement of missing state nodes is limited to the feasible region determined by the preceding state, the current process record, and the subsequent observable state. By propagating the conditional distribution step by step according to the connection direction of the causal path, the interval estimate of the contribution of each resistance is obtained. Based on the excess of the upper bound of the interval relative to the target resistance budget and the local sensitivity of each path, the candidate causal paths are sorted and the dominant out-of-range causal path is determined.

[0009] Preferably, generating the cross-process compensation parameter combination includes: determining the set of interventionable subsequent processes based on the dominant out-of-tolerance causal path, and calculating the joint response matrix of each subsequent process on the contribution of the fin channel resistance, the source-drain extension region resistance, the gate interface additional resistance, and the contact resistance. The contribution amount that exceeds the target resistance budget is allocated to the set of subsequent processes. Within the equipment executable range of each subsequent process, the formation state of the preceding process, and the thermal accumulation boundary of the subsequent process, the surface treatment intensity, injection energy and angle sequence, annealing temperature and time trajectory, pre-contact cleaning conditions, and contact formation conditions are jointly solved. Candidate combinations that cause any non-target resistance contribution to exceed the corresponding budget are eliminated, forming a set of cross-process compensation parameter combinations sorted by remaining compensation capacity.

[0010] Preferably, determining the direct connection and the indirect connection includes: selecting matching sample pairs from historical batches that have the same layout density, initial fin structure size and material batch but different target process variables; For each matched sample pair, calculate the difference sequence of each state node and each resistance contribution before and after the change of process variables; A candidate direct connection is established when the change of the target process variable is transmitted to the resistance contribution only through a single state node; a candidate indirect connection is established when the change of the target process variable is transmitted sequentially through two or more state nodes. Utilize batch execution path blocking verification that did not participate in connection establishment, and compare the differential transmission results before and after blocking the specified state node; Retain connections that have been verified through path blocking and are oriented in the same direction across different device groups, and record the device group-specific bias as an additional condition for the connection.

[0011] Preferably, limiting the measurement of the missing state node to the feasible domain includes: for the missing state node, extracting its adjacent preceding state node, subsequent observable state node and related process variables; Based on historical stable batches, establish conservation constraints, monotonic constraints, and process reachability constraints between adjacent nodes; Convert the current equipment maintenance records, cumulative chamber operation volume, and material batch offset into constraint boundary correction values; For the state values ​​that simultaneously satisfy conservation constraints, monotonic constraints, process reachability constraints, and modified boundary conditions, interval shrinkage is performed; When new characterization data is added in subsequent processes, the value range of the missing state node is updated in reverse with the new characterization data, and the causal path weights connected to the missing state node are corrected simultaneously.

[0012] Preferably, the contribution amount that exceeds the target resistance budget is allocated to the set of subsequent processes, including: establishing a process compensation capacity vector according to the compensable direction, compensable magnitude and coupling degree of each subsequent process to the non-target resistance contribution in the joint response matrix; Based on the irreversible difference between the state already formed by the preceding process and the target state, deduct the resistance contribution that cannot be eliminated by the remaining processes; The remaining compensable contribution is preferentially allocated to the processes that have a unidirectional inhibitory relationship with the dominant out-of-range causal path and have limited influence on the contribution of other resistances, and then the unallocated portion is transferred to two or more processes with complementary response directions. The compensation capacity vector for each process is updated after each allocation until the remaining contribution is fully allocated or all remaining processes reach their corresponding executable boundaries.

[0013] Preferably, transferring the unallocated portion to two or more processes having the complementary response directions includes: selecting process pairs from the joint response matrix that show a unidirectional decrease in the contribution to the dominant deviation and an inverse change in the contribution to at least one non-target resistance; A joint adjustment trajectory is generated along the intersection region of the process response vectors, and the actual completion state of the previous process is used as the boundary condition of the adjustment range of the next process. The joint adjustment trajectory is discretized according to the sequence of processes to form multiple executable parameter sequences. For each executable parameter sequence, calculate the interval results of each resistance contribution and the reliability constraint margin. Delete parameter sequences whose interval results cross the resistance budget boundary or whose reliability constraint margin is negative, and write the retained sequences into the compensation process path.

[0014] Preferably, the device group-specific bias is recorded as an additional connection condition, including: selecting cross-device batches with the same fin structure layout, material batch and target formula under the same process step, and calculating the center offset and propagation slope of the differential sequence of the corresponding state nodes of each device group; The center offset is decomposed into a stable offset and a drift component that varies with the cumulative operating amount of the chamber; The stable bias, the drift component, and their applicable process range are written into the associated device group in the on-resistance causal contribution chain. When the reference wafer result of the current equipment exceeds the applicable process range, the original equipment additional conditions are paused, the center offset and the propagation slope are re-estimated using the intermediate characterization data of the most recent consecutive batches, and the condition distribution of the corresponding connection is updated with the re-estimated results.

[0015] Preferably, writing the retained sequence into the compensation process path includes: establishing a process node for each retained sequence, consisting of the process parameters, expected intermediate state range, allowable deviation range, and subsequent alternative sequences; After completing a process, the actual intermediate representation results are compared with the expected intermediate state range of the corresponding path node. When the actual result is within the allowable deviation range, proceed to the next step according to the original retained sequence; When the actual results exceed the allowable deviation range, a new continuous process sequence is selected from the subsequent alternative sequences based on the original heat consumption budget, the remaining equipment's executable range, and the unfinished resistance contribution budget. After all processes are completed, the final on-chip electrical data is back-allocated to the process parameters and intermediate states according to the path nodes, and the expected intermediate state range and allowable deviation range of subsequent batches are updated.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. By associating data from fin etching, surface treatment, source / drain implantation, annealing, gate dielectric formation, and contact formation processes according to wafer region, device location, and process sequence, and decomposing the on-resistance into fin channel resistance contribution, source / drain extension region resistance contribution, gate interface additional resistance contribution, and contact resistance contribution, the transmission relationship between previous manufacturing states and the final on-resistance can be pinpointed to a specific causal path. After the completion of critical processes, the predicted range of each resistance contribution is updated using intermediate characterization data. The dominant causal path for the deviation is determined based on the excess of the upper bound of the range relative to the target resistance budget and the path's local sensitivity, ensuring that subsequent process adjustments target the actual source of resistance. Cross-process compensation parameter combinations are generated based on the adjustable range of the remaining processes, and the final values ​​of each resistance contribution are compared between the standard process path and the compensated process path within the constraints of threshold voltage, leakage current, gate dielectric reliability, and junction thermal budget. This avoids simply attributing the overall high on-resistance to a single process, reduces errors in compensation direction, and minimizes situations where one resistance decreases while others increase. It allows irreversible deviations from previous processes to be corrected collaboratively and within boundaries by the remaining processes according to the resistance budget.

[0017] 2. By incorporating fin width, fin height, sidewall tilt angle, sidewall roughness, etching damage density, doping concentration distribution, activation ratio, interface state density, pre-contact surface residue, and contact resistance into corresponding state nodes, and establishing direct and indirect connections according to the sequence of processes, the formation process of each resistance contribution can have a traceable data foundation. Introducing a feasible region jointly defined by the preceding state, current process record, and subsequent observable state for missing measurement states can reduce the interference of missing intermediate states on the update of the contribution interval. Allocating the remaining resistance contribution using the joint response matrix and process compensation capacity vector, and using the actual completion state of the previous process as the boundary condition for the adjustment range of the subsequent process, can maintain continuous constraints between surface treatment, implantation, annealing, and contact formation. After incorporating the stable bias of the equipment group and the drift component that varies with the cumulative operating amount of the chamber into the causal connection conditions, it is possible to distinguish between process state changes and equipment offsets. Finally, the on-chip electrical data is traced back along the compensation path to each process parameter and intermediate state, continuously correcting the prediction interval, allowable deviation range, and connection conditions, ensuring consistent data caliber in manufacturing control across different batches. Attached Figure Description

[0018] Figure 1 A flowchart of closed-loop manufacturing process for fin-structured MOSFETs with low on-resistance; Figure 2 Flowchart for constructing the causal contribution chain of conduction resistance and determining the dominant causal path of out-of-tolerance. Detailed Implementation

[0019] In one embodiment, please refer to Figure 1This invention provides a method for manufacturing a low on-resistance fin-structured MOSFET, comprising: collecting process data, intermediate characterization data, and on-chip electrical data for each step of fin etching, surface treatment, source / drain injection, annealing, gate dielectric formation, and contact formation; establishing an association index according to wafer region, device location, and process sequence; constructing a causal contribution chain for on-resistance based on the association index, decomposing the on-resistance into fin channel resistance contribution, source / drain extension region resistance contribution, gate interface additional resistance contribution, and contact resistance contribution; updating the prediction interval of each resistance contribution and determining the dominant excess causal path after the completion of key processes; and applying the dominant excess causal path... The adjustable range of the remaining processes generates a combination of cross-process compensation parameters; under the constraints of threshold voltage, leakage current, gate dielectric reliability and junction thermal budget, the final value of each resistance contribution of the standard process path and the compensation process path is calculated with the current intermediate state as a common starting point, and the control parameters of the subsequent processes are selected and executed; the causal contribution chain of the on-resistance is corrected according to the final electrical test results. In this embodiment, the independent measurement results of each process are converted into a continuous manufacturing state established around the final on-resistance, so that the preceding deviations that have occurred can be compensated in a constrained manner through the adjustable degrees of freedom of the remaining processes, and the control decision of each process corresponds to the specific source of resistance contribution.

[0020] Specifically, the process data for the fin etching process includes etching recipe identification, process time, chamber operation sequence, and process stability range. Intermediate characterization data includes fin width, fin height, sidewall tilt angle, top rounding degree, and sidewall roughness. The surface treatment process records defect characterization, surface residue, and fin size changes before and after treatment. The source / drain implantation process records implantation sequence, energy level, angle sequence, and wafer orientation. The annealing process records temperature and time trajectory and equipment status. The gate dielectric formation process records uniformity characterization and interface status during dielectric formation. The contact formation process records pre-contact cleaning status, contact material formation process, and contact test results. On-chip electrical data includes on-resistance, threshold voltage, turn-off leakage current, and test structure results used to distinguish the effects of channels and contacts. All types of data retain the original acquisition time, wafer, layout location, and corresponding process stage to avoid covering device location differences with only batch averages.

[0021] In this embodiment, the association index is composed of batch identifier, wafer identifier, device location coordinates, process sequence, and acquisition time. Data generated by the same device location in different processes are connected according to the process sequence to form a vertical manufacturing trajectory. Data generated by different device locations on the same wafer in the same process are connected according to the layout density area, wafer radial area, and fin extension direction to form a horizontal comparison set. Data that cannot be directly located to a single device in the equipment log is allocated to the corresponding manufacturing trajectory according to the process time period coverage relationship. The start and end times of the coverage and the equipment status label are retained during allocation. Subsequent calculations only call the corresponding equipment data when there is an intersection between the process time period and the device manufacturing time period. This allows the process record, intermediate characterization, and final electrical results to be continuously traced back along the same physical manufacturing object.

[0022] ; in, This represents the associated index of the nth manufacturing data entry. Indicates batch identifier, Indicates wafer identification. and Indicates the device position coordinates. Indicates the sequence of operations. When using a correlated index to indicate the time of data collection, only two data entries are considered together. , , and Consistent and When the manufacturing sequence is satisfied, they are connected as the same longitudinal trajectory. For example, the index value of the etching characterization record of a certain fin structure is (7,3,12,8,2,105), and the index value of the characterization record after annealing at the same position is (7,3,12,8,5,268). The two are identified as the preceding and following states of the same device position. However, the record with the index (7,3,13,8,5,268) only enters the adjacent position comparison set and does not participate in the direct state update of the device position.

[0023] To ensure comparability of data from different processes, raw data is baseline-corrected according to a stable reference area within the manufacturing batch after entering the associated index. Dimensional data retains physical quantities and adds deviations relative to the reference area. Defect data is converted into unit area state quantities based on the detection area and effective fin sidewall area. Electrical data establishes a correspondence based on the same test structure and test conditions. Equipment process data is converted into an offset sequence relative to the stable process section of the equipment. If there are repeated measurements in the same process, a confidence weight is established based on the measurement location coverage, repeatability, and acquisition time. The original value, correction value, and confidence weight are saved simultaneously. Subsequent causal contribution calculations do not replace the original record with a single correction value.

[0024] Furthermore, data verification is based on the temporal continuity and physical accessibility of the manufacturing trajectory. If the acquisition time of a record is earlier than the completion time of its preceding process, or if the device position in the record cannot fall into the corresponding wafer layout area, the record will be retained in the original data area but will not be included in the state node calculation. If a characterization value deviates from the repeated measurement result at the same location and the equipment process record does not show a corresponding change, its credibility weight will be reduced instead of being directly deleted. If multiple adjacent positions show changes in the same direction at the same time and are consistent with the changes in the stable range of the equipment, the changes will be identified as process state offsets and included in the horizontal comparison set. Time alignment uses the closed interval formed by the process start time, process end time, and measurement completion time. The association is established only when the manufacturing trajectory and the closed interval of the equipment log intersect, so as to avoid cross-batch logs, rework records, and delayed measurement results from entering the wrong causal path.

[0025] The on-resistance causal contribution chain is based on the physical path of charge carriers from the source region through the source-drain expansion region, the gate-controlled fin channel, and the contact region. It maps manufacturing variables such as changes in the effective channel cross-section of charge carriers, scattering probability, doping activation, and metal-semiconductor contact state to the corresponding resistance contribution. Fin width, fin height, sidewall tilt angle, and sidewall roughness mainly contribute to the state description of the fin channel resistance contribution. The doping distribution and activation state formed by source-drain injection and annealing contribute to the source-drain expansion region resistance contribution. The interface state before and after gate dielectric formation and the residual sidewall damage contribute to the additional resistance contribution of the gate interface. Surface residues before contact, contact reaction state, and contact test results contribute to the contact resistance contribution. At the same time, the same manufacturing state can affect more than two resistance contributions through different transmission paths.

[0026] ; in, This represents the normalized on-resistance. This indicates the contribution of the fin channel resistance. This indicates the contribution of the source-drain extension region resistance. This indicates the contribution of additional resistance at the gate interface. The four components, representing the contribution of contact resistance, always maintain the same physical meaning and are normalized using the same test standard. For example, when the four components at a certain device location are respectively 0.42, 0.18, 0.07, and 0.13, The value is 0.80, if the subsequent contact formation conditions make... The value decreased to 0.09, but the annealing conditions simultaneously... If the value is increased to 0.11, the total value will still be 0.80. Based on this, the control system determines that the combination has not formed a net compensation and continues to search for process paths that do not cause other components to increase in the opposite direction.

[0027] In a preferred embodiment, please refer to Figure 2A causal contribution chain for on-resistance is constructed, including: classifying fin width, fin height, sidewall tilt angle, and sidewall roughness into the fin geometry; classifying etching damage density and surface defect density into the sidewall damage state; classifying doping concentration distribution and activation ratio into the doping activation state; classifying interface state density and equivalent dielectric state into the gate interface state; and classifying pre-contact surface residue and contact resistance into the contact state. Directed connections are established according to the sequential relationship of each state in the process sequence. Based on the corresponding records of process variable disturbances and state changes in historical batches, direct connections from process variables to resistance contributions and indirect connections transmitted through intermediate states are determined, and mutual exclusion constraints are set for connections sharing intermediate states to form a set of causal paths traceable to specific manufacturing processes. Directed connections are only allowed to point from process nodes earlier than the current state to the current state or subsequent states, and the final electrical result is prohibited from being used as the generation condition of the preceding process state.

[0028] In the specific construction, the fin geometry is composed of a state vector consisting of fin width, fin height, sidewall tilt angle, and sidewall roughness at the same device location. The sidewall damage state is determined by the defect characterization after etching and the defect residue after surface treatment. The doping activation state is estimated by the implantation record, annealing trajectory, and intermediate electrical test. The gate interface state is estimated by the sidewall state before gate dielectric formation, dielectric formation process record, and interface-related test structure. The contact state is determined by the residual characterization after cleaning before contact, the contact formation process, and the contact test structure. Each state node saves the numerical range, data source, acquisition process, and reliability. If a data source is missing, the corresponding state node is not deleted, but the node is marked as a state to be constrained and estimated.

[0029] The establishment of directed connections is based on the interferability of process variables and the sequence of processes. Fin structure etching variables can point to the fin geometry state and sidewall damage state. Surface treatment variables can point to the sidewall damage state and are allowed to point to the gate interface state through the sidewall damage state. Source and drain injection variables can point to the doping activation state and are allowed to form a joint path through the annealing variable. Pre-contact cleaning variables can point to the contact state, but must not directly cross the physical intermediate state to point to the fin channel resistance contribution. Mutual exclusion constraints of shared intermediate states are used to prevent the same change from being repeatedly counted in multiple paths. For example, when the sidewall roughness change affects the channel resistance through the sidewall damage state, a parallel direct path without intermediate nodes is no longer established based on the same measurement change.

[0030] Preferably, the directed connectivity coefficients are estimated piecewise within the neighborhood of the current state. First, the historical samples are divided into continuous sub-intervals according to the reachability intervals of the state nodes. Then, the local slope of the change in the target process variable and the subsequent state change is calculated in each sub-interval, and the consistency of the slope direction in adjacent sub-intervals and different equipment groups is checked. Sub-intervals with consistent direction and continuous amplitude are merged into the same applicable connectivity interval. Sub-intervals with changed direction are saved and attached with the preceding state conditions. If the sample only covers a part of the applicable connectivity interval, the uncovered part is not linearly extrapolated, but the corresponding path is marked as not usable for the current compensation solution. This ensures that the connectivity coefficients in the causal contribution chain come from the observable manufacturing state and match the current state interval of the wafer.

[0031] ; Here, k is used to distinguish the four types of resistance contributions. This represents the set of causal paths pointing to the contribution of the k-th type of resistance. Let represent the product of the directed connectivity coefficients in the q-th path. and This represents the lower and upper bounds of the initial state deviation of the q-th path. and This represents the predicted range of the corresponding resistance contribution, such as for a certain path. When the value is 0.6 and the state deviation interval is [0.10, 0.20], the path contribution interval is [0.06, 0.12]. The other path's... When the value is -0.3 and the state deviation interval is [0.05, 0.10], the corresponding interval is sorted by the minimum and maximum values ​​to [-0.03, -0.015]. After the two paths are added together, the interval relationship of positive resistance increase and reverse cancellation is retained.

[0032] In a preferred embodiment, updating the prediction interval for each resistance contribution includes: for each completed critical process of the current wafer, mapping the corresponding intermediate characterization data and equipment process data to state nodes in the on-resistance causal contribution chain; calling historical samples that match the current equipment chamber state, material batch, and fin structure layout density to calculate the conditional distribution of each state node; limiting the measurement of missing state nodes to a feasible region jointly determined by the preceding state, the current process record, and the subsequent observable state; propagating the conditional distribution step by step according to the connection direction of the causal path to obtain the interval estimate of each resistance contribution; based on the excess of the upper bound of the interval relative to the target resistance budget and the local sensitivity of each path, ranking the candidate causal paths and determining the dominant out-of-tolerance causal path, with the matching order of historical samples considering equipment state similarity, material batch similarity, layout density similarity, and process formulation similarity in sequence.

[0033] Historical sample matching does not directly use full batch averaging. Instead, it establishes a local neighborhood for the current device location. The local neighborhood consists of device locations with the same wafer radial region, the same fin extension direction, and similar layout density. Then, manufacturing trajectories that meet the comparable conditions of equipment status and material batch are screened from the local neighborhood. The condition distribution is calculated using a weighted empirical distribution. The weight of each historical trajectory is jointly determined by the distance of equipment status, the distance of material batch, the distance of layout density, and the measurement confidence. The larger the distance, the lower the weight. If the number of comparable trajectories is insufficient, the layout density range is expanded but does not cross the equipment status boundary. The extrapolation introduced by the expanded range is written into the prediction interval instead of being directly incorporated into the central estimate.

[0034] The calculation of conditional distribution preserves the correlation between state nodes. Fin width deviation, sidewall roughness, and etching damage caused by the same process are not sampled independently. Instead, a joint state vector is extracted from the matching historical trajectory and a weighted sample set is formed according to the confidence weight. During interval propagation, state combinations that meet the previous observation conditions are selected from the weighted sample set. Then, the four types of resistance contributions are calculated along the verified path. The lower and upper bounds of the prediction interval are determined by the stable coverage range of the obtained contribution samples. If a state combination violates the process reachability constraint or equipment additional conditions, it is removed before propagation. If two paths share the same intermediate state, the same value is used in the same state combination to prevent the same physical deviation from being repeatedly amplified due to independent sampling.

[0035] The determination of the dominant out-of-range causal path considers the resistance budget excess, path local sensitivity, and path state uncertainty. The resistance budget is determined by the acceptable distribution of the target on-resistance among the four types of resistance contributions. Local sensitivity is obtained by changing the path's initial state near the current state and propagating along the directed connection. Uncertainty is formed by the measurement reliability, the dispersion of historical samples, and the stability of path coefficients. The control system does not directly identify paths with high upper bounds but whose uncertainty mainly comes from missing data as dominant paths. Instead, it first calls the feasible region constraint to narrow down the range of missing states and then recalculates the path ranking.

[0036] ; in, This represents the ranking value of the q-th candidate causal path. This indicates the resistance contribution category pointed to by the q-th path. Indicates the target resistance budget for the category. This indicates the local sensitivity around the current state. This represents the uncertainty caused by missing data and fluctuations in path coefficients. For example, when the upper bound of a path's interval is 0.22, the corresponding budget is 0.16, the local sensitivity is 0.8, and the uncertainty is 0.2, If we take 0.04, the other path also has an upper bound of 0.22, but its ranking value is lower than the previous path when the uncertainty is 0.8. The system first verifies the missing status of the latter path to avoid misjudging the high uncertainty interval as the main compensation target.

[0037] In a preferred embodiment, generating a cross-process compensation parameter combination includes: determining a set of interventionable subsequent processes based on the dominant out-of-tolerance causal path, and calculating a joint response matrix of each subsequent process's contribution to the fin channel resistance, source-drain extension region resistance, gate interface additional resistance, and contact resistance; allocating the current contribution exceeding the target resistance budget to the set of subsequent processes, and jointly solving for surface treatment intensity, injection energy and angle sequence, annealing temperature-time trajectory, pre-contact cleaning conditions, and contact formation conditions within the device executable range, the formation state of the preceding process, and the thermal accumulation boundary of each subsequent process; eliminating candidate combinations that cause any non-target resistance contribution to exceed the corresponding budget, and forming a set of cross-process compensation parameter combinations sorted by remaining compensation capability.

[0038] The joint response matrix is ​​jointly established by the local disturbance records in the historical stable batches and the executable process range of the current batch. The rows of the matrix correspond to the four types of resistance contributions, and the columns correspond to the process control quantities that can still be adjusted. The matrix elements represent the direction and magnitude of the incremental resistance contribution when a control quantity is changed near the current intermediate state. If two control quantities are sequentially dependent, the execution result of the former control quantity is written into the response condition of the latter control quantity, and the matrix elements are conditionally updated. For example, after the surface treatment has changed the sidewall damage state, the response of the subsequent annealing to the additional resistance contribution of the gate interface no longer uses the standard batch coefficient, but instead calls the conditional response that matches the updated sidewall damage state.

[0039] Reliability constraints and thermal budget constraints are both converted into boundary conditions in the feasible set of compensation vectors. Threshold voltage and leakage current constraints are determined by the acceptable state domain from the corresponding intermediate state in the historical stable batch to the final electrical result. Gate dielectric reliability constraints are determined by the reachability relationship between sidewall damage state, interface state and subsequent thermal processes. Junction thermal budget is calculated together with the thermal processes that the current wafer has experienced and the thermal accumulation that may be introduced by the remaining processes. Whenever the candidate compensation vector changes the annealing or dielectric formation related control quantity, the remaining thermal budget and doping diffusion state are updated synchronously. If the candidate vector needs to rely on the thermal budget margin that no longer exists, or causes the current state to leave the acceptable state domain, it is deleted before entering the final value comparison.

[0040] ; Where u represents the compensation vector composed of changes in the remaining process control quantities. Let A represent the feasible set formed by the device's executable range, preceding states, threshold voltage constraints, leakage current constraints, gate dielectric reliability constraints, and junction thermal budget constraints. Let A represent the joint response matrix, r represent the deviation vector of the current four types of resistor contributions relative to the budget, and W represent the constraint weight matrix of the deviation of each resistor contribution. Let represent the continuity constraint coefficient, and D represent the difference matrix of the changes in control quantities between adjacent processes. This represents the transpose, for example, the current deviation vector is... At that time, candidate compensation vector Only after substituting A can all four components be kept within the budget and satisfy the following conditions. The time is retained, and the difference term is used to exclude control trajectories with excessively large abrupt changes between adjacent processes.

[0041] The comparison between the standard process path and the compensated process path starts from the current intermediate state. The standard process path calls the baseline subsequent formula of the current product and propagates along the causal contribution chain to the final value of the resistance contribution. The compensated process path calls the candidate compensation vector one by one and propagates using the same state nodes, the same historical condition distribution, and the same constraint boundaries. The comparison results do not directly replace the final values ​​of different batches, but perform counterfactual calculations on the same current state. If the compensated path reduces the dominant resistance contribution but causes any other resistance contribution to exceed the budget, or causes the threshold voltage, leakage current, gate dielectric reliability, and junction thermal budget constraints to lose their remaining margin, the corresponding compensated path is deleted. The retained paths are sorted according to the unconsumed compensation capacity and the prediction interval width.

[0042] The compensation solution adopts a combination of candidate generation and constraint pruning. First, control quantities without identifiable responses to the path are screened out in the joint response matrix based on the dominant out-of-tolerance causal path. Then, sparse candidate points are generated along the executable interval of the remaining control quantities. The matrix response is used to predict the changes in the contribution of the candidate points to the four types of resistors. After retaining the candidate points that satisfy all boundary conditions, local continuous solution is performed between adjacent candidate points. The obtained continuous solution is mapped to a discrete control sequence according to the executable state of the equipment. Then, causal propagation and constraint verification are performed again with the discrete sequence. When the prediction results of the continuous solution and the discrete sequence are inconsistent, the result of the discrete sequence shall prevail to avoid the mathematical optimum from exceeding the actual process state resolution capability.

[0043] In a preferred embodiment, determining direct and indirect connections includes: selecting matching sample pairs from historical batches that have the same layout density, initial fin structure size, and material batches but different target process variables; for each matching sample pair, calculating the difference sequence of each state node and each resistance contribution before and after the change in process variables; establishing a candidate direct connection when the change in target process variables is transmitted to the resistance contribution only through a single state node, and establishing a candidate indirect connection when the change in target process variables is transmitted sequentially through two or more state nodes; performing path blocking verification using batches that did not participate in connection establishment, and comparing the difference transmission results before and after blocking the specified state node; retaining connections that pass path blocking verification and have the same direction in different device groups, and recording the device group-specific bias as an additional condition for connection.

[0044] The formation of matching sample pairs adopts a layer-by-layer shrinkage method. First, the layout density area and the initial size range of the fin structure are fixed. Then, the material batch and the state of the preceding key process are fixed. Subsequently, two manufacturing trajectories with identifiable differences in the target process variable and limited differences in other process variables are selected. The difference sequence is obtained by subtracting the previous trajectory from the subsequent trajectory and is arranged into a state change chain according to the process sequence. If only the fin geometry changes first after the target process variable changes and the channel resistance contribution changes subsequently, a candidate path is established from the target process variable through the fin geometry to the channel resistance contribution. If the sidewall damage state and the gate interface state change sequentially, a candidate indirect path containing two intermediate state nodes is established.

[0045] The path interruption verification uses batches that did not participate in chain building, restricts the specified intermediate states to the common range of the matching samples, and then compares whether the changes in the target process variables can still be transmitted to the corresponding resistance contribution. If the difference between the target etching variable and the channel resistance contribution basically disappears after restricting the fin geometry, the path transmitted through the fin geometry is retained and the parallel path without intermediate states is deleted. If the difference still maintains its original direction and main amplitude after restricting a certain state, the state is determined not to be a necessary transmission node. The path structure is shared between equipment groups only when the connection direction is consistent. The difference in connection amplitude is saved as an additional condition of the equipment to avoid mistaking the offset caused by the specific chamber state as a general manufacturing mechanism.

[0046] In a preferred embodiment, limiting the measurement of missing state nodes to the feasible region includes: extracting adjacent preceding state nodes, subsequent observable state nodes, and related process variables for each missing state node; establishing conservation constraints, monotonic constraints, and process reachability constraints between adjacent nodes based on historical stable batches; converting current equipment maintenance records, cumulative chamber operation volume, and material batch offset into constraint boundary correction values; performing interval shrinking on state values ​​that simultaneously satisfy conservation constraints, monotonic constraints, process reachability constraints, and corrected boundaries; and updating the value range of missing state nodes in reverse with the newly added characterization data when subsequent processes add characterization data, and simultaneously correcting the causal path weights connected to the missing state nodes.

[0047] ; in, Let m represent the feasible region of the m-th missing state node. Indicates the state value to be estimated. This represents a linear constraint formed by material conservation, dimension transfer, or defect transformation relationships. and This indicates the lower and upper bounds after correction based on historical stable batches and equipment offsets. Indicates the preceding state Subsequent observable states and related process variables The set of reachable steps is jointly defined. For example, if the initial feasible interval is [0.18, 0.24], after adding a subsequent representation and excluding values ​​below 0.20 and above 0.22 together with the preceding state, The range shrinks to [0.20, 0.22], and the contribution range of the paths connected to the node also narrows synchronously.

[0048] Conservation constraints are used to limit the same physical quantity from undergoing unprovoked jumps between adjacent processes. Monotonic constraints are used to limit certain states to be maintained or to change along a defined direction under a known process direction. Process reachability constraints are used to exclude state values ​​that the equipment cannot form in the current state and within the remaining process range. Equipment maintenance records and chamber cumulative operation are used to correct for defect residues, processing rates, or state transition boundaries. Material batch offsets are used to correct the response range of the same process variables to doping activation and interface states. Reverse updates are only propagated along verified directed connections and do not change preceding state values ​​that are earlier than the missing nodes and have direct measurement support.

[0049] The subsequent characterization of the reverse update of the missing state adopts path consistency screening. The control system backtracks from each subsequent observable state along the incoming edge to the missing node, calculates the state combination that can generate the current subsequent observation under different candidate values, retains only the combination that simultaneously satisfies the preceding observation, process variable record and equipment additional conditions, and corrects the missing state interval with the weight of the combination appearing in the matching historical trajectory. If the feasible intervals given by multiple subsequent observations for the missing state do not intersect, a single estimate is not forced to be generated. Instead, the measurement reliability and path applicable interval are checked, and the path that does not match the current equipment state is temporarily removed and recalculated. If there is still no intersection, the corresponding node is marked as a state to be retested and the subsequent compensation range is limited.

[0050] In a preferred embodiment, the contribution exceeding the target resistance budget is allocated to the set of subsequent processes, including: establishing a process compensation capacity vector according to the compensable direction, compensable magnitude, and coupling degree of each subsequent process to non-target resistance contributions in the joint response matrix; deducting resistance contributions that cannot be eliminated by the remaining processes based on the irreversible difference between the state formed by the preceding process and the target state; prioritizing the allocation of the compensable remaining contribution to processes that have a unidirectional inhibitory relationship with the dominant excess causal path and have limited influence on other resistance contributions, and then transferring the unallocated portion to two or more processes with complementary response directions; updating the process compensation capacity vector after each allocation until the remaining contribution is fully allocated or all remaining processes reach their corresponding executable boundaries.

[0051] Each component of the process compensation capacity vector is calculated by the executable control range, the directional consistency interval in the joint response matrix, and the constraint margin. The irreversible difference between the state formed by the preceding process and the target state is determined by comparing the current state reachable set with the target state interval. If the target state has fallen outside the reachable set of the remaining processes, the corresponding difference is converted into an uneliminable resistance contribution and deducted from the amount to be allocated. The unidirectional inhibition relationship means that when a subsequent process changes within the allowable range, it continuously reduces the dominant resistance contribution without causing other resistance contributions to exceed the budget. The complementary response relationship means that the two subsequent processes reduce the dominant contribution in the same direction but change the non-target contribution in opposite directions. By combining the execution, the reverse changes cancel each other out.

[0052] In this embodiment, each allocation uses the updated state as the starting point for the next calculation. After a certain process obtains the compensation amount, the control system first predicts the changes in its contribution to the four types of resistors and the constraint margin based on the joint response matrix, then reduces the remaining compensation capacity of the corresponding process, and transmits the predicted state to the condition distribution of subsequent processes. If a single process cannot accommodate all the allocation amounts, the allocation amount of the process within the safety boundary is retained, and the margin is transferred to the complementary process pair. If all remaining processes reach the executable boundary and there are still unallocated amounts, the unallocated amounts are not forcibly compensated by expanding the equipment range, but are retained and used as the basis for determining whether to continue processing, alternative paths, or batch isolation in subsequent path selection.

[0053] In a preferred embodiment, transferring the unallocated portion to two or more processes with complementary response directions includes: selecting process pairs from the joint response matrix that show a decrease in contribution to the dominant resistance in the same direction and an inverse change in contribution to at least one non-target resistance; generating a joint adjustment trajectory along the intersection region of the response vectors of the process pairs, and using the actual completion state of the previous process as the boundary condition of the adjustment range of the next process; discretizing the joint adjustment trajectory according to the order of the processes to form multiple executable parameter sequences; calculating the interval result and reliability constraint margin of each resistance contribution for each executable parameter sequence; deleting parameter sequences whose interval result crosses the resistance budget boundary or whose reliability constraint margin is negative, and writing the retained sequences into the compensation process path.

[0054] The joint regulation trajectory is generated in the region where the response vectors intersect, following the equal decreasing direction of the dominant resistance contribution. Each point in the trajectory corresponds to a combination of control quantities for two or more subsequent processes. During discretization, the boundary is the change in control state that the equipment can stably execute. Continuous mathematical solutions are not directly sent to the manufacturing equipment. After the previous process is completed, the actual intermediate representation replaces the predicted intermediate state, and the allowable range of the next process is recalculated. If the actual state falls between adjacent discrete points of the original trajectory, the candidate sequence with the narrower prediction interval is selected from the two candidate sequences that satisfy the constraints. If the actual state exceeds the coverage of the original trajectory, the subsequent alternative sequence is called instead of extrapolating along the original trajectory.

[0055] In a preferred embodiment, recording the device group-specific bias as a connection additional condition includes: selecting cross-device batches with the same fin structure layout, material batch, and target formulation under the same process step; calculating the center offset and propagation slope of the differential sequence of the corresponding state nodes of each device group; decomposing the center offset into a stable bias and a drift component that changes with the cumulative operating amount of the chamber; writing the stable bias, drift component, and their applicable process range for the associated device group in the on-resistance causal contribution chain; when the reference wafer result of the current device exceeds the applicable process range, pausing the invocation of the original device additional condition, re-estimating the center offset and propagation slope using the intermediate characterization data of the most recent consecutive batches, and updating the condition distribution of the corresponding connection with the re-estimation result.

[0056] ; in, This indicates the cumulative operating volume of the e-th equipment group. The state bias below, This indicates the stable bias of the equipment group. This represents the drift component corresponding to a unit of cumulative operation, for example... Take 0.03, Take 0.002, When taking 5, If the value is set to 0.04, the condition distribution center of the corresponding state node is corrected by 0.04 in the same direction. If the baseline wafer characterization shows that the actual bias no longer falls within the applicable range formed by the function, then the function is discontinued. and The original value is then re-estimated using the most recent consecutive batches to prevent device drift from being incorrectly written into the general causal connection.

[0057] The propagation slope is used to describe the magnitude change of the device bias when it is passed to the resistance contribution through the intermediate state. Cross-device batches are only used to estimate the center offset and propagation slope when the layout, materials and target formulation are consistent. The selection of the most recent consecutive batches keeps the process conditions continuous and excludes direct mixing before and after equipment maintenance. The updated equipment additional conditions only apply to the corresponding equipment group and the applicable process range, and do not change the path direction that has been verified in other equipment groups. If the connection directions of multiple equipment groups are opposite, the corresponding connection will not enter the shared causal path set, but will be retained separately in the equipment group and wait for subsequent path occlusion verification.

[0058] In a preferred embodiment, the reserved sequence is written into the compensation process path, including: establishing a path node for each reserved sequence, consisting of process parameters, expected intermediate state range, allowable deviation range, and subsequent alternative sequences; after executing each process, comparing the actual intermediate characterization result with the expected intermediate state range of the corresponding path node; when the actual result is within the allowable deviation range, executing the next process according to the original reserved sequence; when the actual result exceeds the allowable deviation range, selecting a new continuous process sequence from the subsequent alternative sequences based on the consumed heat budget, the remaining equipment executable range, and the uncompleted resistance contribution budget; after all processes are completed, the final on-chip electrical data is back-allocated to each process parameter and intermediate state according to the path node, and the expected intermediate state range and allowable deviation range of subsequent batches are updated.

[0059] The process parameters in the path nodes store the control settings that the equipment can execute and their applicable prerequisite states. The expected intermediate state range is calculated by the joint response matrix and the current condition distribution. The allowable deviation range is limited by the compensability of the next process and the reliability constraint margin. Subsequent alternative sequences are pre-formed by other reserved sequences under the same current state. Therefore, when the actual state deviates, it is not necessary to search from all process combinations again. When screening new continuous process sequences, sequences that cannot be supported by the consumed heat budget are deleted first, and sequences that need to exceed the execution range of the remaining equipment are deleted. Then, the coverage and range width of each sequence to the unfinished resistance contribution budget are compared.

[0060] The final on-chip electrical data backtracking allocation is based on the actual process parameters, actual intermediate states, and causal path weights recorded at the path nodes. The residuals between the final value of the on-resistance and the final values ​​of the four types of predicted contributions are back-allocated along the directed connections. However, the back-allocation is only used to correct the connection coefficients, conditional distribution, and allowable deviation range, and is not used to change the manufacturing state records that have already occurred. If the residuals are concentrated on the path corresponding to the additional conditions of a certain equipment, the equipment bias and propagation slope are updated first. If the residuals are consistent along the same path in multiple equipment groups and material batches, the shared path coefficients are updated. If the residuals do not have a stable direction, the prediction interval of the corresponding contribution is expanded without forcibly changing the path direction.

[0061] The rollback update sets batch isolation and direction preservation conditions. The residuals formed by a single batch are only used to update the condition distribution center and prediction interval of the current equipment group, without directly changing the direction of the shared path. The connection coefficients are only re-estimated when the same path has residuals in the same direction in multiple consecutive batches, different wafer locations, and comparable material conditions. After re-estimation, the path occlusion verification is performed using the manufacturing trajectory that was not involved in the update. If the verification fails, the original connection is restored and the uncertainty is increased. If the verification passes, the new coefficients are written to the next batch's callable version, while the old version and its applicable batch range are retained, so that the manufacturing record can reproduce the causal contribution chain and compensation process path actually used at that time. When the updated version is written, the batch range, equipment status range, material conditions, and layout conditions involved in the estimation are saved at the same time. The calling end only loads the corresponding version when the current manufacturing trajectory meets all applicable conditions. If the conditions are not met, it rolls back to the verified shared path version and retains the reason for the version rollback and the calling record.

[0062] In the continuous production application of this embodiment, after a new wafer enters the fin structure etching, an associated index is established and an initial fin geometry and sidewall damage state are generated. After surface treatment, the defect state is updated and it is determined whether a dominant channel resistance or gate interface additional resistance path is formed. During the source / drain injection and annealing stages, the extended region resistance budget is allocated according to the remaining compensation capacity. During the gate dielectric formation and contact formation stages, the compensation range is limited according to the consumed thermal budget and the current reliability constraint margin. After each critical process is completed, the predicted state is replaced with the actual intermediate characterization and the standard process path and compensation process path are recalculated. After the final electrical test is completed, the causal contribution chain is backtracked and corrected so that the next batch can call the updated path coefficients, equipment additional conditions and state intervals under the same equipment, materials and layout conditions. This forms a closed-loop manufacturing process of data acquisition, state mapping, causal identification, interval propagation, compensation generation, path execution and result correction.

Claims

1. A method for manufacturing a finned MOSFET with low on-resistance, characterized in that, include: Collect process data, intermediate characterization data, and on-chip electrical data for each step of fin structure etching, surface treatment, source / drain injection, annealing, gate dielectric formation, and contact formation, and establish an associated index according to wafer region, device location, and process sequence; Based on the aforementioned correlation index, a causal contribution chain for on-resistance is constructed, decomposing the on-resistance into contributions from the fin channel resistance, source / drain extension region resistance, gate interface additional resistance, and contact resistance. After the key process is completed, update the prediction range of each resistance contribution and determine the dominant out-of-tolerance causal path; Based on the dominant cause-and-effect path of the deviation and the adjustable range of the remaining processes, a combination of cross-process compensation parameters is generated; Under the constraints of threshold voltage, leakage current, gate dielectric reliability and junction thermal budget, the final values ​​of each resistance contribution of the standard process path and the compensated process path are calculated with the current intermediate state as a common starting point, and the control parameters of the subsequent process are selected and executed. The on-resistance causal contribution chain is corrected based on the final electrical test results.

2. The method for manufacturing a low on-resistance finned MOSFET according to claim 1, characterized in that, Constructing the on-resistance causal contribution chain includes: classifying fin width, fin height, sidewall tilt angle and sidewall roughness into the fin geometry, classifying etching damage density and surface defect density into the sidewall damage state, classifying doping concentration distribution and activation ratio into the doping activation state, classifying interface state density and equivalent dielectric state into the gate interface state, and classifying pre-contact surface residue and contact resistance into the contact state. Establish directed connections according to the sequential relationship of each state in the process sequence; Based on the corresponding records of process variable disturbances and state changes in historical batches, the direct connections from process variables to the resistance contribution and the indirect connections transmitted through intermediate states are determined respectively, and mutual exclusion constraints are set for connections sharing intermediate states to form a set of causal paths traceable to specific manufacturing processes.

3. The method for manufacturing a low on-resistance finned MOSFET according to claim 1, characterized in that, Update the prediction range of each resistance contribution, including: for each completed key process of the current wafer, map the corresponding intermediate characterization data and equipment process data to the state node in the on-resistance causal contribution chain; Call up historical samples that match the current equipment chamber status, material batch, and fin structure layout density to calculate the conditional distribution of each state node; The measurement of missing state nodes is limited to the feasible region determined by the preceding state, the current process record, and the subsequent observable state. By propagating the conditional distribution step by step according to the connection direction of the causal path, the interval estimate of the contribution of each resistance is obtained. Based on the excess of the upper bound of the interval relative to the target resistance budget and the local sensitivity of each path, the candidate causal paths are sorted and the dominant out-of-range causal path is determined.

4. The method for manufacturing a low on-resistance finned MOSFET according to claim 1, characterized in that, Generating the cross-process compensation parameter combination includes: determining the set of interventionable subsequent processes based on the dominant out-of-tolerance causal path, and calculating the joint response matrix of each subsequent process on the contribution of the fin channel resistance, the source-drain extension region resistance, the gate interface additional resistance, and the contact resistance. The contribution amount that exceeds the target resistance budget is allocated to the set of subsequent processes. Within the equipment executable range of each subsequent process, the formation state of the preceding process, and the thermal accumulation boundary of the subsequent process, the surface treatment intensity, injection energy and angle sequence, annealing temperature and time trajectory, pre-contact cleaning conditions, and contact formation conditions are jointly solved. Candidate combinations that cause any non-target resistance contribution to exceed the corresponding budget are eliminated, forming a set of cross-process compensation parameter combinations sorted by remaining compensation capacity.

5. The method for manufacturing a low on-resistance finned MOSFET according to claim 2, characterized in that, Determining the direct connection and the indirect connection includes: selecting matching sample pairs from historical batches that have the same layout density, initial fin structure size and material batch but different target process variables; For each matched sample pair, calculate the difference sequence of each state node and each resistance contribution before and after the change of process variables; A candidate direct connection is established when the change of the target process variable is transmitted to the resistance contribution only through a single state node; a candidate indirect connection is established when the change of the target process variable is transmitted sequentially through two or more state nodes. Utilize batch execution path blocking verification that did not participate in connection establishment, and compare the differential transmission results before and after blocking the specified state node; Retain connections that have been verified through path blocking and are oriented in the same direction across different device groups, and record the device group-specific bias as an additional condition for the connection.

6. The method for manufacturing a low on-resistance finned MOSFET according to claim 3, characterized in that, Limiting the missing state nodes to the feasible region includes: for the missing state node, extracting its adjacent preceding state nodes, subsequent observable state nodes and related process variables; Based on historical stable batches, establish conservation constraints, monotonic constraints, and process reachability constraints between adjacent nodes; Convert the current equipment maintenance records, cumulative chamber operation volume, and material batch offset into constraint boundary correction values; For the state values ​​that simultaneously satisfy conservation constraints, monotonic constraints, process reachability constraints, and modified boundary conditions, interval shrinkage is performed; When new characterization data is added in subsequent processes, the value range of the missing state node is updated in reverse with the new characterization data, and the causal path weights connected to the missing state node are corrected simultaneously.

7. The method for manufacturing a low on-resistance finned MOSFET according to claim 4, characterized in that, The contribution amount that exceeds the target resistance budget is allocated to the set of subsequent processes, including: establishing a process compensation capacity vector according to the compensable direction, compensable magnitude and coupling degree of each subsequent process to the non-target resistance contribution in the joint response matrix; Based on the irreversible difference between the state already formed by the preceding process and the target state, deduct the resistance contribution that cannot be eliminated by the remaining processes; The remaining compensable contribution is preferentially allocated to the processes that have a unidirectional inhibitory relationship with the dominant out-of-range causal path and have limited influence on the contribution of other resistances, and then the unallocated portion is transferred to two or more processes with complementary response directions. The compensation capacity vector for each process is updated after each allocation until the remaining contribution is fully allocated or all remaining processes reach their corresponding executable boundaries.

8. The method for manufacturing a low on-resistance finned MOSFET according to claim 7, characterized in that, Transferring the unallocated portion to two or more processes having the complementary response directions includes: selecting process pairs from the joint response matrix that show a unidirectional decrease in the contribution to the dominant deviation and an inverse change in the contribution to at least one non-target resistance. A joint adjustment trajectory is generated along the intersection region of the process response vectors, and the actual completion state of the previous process is used as the boundary condition of the adjustment range of the next process. The joint adjustment trajectory is discretized according to the sequence of processes to form multiple executable parameter sequences. For each executable parameter sequence, calculate the interval results of each resistance contribution and the reliability constraint margin. Delete parameter sequences whose interval results cross the resistance budget boundary or whose reliability constraint margin is negative, and write the retained sequences into the compensation process path.

9. A method for manufacturing a low on-resistance finned MOSFET according to claim 5, characterized in that, The unique bias of the equipment group is recorded as an additional connection condition, including: selecting cross-equipment batches with the same fin structure layout, material batch and target formula under the same process step, and calculating the center offset and propagation slope of the differential sequence of the corresponding state node of each equipment group; The center offset is decomposed into a stable offset and a drift component that varies with the cumulative operating amount of the chamber; The stable bias, the drift component, and their applicable process range are written into the associated device group in the on-resistance causal contribution chain. When the reference wafer result of the current equipment exceeds the applicable process range, the original equipment additional conditions are paused, the center offset and the propagation slope are re-estimated using the intermediate characterization data of the most recent consecutive batches, and the condition distribution of the corresponding connection is updated with the re-estimated results.

10. A method for manufacturing a low on-resistance finned MOSFET according to claim 8, characterized in that, Writing the retained sequence into the compensation process path includes: establishing a process node for each retained sequence, consisting of the process parameters, expected intermediate state range, allowable deviation range, and subsequent alternative sequences; After completing a process, the actual intermediate representation results are compared with the expected intermediate state range of the corresponding path node. When the actual result is within the allowable deviation range, proceed to the next step according to the original retained sequence; When the actual results exceed the allowable deviation range, a new continuous process sequence is selected from the subsequent alternative sequences based on the original heat consumption budget, the remaining equipment's executable range, and the unfinished resistance contribution budget. After all processes are completed, the final on-chip electrical data is back-allocated to the process parameters and intermediate states according to the path nodes, and the expected intermediate state range and allowable deviation range of subsequent batches are updated.

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