A trench bottom shielding structure silicon carbide MOSFET device preparation control method

Abstract

This invention discloses a method for fabricating and controlling a silicon carbide MOSFET device with a trench bottom shielding structure, relating to the field of MOSFET device fabrication technology. The key technical steps include: dividing the stepped P-type shielding region within the silicon carbide wafer trench array into partitioned fabrication coordinates; separating the ion implantation orientation, target doping concentration, and lateral width process parameters corresponding to the upper and lower sections of the shielding region; establishing independent process tolerance thresholds for the upper and lower sections; acquiring multi-angle ion implantation process measurement data from historical wafer batches on the same production line; and combining this with implantation tilt angle and implantation dose. The effect is to quantitatively characterize the linkage interference of ion implantation parameter fluctuations on the morphology of the two shielding regions, allowing for early quantification and prediction of fluctuations in the upper section's electric field buffering performance and the lower section's high electric field absorption capacity, proactively identifying potential electric field imbalances, and effectively reducing wafer scrap losses caused by process anomalies.

Description

Technical Field

[0001] This invention relates to the field of MOSFET device fabrication technology, and more specifically, to a method for controlling the fabrication of a trench-bottom shielded silicon carbide MOSFET device. Background Technology

[0002] Silicon carbide MOSFETs, leveraging the material advantages of silicon carbide, such as its wide bandgap, high critical breakdown electric field, and excellent thermal conductivity, have gradually achieved commercial application in high-power, high-voltage scenarios, including new energy vehicle inverters, high-voltage energy storage converters, and industrial high-voltage power supplies. Trench-type silicon carbide MOSFETs have become the mainstream structure due to their lower on-resistance and higher device package surface utilization. However, electric field spikes are easily generated at the corners of the trench sidewalls and the bottom of the trench. When the local electric field intensity reaches the silicon carbide breakdown threshold, it can induce failures such as gate oxide layer damage and premature avalanche breakdown. Therefore, the industry generally adds a P-type shielding structure at the bottom of the trench to distribute the concentrated electric field.

[0003] However, most existing solutions use a homogeneous, integrated P-type shielding region for ion implantation. The entire shielding region uses a uniform implantation tilt angle and doping dose, which makes it difficult to match the different performance requirements of smoothing the sudden electric field at the upper corner of the trench and bearing the high-intensity pressure electric field at the bottom of the trench. A higher doping concentration in the upper section will increase the gate leakage current level, while insufficient doping in the lower section will make it difficult to suppress the peak electric field at the bottom. The long-term reliability of the device under high-voltage conditions has obvious shortcomings. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a method for fabricating and controlling a trench bottom shielded silicon carbide MOSFET device.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for fabricating and controlling a silicon carbide MOSFET device with a trench bottom shielding structure, the method comprising the following specific steps:

[0007] The fabrication coordinates of the stepped P-type shielding region within the silicon carbide wafer trench array are divided, and the process parameters of ion implantation orientation, target doping concentration and lateral width corresponding to the upper and lower sections of the shielding region are separated. Independent process tolerance thresholds for the upper and lower sections are established.

[0008] Obtain measured data of multi-angle ion implantation process from historical wafer batches on the same production line, and calculate the coupling influence coefficient of the morphology of the low-doped region in the upper width and the high-doped region in the lower width by combining the implantation tilt angle and implantation dose.

[0009] Based on the coupling influence coefficient, the fluctuation range of the electric field buffering performance of the upper section and the deviation of the high electric field absorption capacity of the lower section of the shielding area at the bottom of the trench of a single device are determined, and the overall electric field tolerance estimate of the shielding structure is obtained.

[0010] By comparing the electric field tolerance estimate with the process allowable deviation threshold, the risk level of electric field distribution imbalance in the shielded area is determined, and the tilt angle correction amount and partitioned implantation dose compensation parameters for multi-angle ion implantation are obtained.

[0011] Based on the tilt angle correction and partition injection dose compensation parameters, the deposition thickness and doping level of the N-type buffer layer at the bottom of the shielding area are monitored to obtain the measured electric field distribution results. The masking etching window size of subsequent wafer batches is iteratively adjusted based on the measured electric field distribution results.

[0012] Preferably, the fabrication coordinates of the stepped P-type shielding region within the silicon carbide wafer trench array are divided, and the ion implantation orientation, target doping concentration, and lateral width process parameters corresponding to the upper and lower sections of the shielding region are separated. Independent process tolerance thresholds are established for the upper and lower sections. The specific steps are as follows:

[0013] Based on the device withstand voltage simulation results, determine the longitudinal boundary coordinates of the upper and lower shielding areas in the trench depth direction, limit the doping concentration range and upper limit of the lateral width of the upper shielding area, and limit the lower limit of the doping concentration and lower limit of the lateral width of the lower shielding area.

[0014] Based on the wafer edge region and wafer center region, calculate the dimensional tolerances and doping concentration tolerances of the upper and lower shielding regions to generate differentiated process tolerance thresholds for each region.

[0015] Preferably, measured data of multi-angle ion implantation processes from historical wafer batches on the same production line are obtained. Combined with the implantation tilt angle and implantation dose, the coupling influence coefficient between the morphology of the low-doped region in the upper width and the high-doped region in the lower width is calculated. The specific steps are as follows:

[0016] Obtain sample wafers with intact self-aligned masking structures and no additional photolithography stacking processes from historical batches, and divide the upper and lower shielding areas into corresponding injection tilt angles, injection doses, measured doping concentrations, and measured lateral widths.

[0017] The coupling coefficients of the upper shielding region's tilt angle and width, and the dose and doping concentration are calculated to obtain the upper section's partial coupling coefficients. The coupling coefficients of the lower shielding region's tilt angle and width, and the dose and doping concentration are calculated to obtain the partial coupling coefficients.

[0018] The partition coupling influence coefficient is obtained by integrating the upper segment coupling coefficient and the lower segment coupling coefficient.

[0019] Preferably, the fluctuation range of the electric field buffering performance of the upper section and the deviation of the high electric field absorption capacity of the lower section of the shielding area at the bottom of the trench of a single device are determined according to the coupling influence coefficient, so as to obtain the estimated value of the electric field tolerance of the overall shielding structure. The specific steps are as follows:

[0020] The fluctuation range of the upper section's sudden electric field buffering performance is obtained by calculating the actual doping and the offset of the upper section's width relative to the preset value based on the upper section's sub-coupling coefficient.

[0021] The deviation of the high electric field absorption capacity at the bottom of the trench is obtained by calculating the actual doping and the offset of the width of the lower section relative to the preset value based on the lower section's sub-coupling coefficient.

[0022] Based on the weighting of the electric field load at the bottom of the trench, the fluctuation range of the upper section's abrupt electric field buffering performance and the deviation of the lower section's high electric field absorption capacity at the bottom of the trench are combined for calculation, and the overall electric field tolerance estimate of the shielding structure is output.

[0023] Preferably, by comparing the predicted electric field tolerance value with the process tolerance threshold, the risk level of electric field distribution imbalance in the shielded area is determined, and the tilt angle correction and partitioned implantation dose compensation parameters for multi-angle ion implantation are obtained. The specific steps are as follows:

[0024] By comparing the estimated electric field tolerance with the process allowable deviation threshold, the risk level of electric field distribution imbalance in the shielded area is divided into the estimated difference range corresponding to low electric field imbalance risk, medium electric field imbalance risk, and high electric field imbalance risk.

[0025] The risk level is determined by comparing the difference between the estimated value and the benchmark withstand voltage threshold and assigning the range to the risk level.

[0026] Among them, for low-risk cases, only the dose compensation value of the lower segment ion implantation is slightly adjusted; for medium-risk cases, the implantation dose of the upper and lower segments is corrected simultaneously; and for high-risk cases, the incident tilt angle of multi-angle ion implantation and the two-segment partition implantation dose are adjusted simultaneously.

[0027] The tilt correction amount and zonal injection dose compensation parameters for multi-angle ion implantation are determined based on the risk level.

[0028] Preferably, based on the tilt angle correction and partition injection dose compensation parameters, the deposition thickness and doping level of the N-type buffer layer at the bottom of the shielding area are monitored to obtain the measured electric field distribution results. The masking etching window size for subsequent wafer batches is then iteratively adjusted based on the measured electric field distribution results. The specific steps are as follows:

[0029] The stepped P-type shielding zone for self-masking is determined based on the multi-angle ion implantation orientation.

[0030] Measured parameters of the film thickness and doping concentration of the N-type buffer layer in the stepped P-type shielding region were collected.

[0031] Electric field simulation and retesting were performed on the cross-section of the finished trench, integrating the probability of electric field stress concentration in the upper section with the magnitude of the peak electric field at the bottom of the lower section.

[0032] When the electric field stress concentration probability in the upper section and the peak electric field value at the bottom of the lower section exceed the preset range in the measured electric field indicators, the width of the self-aligned masking trench etching window is reduced or widened to finely adjust the masking etching window size of subsequent wafer batches.

[0033] Compared with existing technologies, this invention has the following advantages: By establishing segmented, independent, and regionally differentiated process tolerance thresholds based on the process fluctuation differences in the wafer's central and edge regions, the upper segment strictly constrains the doping concentration range and width upper limit to suppress gate leakage, while the lower segment limits doping and width to ensure the bottom high-voltage carrying capacity. This reduces the probability of gate oxide breakdown due to electric field spikes at trench corners and premature avalanche breakdown at the bottom of the trench, thus enhancing the long-term operational reliability of the device under high-voltage conditions. By retrieving historical wafer measurement data from the same production line, the coupling coefficients of tilt angle and width, dosage and doping are calculated separately for the upper and lower segments, and integrated to obtain the partitioned coupling influence coefficient. This can quantitatively characterize the linkage interference of ion implantation parameter fluctuations on the morphology of the two shielded areas, and can quantitatively predict the fluctuation deviations of the upper segment's electric field buffering performance and the lower segment's high electric field absorption capacity in advance, identifying potential electric field imbalance hazards ahead of time and effectively reducing wafer scrap losses caused by process anomalies. Attached Figure Description

[0034] Figure 1 This is a schematic flowchart illustrating a method for fabricating and controlling a trench-bottom shielded silicon carbide MOSFET device according to an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram illustrating the process of obtaining the partitioned coupling influence coefficient using a method for fabricating and controlling a trench bottom shielded silicon carbide MOSFET device according to an embodiment of the present invention. Detailed Implementation

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0038] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0039] Reference Figures 1-2 As shown.

[0040] The embodiments further illustrate the fabrication and control method of a trench bottom shielded silicon carbide MOSFET device proposed in this invention.

[0041] A method for fabricating and controlling a silicon carbide MOSFET device with a trench bottom shielding structure, the method comprising the following specific steps:

[0042] The fabrication coordinates of the stepped P-type shielding region within the silicon carbide wafer trench array are divided, and the process parameters of ion implantation orientation, target doping concentration and lateral width corresponding to the upper and lower sections of the shielding region are separated. Independent process tolerance thresholds for the upper and lower sections are established.

[0043] Obtain measured data of multi-angle ion implantation process from historical wafer batches on the same production line, and calculate the coupling influence coefficient of the morphology of the low-doped region in the upper width and the high-doped region in the lower width by combining the implantation tilt angle and implantation dose.

[0044] Based on the coupling influence coefficient, the fluctuation range of the electric field buffering performance of the upper section and the deviation of the high electric field absorption capacity of the lower section of the shielding area at the bottom of the trench of a single device are determined, and the overall electric field tolerance estimate of the shielding structure is obtained.

[0045] By comparing the electric field tolerance estimate with the process allowable deviation threshold, the risk level of electric field distribution imbalance in the shielded area is determined, and the tilt angle correction amount and partitioned implantation dose compensation parameters for multi-angle ion implantation are obtained.

[0046] Based on the tilt angle correction and partition injection dose compensation parameters, the deposition thickness and doping level of the N-type buffer layer at the bottom of the shielding area are monitored to obtain the measured electric field distribution results. The masking etching window size of subsequent wafer batches is iteratively adjusted based on the measured electric field distribution results.

[0047] The fabrication coordinates of the stepped P-type shielding region within the silicon carbide wafer trench array are divided, and the process parameters of ion implantation orientation, target doping concentration, and lateral width corresponding to the upper and lower sections of the shielding region are separated. Independent process tolerance thresholds for the upper and lower sections are established. The specific steps are as follows:

[0048] Based on the device withstand voltage simulation results, determine the longitudinal boundary coordinates of the upper and lower shielding areas in the trench depth direction, limit the doping concentration range and upper limit of the lateral width of the upper shielding area, and limit the lower limit of the doping concentration and lower limit of the lateral width of the lower shielding area.

[0049] Based on the wafer edge region and wafer center region, calculate the dimensional tolerances and doping concentration tolerances of the upper and lower shielding regions to generate differentiated process tolerance thresholds for each region.

[0050] Parameter calibration was conducted based on the inherent structural function of the stepped P-type shielding region of the SiC trench MOSFET. The upper shielding region, with its lower doping concentration and narrower lateral width, buffers the abrupt change in the trench's electric field. The lower shielding region, with its higher doping concentration and wider lateral width, absorbs the high-intensity electric field accumulated at the bottom of the trench. The functional requirements of these two regions are significantly different, and a uniform process control standard cannot be applied. First, the longitudinal boundary coordinates were defined based on device breakdown voltage simulation. The simulation used the critical breakdown electric field of 2.2 MV / cm for silicon carbide as a hard constraint, setting the longitudinal depth parameter A for the upper shielding region and B for the lower shielding region. The overall longitudinal depth of the shielding region was C = A + B. The values ​​of A and B were continuously iteratively adjusted until the peak electric field at the trench corner and the bottom of the trench did not exceed 2.2 MV / cm. The corresponding depth points at this point were then defined as the longitudinal boundary coordinates between the two shielding regions. After the boundary points are determined, the constraint ranges for individual parameters are defined. For the upper shielding zone that meets the electric field buffering requirements, the doping concentration must fall within the range of the lower limit to the upper limit of D, and the maximum allowable value of the lateral width, the upper limit of E, is also set. For the lower shielding zone that meets the high-voltage electric field support requirements, the minimum allowable value of the doping concentration, the lower limit of F, and the minimum allowable value of the lateral width, the lower limit of G, are defined.

[0051] After completing the single-point parameter constraints, the tolerances are calculated separately for two regions: the wafer center and the wafer edge. In the ion implantation process, the plasma distribution in the wafer center is uniform, and the ion incident flux fluctuation is relatively low. At the wafer edge, due to sheath distortion, the fluctuations in implantation tilt angle and dose are significantly larger. The finished product parameters in both regions naturally exhibit dispersion deviations. Using a normal distribution with a standard deviation of 3 times covering 99.73% of conventional process fluctuations as the calculation benchmark, the tolerance for the upper section width of the wafer center region (H1) is calculated as: H1 = standard deviation of the upper section width sample of the wafer center region × 3; the tolerance for the upper section width of the wafer edge region (H2) is calculated as: H2 = standard deviation of the upper section width sample of the wafer edge region × 3; the tolerance for the lower section width of the wafer center region (I1) is calculated as: I2 = standard deviation of the lower section width sample of the wafer center region × 3; and the tolerance for the lower section width of the wafer edge region (I2) is calculated as: I2 = standard deviation of the lower section width sample of the wafer edge region × 3. The doping tolerance calculation formula is as follows: For the upper section of the wafer center region, J1 = standard deviation of the upper section doping sample × 3; for the upper section of the wafer edge region, J2 = standard deviation of the upper section doping sample × 3; for the lower section of the wafer center region, K1 = standard deviation of the lower section doping sample × 3; for the lower section of the wafer edge region, K2 = standard deviation of the lower section doping sample × 3. Based on the tolerance-based differential threshold, the upper section center width control range = upper section reference width ± H1; the upper section edge width control range = upper section reference width ± H2; the upper section center doping control range = upper section reference doping ± J1; the upper section edge doping control range = upper section reference doping ± J2; the lower section center width control range = lower section reference width ± I1; the lower section edge width control range = lower section reference width ± I2; the lower section center doping control range = lower section reference doping ± K1; the lower section edge doping control range = lower section reference doping ± K2. Setting thresholds by region can adapt to the process fluctuation characteristics of different radial positions of the wafer, avoid the performance dispersion problem caused by the lenient control standards in the center, and prevent unnecessary wafer scrapping caused by strict edge standards. The complete set of data after calibration will serve as the judgment benchmark for subsequent process correction. It is compatible with the forming mode of multi-angle ion implantation combined with self-aligned masking. Combined with the electric field homogenization effect of the bottom N-type buffer layer, it avoids the defects of electric field distribution imbalance in the shielding area in advance.

[0052] Obtain measured data of multi-angle ion implantation processes from historical wafer batches on the same production line. Combine this with the implantation tilt angle and implantation dose to calculate the coupling influence coefficient between the morphology of the low-doped region in the upper width and the high-doped region in the lower width. The specific steps are as follows:

[0053] Obtain sample wafers with intact self-aligned masking structures and no additional photolithography stacking processes from historical batches, and divide the upper and lower shielding areas into corresponding injection tilt angles, injection doses, measured doping concentrations, and measured lateral widths.

[0054] The coupling coefficients of the upper shielding region's tilt angle and width, and the dose and doping concentration are calculated to obtain the upper section's partial coupling coefficients. The coupling coefficients of the lower shielding region's tilt angle and width, and the dose and doping concentration are calculated to obtain the partial coupling coefficients.

[0055] The partition coupling influence coefficient is obtained by integrating the upper segment coupling coefficient and the lower segment coupling coefficient.

[0056] Select compliant historical sample wafers. The strict criteria for samples are that the self-aligned mask structure is intact and undamaged, and no additional photolithography processes are added during the wafer fabrication process. Abnormal samples with mask damage or those requiring additional photolithography processing can eliminate data deviations caused by irrelevant process factors, ensuring that subsequent coefficient calculations are consistent with normal mass production conditions. After screening, the data is classified and organized according to the upper and lower sections of the shielded area. The implantation tilt angle value, implantation dose value, measured doping concentration value, and measured lateral width value corresponding to the upper shielded area are collected separately, and the four types of measured data of the same dimension for the lower shielded area are collected separately.

[0057] The coupling coefficients are calculated separately for the upper and lower segments. The upper segment's coupling coefficient A for tilt angle width is calculated as: A = (change in upper segment lateral width ÷ change in upper segment injection tilt angle). This value reflects the micrometer-level change in the upper segment's lateral width for every 1-degree tilt angle shift. The upper segment's coupling coefficient B for dose doping is calculated as: B = (change in upper segment doping concentration ÷ change in upper segment injection dose). This characterizes the increase or decrease in upper segment doping concentration caused by unit dose fluctuations. These two results are combined to form the upper segment's coupling coefficient set. The lower segment's coupling coefficient C for tilt angle width is calculated as: C = (change in lower segment lateral width ÷ change in lower segment injection tilt angle). The lower segment's coupling coefficient D for dose doping is calculated as: D = (change in lower segment doping concentration ÷ change in lower segment injection dose). These two calculations are summarized to form the lower segment's coupling coefficient set. For example, a 2-degree shift in the upper segment injection tilt angle corresponds to a 0.04-micrometer change in lateral width. Substituting this into the formula, we get A = 0.04 ÷ 2 = 0.02 micrometers per degree, which allows for a direct prediction of the morphological changes caused by tilt angle fluctuations.

[0058] Finally, coefficient integration calculations are performed to obtain the overall partition coupling influence coefficient, S, which is set as S=(A+B+C+D)÷4. The binding effect of the four types of sub-couplings is synthesized through mean value calculation, and the linkage interference intensity between the two types of morphologies—the upper low-doped region and the lower high-doped region—is uniformly quantified. The calculated partition coupling influence coefficient can be incorporated into the subsequent electric field tolerance prediction stage, quantitatively predicting the performance deviations caused by tilt angle and dose process fluctuations on the upper electric field buffering performance and the lower high-voltage carrying capacity. This adapts to the differentiated tolerance control standards of the wafer center and edge regions, providing quantifiable numerical basis for subsequent ion implantation tilt angle correction and dose parameter compensation. It also identifies potential electric field concentration hazards caused by process fluctuations in advance, maintaining the low-cost and high-precision process advantages of the self-aligned masking molding process, and completing the entire-link electric field control in conjunction with the N-type buffer layer at the bottom of the shielding area.

[0059] Based on the coupling influence coefficient, the fluctuation range of the electric field buffering performance of the upper section and the deviation of the high electric field absorption capacity of the lower section in the bottom shielding area of ​​a single device trench are determined, and the overall electric field tolerance estimate of the shielding structure is obtained. The specific steps are as follows:

[0060] The fluctuation range of the upper section's sudden electric field buffering performance is obtained by calculating the actual doping and the offset of the upper section's width relative to the preset value based on the upper section's sub-coupling coefficient.

[0061] The deviation of the high electric field absorption capacity at the bottom of the trench is obtained by calculating the actual doping and the offset of the width of the lower section relative to the preset value based on the lower section's sub-coupling coefficient.

[0062] Based on the weighting of the electric field load at the bottom of the trench, the fluctuation range of the upper section's abrupt electric field buffering performance and the deviation of the lower section's high electric field absorption capacity at the bottom of the trench are combined for calculation, and the overall electric field tolerance estimate of the shielding structure is output.

[0063] Based on the quantitative analysis of the process parameter offset by the sub-coupling coefficient, the impact on the segmented electrical performance of the stepped P-type shield is quantified, and the overall electric field tolerance estimate of the shield structure is finally output. This is matched with the structural division of labor of the upper section of the SiC trench MOSFET to buffer the sudden electric field and the lower section to bear the bottom high voltage electric field, providing quantitative data support for the subsequent electric field imbalance risk classification.

[0064] The performance calculation of the upper shielding area involves retrieving the upper tilt angle width coupling coefficient and the upper dose doping coupling coefficient, respectively, and substituting them into the calculations to solve for the offset of size and doping. The actual offset value of the upper width = upper tilt angle width coupling coefficient × current tilt angle process offset, and the actual offset value of the upper doping = upper dose doping coupling coefficient × current injection dose process offset. Based on these two types of offsets, the fluctuation range of the upper section's abrupt electric field buffering performance is calculated. For example, if the upper tilt angle width coupling coefficient is 0.02 micrometers per degree, and the actual tilt angle offsets by 1.5 degrees compared to the preset standard, the actual offset value of the upper width can be calculated as 0.02 × 1.5 = 0.03 micrometers. A positive widening of the width will slightly weaken the electric field mitigation effect at the corner, and a positive rise caused by doping will increase the risk of leakage current on the gate side. The two offsets together determine the fluctuation range of the upper section's electric field buffering capability.

[0065] To calculate the deviation of the lower shielding area, a unified basic formula is applied using the two-component coupling coefficients corresponding to the lower segment. The actual offset value of the lower segment width = the lower segment tilt angle width component coupling coefficient × the current tilt angle process offset; the actual offset value of the lower segment doping = the lower segment dose doping component coupling coefficient × the current injection dose process offset. Based on the two offset results, the deviation of the high electric field absorption capacity at the bottom of the lower trench is calculated. When the lower segment width and doping are lower than the preset standards, the effective area of ​​the high voltage electric field distributed at the bottom of the trench will shrink, the local electric field peak will increase, and the probability of device avalanche breakdown will increase accordingly. If the size and doping exceed the design range, the reverse leakage current level will increase. Both types of deviations will directly change the upper limit of the device's bottom pressure bearing capacity.

[0066] Based on the pre-simulated electric field load allocation weights at the bottom of the trench, a weighted fusion calculation is performed. The upper section electric field load allocation weight parameter M and the lower section electric field load allocation weight parameter N are set, satisfying M+N=1. The overall electric field withstand capability estimate of the shielding structure is calculated as: Upper section sudden electric field buffering performance fluctuation amplitude × M + Lower section high electric field absorption capacity deviation × N. Taking a weight of M=0.3 and a weight of N=0.7 as an example, the upper section electric field buffering performance fluctuation amplitude is negative 0.07 kV / cm, and the lower section high electric field absorption capacity deviation is negative 0.12 kV / cm. Substituting these values ​​into the formula, the overall electric field withstand capability estimate is obtained as: 0.07×0.3+0.12×0.7=0.105 kV / cm. A negative number indicates a decline in withstand capability compared to the baseline design. The estimated value can be compared with the process tolerance threshold of the different regions, quantitatively evaluate the voltage resistance loss caused by process fluctuations, adapt to different tolerance control standards of the wafer center area and edge area, support the derivation of subsequent ion implantation tilt angle correction amount and dose compensation parameters, rely on the process characteristics of self-aligned masking and form, link with the electric field homogenization effect of the bottom N-type buffer layer, and predict in advance the possibility of electric field concentration failure in the shielding area of ​​different wafer batches.

[0067] By comparing the predicted electric field tolerance with the process tolerance threshold, the risk level of electric field distribution imbalance in the shielded area is determined, and the tilt angle correction and zonal implantation dose compensation parameters for multi-angle ion implantation are obtained. The specific steps are as follows:

[0068] By comparing the estimated electric field tolerance with the process allowable deviation threshold, the risk level of electric field distribution imbalance in the shielded area is divided into the estimated difference range corresponding to low electric field imbalance risk, medium electric field imbalance risk, and high electric field imbalance risk.

[0069] The risk level is determined by comparing the difference between the estimated value and the benchmark withstand voltage threshold and assigning the range to the risk level.

[0070] Among them, for low-risk cases, only the dose compensation value of the lower segment ion implantation is slightly adjusted; for medium-risk cases, the implantation dose of the upper and lower segments is corrected simultaneously; and for high-risk cases, the incident tilt angle of multi-angle ion implantation and the two-segment partition implantation dose are adjusted simultaneously.

[0071] The tilt correction amount and zonal injection dose compensation parameters for multi-angle ion implantation are determined based on the risk level.

[0072] The valuation difference ranges corresponding to three risk categories are divided. First, the valuation difference is calculated as: Valuation Difference = Process Tolerance Threshold - Estimated Electric Field Tolerance. Based on the magnitude of the difference, three ranges are defined: a difference between 0 and the first threshold value is classified as low electric field imbalance risk; a difference between the first and second threshold values ​​is classified as medium electric field imbalance risk; and a difference greater than the second threshold value is classified as high electric field imbalance risk. For example, if the first threshold value is set to 0.08 kV per centimeter and the second threshold value to 0.15 kV per centimeter, and the calculated valuation difference is 0.05 kV per centimeter, this value falls within the 0 to 0.08 kV per centimeter range, and the device is classified as low electric field imbalance risk.

[0073] Subsequent comparisons of the estimated differences within a predetermined range determine the precise risk level of the device, with different risk levels corresponding to progressively increasing process intervention measures. Low-risk levels indicate minor voltage withstand performance losses due to process fluctuations, with the upper-stage electric field buffering capacity within acceptable fluctuation ranges. Only minor adjustments to the lower-stage ion implantation dose compensation value are needed, leveraging the higher doping capacity of the lower stage to compensate for the small voltage withstand gap. This avoids altering the upper-stage process parameters and prevents additional disturbances to the electric field smoothing effect at trench corners. Medium-risk levels indicate observable performance losses due to simultaneous morphology and doping deviations in both the upper and lower shielding regions. Simply adjusting the lower-stage parameters cannot compensate for the voltage withstand gap; simultaneous correction of the implantation dose in both the upper and lower sections is required to enhance the upper-stage electric field buffering performance and the lower-stage high-field absorption capacity, respectively, to prevent further deterioration of the electric field concentration problem. High-level risk indicates that process deviations have caused significant potential electric field imbalance. Relying solely on dose compensation cannot offset the morphological deformation caused by tilt angle offset. It is necessary to simultaneously adjust the incident tilt angle of multi-angle ion implantation, and carry out joint correction by combining the implantation doses of the upper and lower sections. This corrects the lateral width deviation of the shielding area from the source of morphological formation, and then compensates for the shortcomings in electrical performance by optimizing the doping dose.

[0074] Based on the determined risk level, the model is used to calculate the corresponding tilt angle correction and partitioned injection dose compensation parameters. The tilt angle correction is calculated as the sub-item tilt angle coupling coefficient multiplied by the estimated difference, and the partitioned dose compensation parameter is calculated as the sub-item dose coupling coefficient multiplied by the estimated difference. Different risk levels are matched with corresponding correction amplification coefficients to complete the numerical conversion. This tiered process correction approach avoids the over-correction problem caused by uniform large-scale adjustments. In low-risk scenarios, the magnitude of process changes is controlled to reduce process costs, while in high-risk scenarios, source parameter corrections are performed to avoid batch breakdown voltage failures of devices. The output parameters can be directly used for pre-process control of the wafer ion implantation process. Subsequent iterations and optimizations are performed using measured electric field data from the N-type buffer layer to continuously reduce the dispersion of the electric field performance in the shielded area of ​​different wafer batches.

[0075] Based on the tilt angle correction and partition injection dose compensation parameters, the deposition thickness and doping level of the N-type buffer layer at the bottom of the shielding area are monitored to obtain the measured electric field distribution results. The masking etching window size for subsequent wafer batches is then iteratively adjusted based on the measured electric field distribution results. The specific steps are as follows:

[0076] The stepped P-type shielding zone for self-masking is determined based on the multi-angle ion implantation orientation.

[0077] Measured parameters of the film thickness and doping concentration of the N-type buffer layer in the stepped P-type shielding region were collected.

[0078] Electric field simulation and retesting were performed on the cross-section of the finished trench, integrating the probability of electric field stress concentration in the upper section with the magnitude of the peak electric field at the bottom of the lower section.

[0079] When the electric field stress concentration probability in the upper section and the peak electric field value at the bottom of the lower section exceed the preset range in the measured electric field indicators, the width of the self-aligned masking trench etching window is reduced or widened to finely adjust the masking etching window size of subsequent wafer batches.

[0080] By using the multi-angle ion implantation orientation that has been corrected, the doping formation of the stepped P-type shielding region under the self-aligned masking mode is completed. Ions are injected into the wafer according to the corrected tilt angle. The upper and lower shielding regions are doped according to the compensated implantation dose. The lateral doping range is limited by the original trench mask. No additional photolithography process is added throughout the process, avoiding the morphological errors introduced by overlay deviation.

[0081] After molding, sampling of the bottom buffer layer parameters is carried out. Two key indicators are measured: the thickness of the N-type buffer layer deposition film and the regional doping concentration. The basic bearing capacity of the buffer layer can be calculated using standardized calculations. The upper limit of the basic bearing capacity of the buffer layer = measured film thickness × measured doping concentration × electric field coefficient of silicon carbide material. For example, the measured film thickness is 0.32 micrometers, and the measured doping concentration is 1.2 × 10¹. 7 The electric field coefficient of the material is fixed at 1.8 × 10⁻¹ per cubic centimeter. 9 Substituting cubic centimeters per micrometer into the formula, we can obtain the upper limit of the bearing capacity of the buffer layer foundation = 0.32 × 1.2 × 10¹ 7 ×1.8×10⁻¹ 9 =0.006912 kV. The collected physical parameters will be imported into the trench cross-section electric field simulation tool for retesting and analysis. The simulation calculation will statistically analyze two key electrical indicators: the first is the probability of electric field stress concentration around the upper shielding area, and the second is the magnitude of the electric field peak at the lower shielding area at the bottom of the trench. These two values ​​can fully reflect the true electric field distribution of the entire shielding structure and verify the actual improvement effect of the preceding tilt angle and dose correction action.

[0082] The two measured electrical indices obtained from the simulation were compared and verified with the pre-defined acceptable value range. When the probability of electric field stress concentration in the upper section is higher than the upper limit of the range, it indicates that the problem of electric field spikes at the trench corner is still significant. It is necessary to widen the trench etching window width corresponding to the self-aligned masking and optimize the smoothing effect of the upper section electric field by expanding the lateral dimension. When the peak electric field at the bottom of the lower section exceeds the upper limit of the range, it indicates that the pressure bearing space at the bottom is insufficient. The trench etching window width should be narrowed to enhance the ability of the lower shielding area to absorb high-intensity electric fields. The single adjustment range of the window is calculated with reference to the deviation multiplier. The window size correction range = reference window width × measured deviation exceeding the standard ÷ maximum allowable deviation of the range. The adjusted etching window parameters are simultaneously sent to subsequent wafer batches for trench forming. By optimizing the front-end pattern morphology, the probability of electric field imbalance failure in subsequent batches is reduced. The entire process involves connecting the pre-coordinate calibration, coupling coefficient calculation, and risk classification correction data, continuously iterating to narrow the performance dispersion gap between the wafer center and edge regions, and steadily improving the withstand voltage reliability and batch yield of silicon carbide MOSFET devices in the mass production stage.

[0083] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating and controlling a silicon carbide MOSFET device with a trench bottom shielding structure, characterized in that, The method includes the following specific steps: The fabrication coordinates of the stepped P-type shielding region within the silicon carbide wafer trench array are divided, and the process parameters of ion implantation orientation, target doping concentration and lateral width corresponding to the upper and lower sections of the shielding region are separated. Independent process tolerance thresholds for the upper and lower sections are established. Obtain measured data of multi-angle ion implantation process from historical wafer batches on the same production line, and calculate the coupling influence coefficient of the morphology of the low-doped region in the upper width and the high-doped region in the lower width by combining the implantation tilt angle and implantation dose. Based on the coupling influence coefficient, the fluctuation range of the electric field buffering performance of the upper section and the deviation of the high electric field absorption capacity of the lower section of the shielding area at the bottom of the trench of a single device are determined, and the overall electric field tolerance estimate of the shielding structure is obtained. By comparing the electric field tolerance estimate with the process allowable deviation threshold, the risk level of electric field distribution imbalance in the shielded area is determined, and the tilt angle correction amount and partitioned implantation dose compensation parameters for multi-angle ion implantation are obtained. Based on the tilt angle correction and partition injection dose compensation parameters, the deposition thickness and doping level of the N-type buffer layer at the bottom of the shielding area are monitored to obtain the measured electric field distribution results. The masking etching window size of subsequent wafer batches is iteratively fine-tuned based on the measured electric field distribution results.

2. The method for fabricating and controlling a trench-bottom-shielded silicon carbide MOSFET device according to claim 1, characterized in that, The fabrication coordinates of the stepped P-type shielding region within the silicon carbide wafer trench array are divided, and the process parameters of ion implantation orientation, target doping concentration, and lateral width corresponding to the upper and lower sections of the shielding region are separated. Independent process tolerance thresholds for the upper and lower sections are established. The specific steps are as follows: Based on the device withstand voltage simulation results, determine the longitudinal boundary coordinates of the upper and lower shielding areas in the trench depth direction, limit the doping concentration range and upper limit of the lateral width of the upper shielding area, and limit the lower limit of the doping concentration and lower limit of the lateral width of the lower shielding area. Based on the wafer edge region and wafer center region, calculate the dimensional tolerances and doping concentration tolerances of the upper and lower shielding regions to generate differentiated process tolerance thresholds for each region.

3. The method for fabricating and controlling a trench-bottom-shielded silicon carbide MOSFET device according to claim 2, characterized in that, Obtain measured data of multi-angle ion implantation processes from historical wafer batches on the same production line. Combine this with the implantation tilt angle and implantation dose to calculate the coupling influence coefficient between the morphology of the low-doped region in the upper width and the high-doped region in the lower width. The specific steps are as follows: Obtain sample wafers with intact self-aligned masking structures and no additional photolithography stacking processes from historical batches, and divide the upper and lower shielding areas into corresponding implantation tilt angles, implantation doses, measured doping concentrations, and measured lateral widths. The coupling coefficients of the upper shielding region's tilt angle and width, and the dose and doping concentration are calculated to obtain the upper section's partial coupling coefficients. The coupling coefficients of the lower shielding region's tilt angle and width, and the dose and doping concentration are calculated to obtain the partial coupling coefficients. The partition coupling influence coefficient is obtained by integrating the upper segment coupling coefficient and the lower segment coupling coefficient.

4. The method for fabricating and controlling a trench-bottom-shielded silicon carbide MOSFET device according to claim 3, characterized in that, Based on the coupling influence coefficient, the fluctuation range of the electric field buffering performance of the upper section and the deviation of the high electric field absorption capacity of the lower section in the bottom shielding area of ​​a single device trench are determined, and the overall electric field tolerance estimate of the shielding structure is obtained. The specific steps are as follows: The fluctuation range of the upper section's sudden electric field buffering performance is obtained by calculating the actual doping and the offset of the upper section's width relative to the preset value based on the upper section's sub-coupling coefficient. The deviation of the high electric field absorption capacity at the bottom of the trench is obtained by calculating the actual doping and the offset of the width of the lower section relative to the preset value based on the lower section's sub-coupling coefficient. Based on the weighting of the electric field load at the bottom of the trench, the fluctuation range of the upper section's abrupt electric field buffering performance and the deviation of the lower section's high electric field absorption capacity at the bottom of the trench are combined for calculation, and the overall electric field tolerance estimate of the shielding structure is output.

5. The method for fabricating and controlling a trench-bottom-shielded silicon carbide MOSFET device according to claim 4, characterized in that, By comparing the predicted electric field tolerance with the process tolerance threshold, the risk level of electric field distribution imbalance in the shielded area is determined, and the tilt angle correction and zonal implantation dose compensation parameters for multi-angle ion implantation are obtained. The specific steps are as follows: By comparing the estimated electric field tolerance with the process allowable deviation threshold, the risk level of electric field distribution imbalance in the shielded area is divided into the estimated difference range corresponding to low electric field imbalance risk, medium electric field imbalance risk, and high electric field imbalance risk. The risk level is determined by comparing the difference between the estimated value and the benchmark withstand voltage threshold and assigning the range to the risk level. Among them, for low-risk cases, only the dose compensation value of the lower segment ion implantation is slightly adjusted; for medium-risk cases, the implantation dose of the upper and lower segments is corrected simultaneously; and for high-risk cases, the incident tilt angle of multi-angle ion implantation and the two-segment partition implantation dose are adjusted simultaneously. The tilt correction amount and zonal injection dose compensation parameters for multi-angle ion implantation are determined based on the risk level.

6. The method for fabricating and controlling a trench-bottom-shielded silicon carbide MOSFET device according to claim 5, characterized in that, Based on the tilt angle correction and partition injection dose compensation parameters, the deposition thickness and doping level of the N-type buffer layer at the bottom of the shielding area are monitored to obtain the measured electric field distribution results. The masking etching window size for subsequent wafer batches is then iteratively adjusted based on the measured electric field distribution results. The specific steps are as follows: The stepped P-type shielding zone for self-masking is determined based on the multi-angle ion implantation orientation. Measured parameters of the film thickness and doping concentration of the N-type buffer layer in the stepped P-type shielding region were collected. Electric field simulation and retesting were performed on the cross-section of the finished trench, integrating the probability of electric field stress concentration in the upper section with the magnitude of the peak electric field at the bottom of the lower section. When the electric field stress concentration probability in the upper section and the peak electric field value at the bottom of the lower section exceed the preset range in the measured electric field indicators, the width of the self-aligned masking trench etching window is reduced or widened to finely adjust the masking etching window size of subsequent wafer batches.

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