Preparation method of high-voltage GaN HEMT device with superlattice back barrier structure

Abstract

The application discloses a preparation method of a high-voltage GaN HEMT device with a superlattice back barrier structure, and relates to the technical field of semiconductors.The technical scheme points of the application include the following specific steps: collecting superlattice single-layer thickness, component gradient, periodic stacking number, and in-situ growth stress value to construct a back barrier superlattice process benchmark data set; selecting an optimal back barrier benchmark stacking unit in the back barrier superlattice process benchmark data set according to device off-state buffer leakage current and back surface heat dissipation thermal resistance; and forming a trench morphology process set based on trench depth, sidewall inclination angle, and trench bottom round corner curvature etching parameters, and marking the limit breakdown failure trench parameters of the trench morphology process set as a boundary control unit.The effect is that the influence of multi-parameter coupling on device leakage and heat dissipation performance can be quantified, and the optimal stacking unit can strengthen the electron beam binding capacity of the channel and weaken the charge tunneling effect under high voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure. Background Technology

[0002] High-voltage GaNHEMT devices, leveraging the high voltage withstand capability and low conduction loss characteristics of wide-bandgap semiconductor materials, are widely used in high-power power electronics applications such as automotive power conversion and high-voltage energy storage converters. Conventional high-voltage devices often employ a single-layer AlGaN buffer layer to suppress off-state leakage current. However, the single-layer buffer layer has a weak confinement effect on channel electrons, leading to significant charge tunneling under high-voltage conditions. This results in persistently high off-state buffer leakage current, with leakage losses continuously converting into heat, increasing the thermal resistance on the back of the chip. Over long-term operation, this can lead to reliability defects such as threshold drift and voltage withstand decay. To improve electron confinement capabilities, the industry has introduced superlattice back barrier structures to replace the single-layer buffer layer.

[0003] However, existing superlattice epitaxial processes lack a standardized data management system. They do not simultaneously collect core parameters such as single-layer thickness, composition gradient, number of periodic stacks, and in-situ residual stress to construct a process benchmark dataset. This makes it impossible to quantify the impact of multi-parameter coupling on device leakage current and heat dissipation performance. Relying solely on fixed empirical parameters to grow thin films makes it difficult to select the optimal benchmark stacking unit that balances low leakage current and low thermal resistance. The superlattice structure and device end-performance have poor matching. Furthermore, in trench forming processes, existing etching processes only individually control trench depth, sidewall tilt angle, and bottom fillet curvature. They do not use breakdown tests to define the boundary control unit corresponding to the failure-type trench, making it impossible to clearly define the safe design range of trench morphology. Insufficient bottom fillet curvature of the trench can induce local electric field concentration, significantly reducing the device's blocking voltage. The lattice damage caused by etching can also increase the trap charge density at the gate oxide interface, further aggravating leakage losses. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a method for fabricating high-voltage GaNHEMT devices with a superlattice back barrier structure.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure, comprising the following specific steps:

[0007] A back barrier superlattice process benchmark dataset was constructed by collecting superlattice single-layer thickness, composition gradient, number of periodic stacks, and in-situ growth stress values. The optimal back barrier benchmark stacking unit was calibrated in the back barrier superlattice process benchmark dataset based on device off-state buffer leakage current and back-side heat dissipation thermal resistance.

[0008] Based on the etching parameters of trench depth, sidewall tilt angle, and bottom fillet curvature, a trench morphology process set is formed. The ultimate breakdown failure trench parameters in the trench morphology process set are marked as boundary control units. Combined with the optimal back barrier reference stacking unit and the boundary control unit, a synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology is generated. Based on the synergistic electrical correlation feature surface and the trench morphology process set, a target optimized trench unit is generated.

[0009] Based on the target optimization of the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation law of trench unit, a collaborative performance control database of superlattice and trench is constructed.

[0010] A suitable process control scheme is generated by combining the back barrier superlattice process benchmark dataset with the collaborative performance control database.

[0011] Preferably, a back-barrier superlattice process benchmark dataset is constructed by collecting superlattice single-layer thickness, composition gradient, number of periodic stacks, and in-situ growth stress values. The optimal back-barrier benchmark stacking cells in the dataset are then selected based on the device's off-state buffer leakage current and back-side thermal resistance. Specifically, the following steps are included:

[0012] The epitaxial chamber growth temperature, V / III gas source ratio, and component doping flow rate of AlGaN barrier sublayer and GaN channel sublayer in the continuous alternating epitaxial growth of the substrate back side are collected to obtain the continuous alternating epitaxial growth data of the substrate back side. Based on the thickness of each layer of the wafer superlattice, the component gradient range, the total number of cycles, and the residual stress inside the thin film in the continuous alternating epitaxial growth data of the substrate back side, a back barrier superlattice process benchmark dataset is generated.

[0013] A multi-dimensional screening scheme is generated by setting the upper limit threshold of the off-state buffer leakage current and the upper limit threshold of the back thermal resistance of the chip. Based on the historical stacking parameter combinations of the back barrier superlattice process benchmark dataset, the process parameter combinations that meet the multi-dimensional screening scheme are selected, and the superlattice stacking structure corresponding to the parameter combination is marked as the optimal back barrier benchmark stacking unit.

[0014] Preferably, based on the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation law of the target optimized trench unit, a collaborative performance control database for superlattice and trench is constructed, specifically including the following steps:

[0015] The trench morphology process set is formed by collecting the trench depth, sidewall tilt angle, and bottom fillet curvature etching parameters. Based on the ultimate breakdown failure trench parameters in the trench morphology process set, the boundary reference cell is obtained. The device blocking voltage, gate oxide interface trap charge, and bottom electric field peak data corresponding to the optimal back barrier reference stack cell and the boundary reference cell are calculated to generate the synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology. The first target optimized trench cell is generated based on the synergistic electrical correlation feature surface and the trench morphology process set.

[0016] Obtain the appropriate high-temperature operating conditions from the historical fabrication database of the same power level to form the second target optimized trench unit;

[0017] A database for the coordinated performance management of superlattices and trenches is formed by integrating the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation patterns of the trench unit optimized by the first objective and the trench unit optimized by the second objective.

[0018] Preferably, a collaborative performance management database for superlattice and trench is formed by integrating the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation patterns of the first-objective optimized trench unit and the second-objective optimized trench unit, specifically including the following steps:

[0019] Extract the bottom electric field peak, gate oxide interface trap charge density, and polarization electron blocking coefficient corresponding to the back barrier layer of the superlattice of different periods in the first target optimization trench unit, and construct the first cooperative performance feature subset;

[0020] Extract the annealing activation uniformity, chip thermal resistance, and blocking leakage level of the matching gradient component superlattice back barrier layer in the second target optimization trench unit to construct the second cooperative performance feature subset.

[0021] The first and second subsets of collaborative performance features are combined to form a collaborative performance management database that can be retrieved in real time and linked across processes.

[0022] Preferably, the device blocking voltage, gate oxide interface trap charge, and bottom electric field peak data corresponding to the optimal back barrier reference stacking cell and boundary control cell are calculated to generate a synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology. Based on the synergistic electrical correlation feature surface and the trench morphology process set, a first target optimized trench cell is generated, specifically including the following steps:

[0023] The optimal back barrier reference stacking cell is matched with the trench structure of the trench morphology process to obtain the multi-physics joint relationship. The corresponding blocking withstand voltage value, total trap charge of the gate oxide interface, and peak electric field at the bottom corner of the trench are calculated in the multi-physics joint relationship to generate the first set of cooperative electrical parameter datasets.

[0024] By matching the limit breakdown failure trench boundary reference cell with the optimal back barrier reference stacked cell of the same specification, a second set of cooperative electrical parameter datasets is obtained.

[0025] Based on the numerical difference between the first set of collaborative electrical parameter datasets and the second set of collaborative electrical parameter datasets, a three-dimensional collaborative electrical correlation feature surface is generated by combining the number of superlattice periods, the curvature of the bottom fillet of the trench, and the leakage current and withstand voltage performance of the device.

[0026] A preset threshold for the concentration suppression of the electric field at the bottom of the trench is set. The morphological parameters selected by the trench morphology process are matched with the cooperative electrical correlation feature surface to obtain the cooperative electrical correlation value. The trench units with the bottom electric field peak value lower than the suppression threshold in the cooperative electrical correlation value are marked as the first target optimized trench units.

[0027] Preferably, an adapted process control scheme is generated by combining the back barrier superlattice process benchmark dataset and the collaborative performance control database, specifically including the following steps:

[0028] Multi-gradient P-type ion segmented implantation is carried out according to the depth direction of the bottom of the trench, and the gradient doped shielding layer at the bottom of the trench is prepared by segmented isothermal activation annealing to obtain the back superlattice back barrier layer of the wafer. The actual composition and periodic parameters of the back superlattice back barrier layer of the wafer are monitored to obtain the back barrier superlattice process benchmark dataset.

[0029] The benchmark stacking unit with the smallest deviation in the back barrier superlattice process benchmark dataset is selected, and the trench morphology parameters corresponding to the benchmark stacking unit are extracted. The trench morphology parameters are then matched with the collaborative performance control database to obtain the appropriate process control threshold.

[0030] Generate an adaptive process control scheme based on the adaptive process control threshold.

[0031] Preferably, the process control scheme is generated based on the process control threshold, specifically including the following steps:

[0032] The superlattice back barrier process is obtained by adjusting the back superlattice epitaxial rate, front trench etching RF power, trench bottom ion implantation segmented dose, and shielding layer annealing step holding time based on the adaptive process control threshold.

[0033] Based on the superlattice back barrier process, a passivated gate oxide layer and a polysilicon gate structure are prepared on the inner wall of the trench. The device is then subjected to source region ion implantation, ohmic contact metallization, and chip edge gradient field limiting ring preparation. The electron blocking efficiency of the superlattice back barrier and the electric field equalization coefficient of the bottom shielding layer of the trench are used to jointly verify the process window of each process to obtain an appropriate process control scheme.

[0034] Preferably, the benchmark stacking unit with the smallest central deviation in the back barrier superlattice process benchmark dataset is selected, the trench morphology parameters corresponding to the benchmark stacking unit are extracted, and the trench morphology parameters are matched with the collaborative performance control database to obtain the appropriate process control threshold. Specifically, this includes the following steps:

[0035] If the current back-side superlattice epitaxial growth rate exceeds the epitaxial window corresponding to the adaptive control threshold, the gas supply rate of the MOCVD chamber will be adjusted to slow down or speed up the superlattice stacking growth rate.

[0036] If the current trench dry etching RF power exceeds the morphology window corresponding to the adaptation control threshold, the plasma RF output power is adjusted up or down to correct the rounded corner curvature at the bottom of the trench.

[0037] If the dose of a single segment of P-type ion implantation at the bottom of the trench is lower than the dose standard corresponding to the adaptive control threshold, the output intensity of the ion source will be increased segment by segment to supplement the doping concentration of the shielding layer.

[0038] If the current isothermal annealing time of each segment of the shielding layer does not reach the activation standard corresponding to the adaptation control threshold, the isothermal annealing time of the corresponding temperature range will be extended until the electric field balance coefficient of the bottom shielding layer and the electron blocking efficiency of the superlattice back barrier both reach the preset qualified standard.

[0039] Compared with existing technologies, this invention has the following advantages: By collecting multi-dimensional growth parameters such as superlattice single-layer thickness, aluminum composition gradient, number of periodic stacks, and in-situ residual stress, and using off-state buffer leakage current and back-side heat dissipation thermal resistance as screening indicators to calibrate the optimal back-side barrier benchmark stacking unit, the influence of multi-parameter coupling on device leakage current and heat dissipation performance can be quantified. The optimal stacking unit can enhance the channel electron binding capability, weaken the charge tunneling effect under high voltage, reduce off-state buffer leakage current, reduce heat accumulation caused by leakage loss, control the back-side heat dissipation thermal resistance of the chip, and facilitate the mitigation of threshold drift and withstand voltage decay problems after long-term device operation. By marking the failure trench parameters through ultimate breakdown test as boundary control unit, the electric field distribution law after the trench morphology and superlattice structure coupling is intuitively reflected by the three-dimensional feature surface, and the target optimized trench unit with excellent electric field dispersion effect is screened. The optimized trench can ensure that the bottom rounded corner curvature is within a reasonable range, avoid the withstand voltage drop caused by local electric field accumulation, reduce lattice damage caused by etching, reduce the gate oxide interface trap charge density, further suppress device leakage loss, and improve the device blocking withstand voltage level. Attached Figure Description

[0040] Figure 1 This is a schematic flowchart illustrating a method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure, as provided in an embodiment of the present invention.

[0041] Figure 2This is a schematic diagram illustrating the collaborative performance management database obtained by a method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure, as provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0044] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0045] Reference Figures 1-2 As shown.

[0046] The embodiments further illustrate the fabrication method of a high-voltage GaNHEMT device with a superlattice back barrier structure proposed in this invention.

[0047] A method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure, comprising the following specific steps:

[0048] A back barrier superlattice process benchmark dataset was constructed by collecting superlattice single-layer thickness, composition gradient, number of periodic stacks, and in-situ growth stress values. The optimal back barrier benchmark stacking unit was calibrated in the back barrier superlattice process benchmark dataset based on device off-state buffer leakage current and back-side heat dissipation thermal resistance.

[0049] Based on the etching parameters of trench depth, sidewall tilt angle, and bottom fillet curvature, a trench morphology process set is formed. The ultimate breakdown failure trench parameters in the trench morphology process set are marked as boundary control units. Combined with the optimal back barrier reference stacking unit and the boundary control unit, a synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology is generated. Based on the synergistic electrical correlation feature surface and the trench morphology process set, a target optimized trench unit is generated.

[0050] Based on the target optimization of the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation law of trench unit, a collaborative performance control database of superlattice and trench is constructed.

[0051] A suitable process control scheme is generated by combining the back barrier superlattice process benchmark dataset with the collaborative performance control database.

[0052] A back-barrier superlattice process benchmark dataset was constructed by collecting superlattice single-layer thickness, composition gradient, number of periodic stacks, and in-situ growth stress values. The optimal back-barrier benchmark stacking cells in the dataset were then calibrated based on device off-state buffer leakage current and back-side thermal resistance. The specific steps include:

[0053] The epitaxial chamber growth temperature, V / III gas source ratio, and component doping flow rate of AlGaN barrier sublayer and GaN channel sublayer in the continuous alternating epitaxial growth of the substrate back side are collected to obtain the continuous alternating epitaxial growth data of the substrate back side. Based on the thickness of each layer of the wafer superlattice, the component gradient range, the total number of cycles, and the residual stress inside the thin film in the continuous alternating epitaxial growth data of the substrate back side, a back barrier superlattice process benchmark dataset is generated.

[0054] A multi-dimensional screening scheme is generated by setting the upper limit threshold of the off-state buffer leakage current and the upper limit threshold of the back thermal resistance of the chip. Based on the historical stacking parameter combinations of the back barrier superlattice process benchmark dataset, the process parameter combinations that meet the multi-dimensional screening scheme are selected, and the superlattice stacking structure corresponding to the parameter combination is marked as the optimal back barrier benchmark stacking unit.

[0055] We constructed a benchmark dataset for back-barrier superlattice processes. The data collection focused on AlGaN barrier sublayers and GaN channel sublayers grown alternately on the back side of the substrate. The chamber temperature during epitaxial growth directly regulates the atomic migration rate of the thin film. Too low a temperature leads to disordered lattice atomic arrangement, while too high a temperature causes component desorption. Both temperature deviations alter the actual thickness of the superlattice monolayer. For example, increasing the chamber temperature by 30 degrees Celsius increases Al atom desorption, resulting in a reduction of approximately 15% in the thickness of the AlGaN barrier sublayer. The VIII gas source ratio determines the nitrogen-to-metal element ratio within the epitaxial film. An imbalance in this ratio causes abrupt changes in the composition gradient. The metal component flow rate within the gas source synchronously controls the aluminum content within the film. Continuously increasing the flow rate widens the composition gradient range, while a constant flow rate flattens the composition gradient. These three types of growth process parameters together constitute the original data for alternating back-side epitaxial growth on the substrate. Based on the original growth data, four structural property parameters of the wafer superlattice are extracted: the thickness of each film layer, the composition gradient range, the total number of stacking cycles, and the internal residual stress remaining after film formation. After all four types of parameters are entered and integrated, a complete back barrier superlattice process benchmark dataset is formed. Each set of parameters in the dataset corresponds to a complete superlattice stacking structure, realizing a one-to-one correspondence between the growth process and the finished film structure.

[0056] After the baseline dataset for back-barrier superlattice technology was built, the optimal back-barrier baseline stacking cell selection process began. This selection relied on a multi-dimensional selection scheme built using preset dual performance thresholds. These two thresholds corresponded to two key defect indicators during long-term device operation. The upper limit threshold for off-state buffer leakage current was used to control charge tunneling loss in the device's off-state state. A leakage current exceeding this threshold indicated insufficient binding capacity of the superlattice back barrier for channel electrons, leading to continuous leakage loss under high-voltage conditions and exacerbating device heating. The upper limit threshold for back-side thermal resistance controlled the device's heat dissipation and conduction capabilities. A thermal resistance exceeding this threshold indicated that residual stress within the superlattice film caused numerous lattice defects. These defects hindered heat conduction to the substrate, and the resulting heat accumulation further increased the leakage current. These two performance indicators were mutually restrictive. By using a multi-dimensional screening scheme to traverse all historical stacking parameter combinations within the process benchmark dataset, the measured off-state buffer leakage current and back heat dissipation thermal resistance values ​​corresponding to each parameter group are compared one by one. Parameter combinations with both performance values ​​below the preset upper limit threshold are retained, while other parameter combinations are directly eliminated. The entire superlattice stacking structure corresponding to the parameter combination that satisfies the dual threshold constraint is identified as the optimal back barrier benchmark stacking unit.

[0057] By collecting controllable process parameters at the epitaxial growth source and converting them into quantifiable superlattice structure properties to form a standardized database, and then using the leakage current and heat dissipation performance of the device terminal as a reverse constraint to screen structures, a two-way matching is achieved from thin film growth process to device terminal performance, eliminating the performance imbalance problem caused by single parameter optimization. The optimal stacking unit obtained by screening can not only block off-state charge tunneling by relying on reasonable composition gradient and number of cycles to reduce buffer leakage current, but also control the residual stress of the thin film within a reasonable range, reduce lattice defects, and reduce the heat conduction resistance on the back of the chip, thus simultaneously improving the two core shortcomings of device leakage current and heat dissipation.

[0058] Based on the target optimization of the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation law of the trench unit, a collaborative performance control database for superlattice and trench is constructed, which specifically includes the following steps:

[0059] The trench morphology process set is formed by collecting the trench depth, sidewall tilt angle, and bottom fillet curvature etching parameters. Based on the ultimate breakdown failure trench parameters in the trench morphology process set, the boundary reference cell is obtained. The device blocking voltage, gate oxide interface trap charge, and bottom electric field peak data corresponding to the optimal back barrier reference stack cell and the boundary reference cell are calculated to generate the synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology. The first target optimized trench cell is generated based on the synergistic electrical correlation feature surface and the trench morphology process set.

[0060] Obtain the appropriate high-temperature operating conditions from the historical fabrication database of the same power level to form the second target optimized trench unit;

[0061] A database for the coordinated performance management of superlattices and trenches is formed by integrating the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation patterns of the trench unit optimized by the first objective and the trench unit optimized by the second objective.

[0062] Based on the electrical co-modeling of trench etching parameters and superlattice stacked structure, three types of etching variables were first collected: trench depth, sidewall tilt angle, and trench bottom fillet curvature. Multiple sets of parameter combinations were summarized to form a complete trench morphology process set. Each set of parameters in the process set corresponds to an independent device sample, and ultimate withstand voltage breakdown tests were conducted. Parameter combinations that resulted in breakdown failure were uniformly classified and marked as boundary control units, thereby defining the safe design range of trench morphology. For example, if the value of the trench bottom fillet curvature is too small, it will cause a high concentration of local electric field, and the corresponding parameter will be classified into the boundary control unit. Subsequently, combined with the optimal back barrier reference stacked unit selected in the early stage, three sets of electrical data were simultaneously extracted from the two sets of units: the peak electric field at the bottom of the trap charge at the gate oxide interface of the blocking withstand voltage gate oxide interface. Multi-dimensional data fitting was used to generate a co-electrical correlation feature surface, which can intuitively reflect the continuous fluctuation trend of device electrical performance when the superlattice stacked structure and trench morphology change synchronously. Based on the qualified parameters in the trench morphology process set of the surface reverse screening, the morphology schemes that are easy to trigger electric field concentrated breakdown are eliminated, and the first target optimized trench unit is obtained. This unit only meets the basic requirements of room temperature static withstand voltage and uniform electric field distribution.

[0063] The trench design was optimized for operating conditions by incorporating actual device operating conditions. Various high-temperature operating scenarios recorded in the historical fabrication database of devices of the same power level were retrieved to extract the performance deviation patterns caused by lattice thermal expansion and charge migration under high-temperature environments. This was used to correct the trench morphology parameters, resulting in a second-target optimized trench unit. High-temperature environments accelerate the formation of interface defects on the trench sidewalls and weaken the polarization shielding capability of superlattice materials. The second-target optimized trench unit specifically compensates for these high-temperature losses, overcoming the limitation of the first-target optimized trench unit, which is only suitable for room-temperature environments.

[0064] A final control database is constructed by integrating the three core performance variation patterns of two types of optimized trench units: electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency. The electric field dispersion coefficient characterizes the ability of the trench structure to distribute the internal electric field of the device; a higher value indicates a smoother electric field distribution and a lower risk of breakdown. Interface defect density reflects the impact of the trench etching process on the gate oxide interface lattice integrity; unreasonable etching angles and fillet parameters can significantly increase defect density, inducing leakage and threshold drift. Superlattice polarization shielding efficiency represents the ability of the back barrier structure to counteract the interference of channel polarization charges; changes in trench morphology affect the channel electric field boundary, indirectly affecting the shielding effect of polarization charges. The continuous trends of the three performance indicators of the first-objective optimized trench unit at room temperature with changes in trench parameters are fully extracted, and then the fluctuation curves of the three performance indicators of the second-objective optimized trench unit under high-temperature conditions are superimposed. All variation patterns are integrated and summarized to ultimately form a collaborative performance control database for superlattices and trenches.

[0065] This database fully covers two scenarios: room temperature static withstand voltage and high temperature actual operation. It clearly records the linkage effect of trench morphology parameter changes on the three core performance parameters. It can predict the device performance after different trenches are combined with superlattice structures before device fabrication, realize precise control of the synergistic process of trench etching and back barrier superlattice, and avoid the problem of high temperature failure electric field concentration and interface leakage caused by single structure optimization.

[0066] A collaborative performance management database for superlattices and trenches is formed by integrating the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation patterns of the first and second objective optimized trench units. This specifically includes the following steps:

[0067] Extract the bottom electric field peak, gate oxide interface trap charge density, and polarization electron blocking coefficient corresponding to the back barrier layer of the superlattice of different periods in the first target optimization trench unit, and construct the first cooperative performance feature subset;

[0068] Extract the annealing activation uniformity, chip thermal resistance, and blocking leakage level of the matching gradient component superlattice back barrier layer in the second target optimization trench unit to construct the second cooperative performance feature subset.

[0069] The first and second subsets of collaborative performance features are combined to form a collaborative performance management database that can be retrieved in real time and linked across processes.

[0070] Based on the first objective, the trench unit is optimized to carry out parameter extraction and the construction of the first collaborative performance feature subset. This trench unit is suitable for room temperature static high pressure working scenarios and is matched with superlattice back barrier layers with different periodic stacking forms. The extraction process simultaneously records three types of core performance data: 1. Bottom electric field peak value, used to measure the concentration of electric field at the bottom of the trench. Changes in the number of superlattice stacking periods directly alter the channel charge binding capability. When the number of periods is low, the bottom electric field peak value will increase significantly, easily causing local breakdown of the device; 2. Gate oxide interface trap charge density, used to characterize the damage caused by trench etching to the gate oxide interface lattice structure. Deviations in etching morphology parameters will increase the number of interface trap charges, continuously inducing off-state leakage; 3. Polarization electron blocking coefficient, representing the ability of the superlattice back barrier to block polarization electrons from overflowing the channel. This value shows a regular change with the number of superlattice stacking periods. All the variation patterns of the three sets of parameters under different period superlattice combinations with trench structures are uniformly included to form a complete first synergistic performance feature subset. This subset fully covers the coupling law of the three types of electrical performance of electric field, interface polarization, etc. under room temperature static withstand voltage conditions.

[0071] Data was collected for the second target optimized trench unit, which is designed for long-term high-temperature operation and paired with a superlattice back barrier layer with gradient aluminum composition. Three types of performance indicators adapted to high-temperature scenarios were collected to construct a second subset of synergistic performance characteristics. Annealing activation uniformity reflects the consistency of impurity activation within the superlattice during high-temperature processing. Uneven distribution of gradient aluminum composition will cause a decrease in annealing activation uniformity, resulting in large-scale dispersion of device on-resistance. Chip thermal resistance represents the resistance to heat conduction from the thin film to the substrate. Under high-temperature operation, residual stress within the superlattice will generate lattice defects, which will increase the overall thermal resistance. Heat accumulation will further deteriorate the blocking leakage level. The blocking leakage level directly reflects the charge tunneling loss of the device under high-temperature and high-pressure conditions. The superlattice structure with gradient aluminum composition can reduce the leakage increase caused by high temperature. The three types of thermal leakage-related parameters after combining the gradient aluminum composition superlattice with the trench are fully collected to form the second subset of synergistic performance characteristics, specifically corresponding to the thermal stability and leakage performance of the device under long-term high-temperature operation.

[0072] The first and second subsets of collaborative performance features respectively encapsulate the electrical performance characteristics at room temperature and the thermal leakage performance characteristics at high temperature. Each subset contains quantitative performance change curves after matching the trench morphology with the superlattice structure. Combining these two subsets generates the final collaborative performance control database. This database integrates all relevant performance data, including electric field, interface polarization, thermal resistance, and leakage current, under all operating conditions at room temperature and high temperature. Internal parameters can be retrieved in real-time from production equipment. Furthermore, it enables cross-process linkage control between trench etching and superlattice epitaxial growth. For example, during production, retrieving corresponding parameters from the database allows for simultaneous calibration of the superlattice stacking period and trench fillet curvature, balancing room temperature withstand voltage and high temperature heat dissipation requirements. This avoids device performance bottlenecks caused by optimizing parameters under single operating conditions, achieving standardized collaborative process control of the superlattice back barrier and trench structure under all operating conditions.

[0073] The process involves calculating the device blocking voltage, gate oxide interface trap charge, and bottom electric field peak data corresponding to the optimal back barrier reference stack cell and boundary control cell to generate a synergistic electrical correlation feature surface between the superlattice back barrier and trench morphology. Based on the synergistic electrical correlation feature surface and the trench morphology process set, a first target optimized trench cell is generated. This process includes the following steps:

[0074] The optimal back barrier reference stacking cell is matched with the trench structure of the trench morphology process to obtain the multi-physics joint relationship. The corresponding blocking withstand voltage value, total trap charge of the gate oxide interface, and peak electric field at the bottom corner of the trench are calculated in the multi-physics joint relationship to generate the first set of cooperative electrical parameter datasets.

[0075] By matching the limit breakdown failure trench boundary reference cell with the optimal back barrier reference stacked cell of the same specification, a second set of cooperative electrical parameter datasets is obtained.

[0076] Based on the numerical difference between the first set of collaborative electrical parameter datasets and the second set of collaborative electrical parameter datasets, a three-dimensional collaborative electrical correlation feature surface is generated by combining the number of superlattice periods, the curvature of the bottom fillet of the trench, and the leakage current and withstand voltage performance of the device.

[0077] A preset threshold for the concentration suppression of the electric field at the bottom of the trench is set. The morphological parameters selected by the trench morphology process are matched with the cooperative electrical correlation feature surface to obtain the cooperative electrical correlation value. The trench units with the bottom electric field peak value lower than the suppression threshold in the cooperative electrical correlation value are marked as the first target optimized trench units.

[0078] Basic electrical parameter samples were collected, and the optimal back barrier reference stacking units, selected through screening, were matched one-to-one with all trench structures within the trench morphology process set to establish a multi-physics joint relationship under the coexistence of superlattice thin films and trench etched structures. This multi-physics joint relationship can simultaneously reflect the interaction between the lattice polarization electric field interface charge distribution and the spatial electric field distribution. Based on this relationship, three core electrical indices can be calculated: 1. Blocking withstand voltage, representing the highest operating voltage the device can withstand in the off-state; 2. Total gate oxide interface trap charge, reflecting the degree of lattice damage caused by the trench etching process to the gate dielectric interface; 3. Peak electric field at the bottom corner of the trench, representing the strength of the electric field accumulation at a local location in the trench. The indices calculated after matching all structures are uniformly collected to form the first set of collaborative electrical parameter datasets, covering the electrical performance of various conventional trenches paired with standard superlattice structures.

[0079] A failure control electrical sample dataset was constructed. The trenches that had already experienced ultimate breakdown failure within the trench morphology process set were selected as boundary control units. The structure of these units was matched with the optimal back barrier reference stacking units of the same specification. The multiphysics numerical calculation process was repeated to extract the peak electric field at the bottom of the blocking voltage gate oxide trap charge corresponding to this combination. The results were then summarized to form a second set of collaborative electrical parameter datasets. All parameters in this dataset correspond to the critical state of device failure and are used to delineate the dangerous range of trench morphology parameters.

[0080] A three-dimensional collaborative electrical correlation feature surface is constructed based on the numerical differences between the two datasets. The numerical deviation between the two datasets can intuitively reflect the change in electrical performance when the trench morphology transitions from a qualified state to a breakdown failure state. Two core structural variables, the number of superlattice periods and the rounded corner curvature at the bottom of the trench, are introduced. Combined with the performance variation laws of leakage current and withstand voltage, a three-dimensional surface is fitted. The three dimensions of the surface correspond to the superlattice stacking parameters, trench morphology parameters, and device electrical performance, respectively. It can continuously and intuitively present the synchronous change trend of electric field, leakage current, and withstand voltage under any structural combination scheme. For example, the continuous reduction of the rounded corner curvature at the bottom of the trench will intuitively show the trajectory of the rapid rise of the bottom electric field peak and the synchronous decrease of the withstand voltage on the surface.

[0081] The first target optimized trench unit is obtained by screening based on the electric field constraint threshold. The electric field concentration suppression threshold at the bottom of the trench is preset as a safety judgment standard. All morphological parameters in the trench morphology process set are traversed. Each set of parameters is substituted into the three-dimensional cooperative electrical correlation feature surface to obtain the corresponding cooperative electrical correlation value. The peak electric field at the bottom of the trench contained in the correlation value is compared with the preset suppression threshold. Only the trench structure with the peak electric field at the bottom is stably lower than the suppression threshold is retained. When this type of trench is paired with the optimal back barrier stacking unit, there will be no problem of excessive accumulation of local electric field. It can stably maintain a high blocking voltage and a low interface trap charge. It is uniformly marked as the first target optimized trench unit.

[0082] A quantitative evaluation standard is established by comparing two sets of data: qualified and failed. A continuous mapping between multiple structural parameters and electrical performance is achieved by relying on three-dimensional curved surfaces. The peak electric field is used as the core screening indicator to avoid electric field concentration breakdown defects caused by trench morphology from the root, and to provide a trench foundation structure that meets the room temperature pressure resistance standard for the subsequent construction of a collaborative database.

[0083] A suitable process control scheme is generated by combining the back barrier superlattice process benchmark dataset and the collaborative performance control database, specifically including the following steps:

[0084] Multi-gradient P-type ion segmented implantation is carried out according to the depth direction of the bottom of the trench, and the gradient doped shielding layer at the bottom of the trench is prepared by segmented isothermal activation annealing to obtain the back superlattice back barrier layer of the wafer. The actual composition and periodic parameters of the back superlattice back barrier layer of the wafer are monitored to obtain the back barrier superlattice process benchmark dataset.

[0085] The benchmark stacking unit with the smallest deviation in the back barrier superlattice process benchmark dataset is selected, and the trench morphology parameters corresponding to the benchmark stacking unit are extracted. The trench morphology parameters are then matched with the collaborative performance control database to obtain the appropriate process control threshold.

[0086] Generate an adaptive process control scheme based on the adaptive process control threshold.

[0087] A baseline dataset for the fabrication and process of the back-side superlattice barrier layer on the wafer was collected. Multi-gradient P-type ion implantation was performed segmented according to the depth direction at the bottom of the trench. Different ion implantation doses were set at different depths to form a doped shielding layer with stratified concentration distribution at the bottom of the trench, mitigating the problem of local electric field accumulation at the trench bottom. After ion implantation, segmented isothermal activation annealing was performed. Segmented temperature control avoids defects such as surface aluminum component desorption or insufficient activation of underlying impurities caused by a single high-temperature range, stabilizing the formation of the gradient-doped shielding layer at the bottom of the trench and simultaneously completing the overall fabrication of the back-side superlattice barrier layer. After fabrication, the actual aluminum component distribution and the number of periodic stacks of the back-side superlattice barrier layer were monitored in real time. Derivative parameters of layer thickness and residual stress during growth were recorded simultaneously. All measured process and structural data were collected and comprehensively constructed into a baseline dataset for the back-side barrier superlattice process. This dataset records the actual fabrication parameters and formed structural state of each batch of superlattice films.

[0088] After selecting the optimal stacking cells and matching them with the collaborative performance control database to obtain control thresholds, the system iterates through all stacking cells in the back-barrier superlattice process benchmark dataset. It compares the numerical deviations between the preset standard parameters and the actual test parameters of each cell, retaining the structure with the smallest overall deviation as the benchmark stacking cell. This cell exhibits the highest growth process stability, and its overall device leakage current and heat dissipation performance better matches the design standards. The system extracts the complete set of trench morphology parameters corresponding to this benchmark stacking cell from the previous simulation matching, including trench depth, sidewall tilt angle, and bottom fillet curvature. These parameters are then imported into the collaborative performance control database to complete data matching. The database stores the full-condition performance variation law of electric field dispersion and interface defect polarization shielding after trench and superlattice pairing. The system automatically retrieves the performance boundaries adapted to the current benchmark stacking cell and outputs the corresponding process control thresholds for each process step. These thresholds define the upper and lower ranges of allowable parameter fluctuations for each process step, such as limiting the minimum range of the trench bottom fillet curvature to avoid the risk of electric field concentration failure.

[0089] A complete adaptive process control scheme is generated based on the adaptive process control thresholds. The scheme coordinates the entire process of superlattice epitaxial growth trench ion implantation trench etching annealing. The scheme specifies the standard values ​​and allowable error ranges for the number of superlattice single-layer thickness aluminum composition gradient periodic stacks, and simultaneously specifies the temperature, dosage, and duration of trench etching, ion implantation, and annealing processes. All process standards are constrained by the control thresholds. The entire scheme establishes data correlation between the superlattice epitaxial process and the trench processing process. Based on measured superlattice forming data, it combines the constraints of trench and superlattice synergistic performance to uniformly control the production process, solving the structural parameter mismatch problem caused by controlling a single process alone. This ensures that the superlattice back barrier and trench structure always maintain the optimal synergistic state during batch preparation, and stabilizes the core performance indicators of device off-state leakage current blocking voltage heat dissipation thermal resistance.

[0090] Generate an adaptive process control plan based on the adaptive process control threshold, specifically including the following steps:

[0091] The superlattice back barrier process is obtained by adjusting the back superlattice epitaxial rate, front trench etching RF power, trench bottom ion implantation segmented dose, and shielding layer annealing step holding time based on the adaptive process control threshold.

[0092] Based on the superlattice back barrier process, a passivated gate oxide layer and a polysilicon gate structure are prepared on the inner wall of the trench. The device is then subjected to source region ion implantation, ohmic contact metallization, and chip edge gradient field limiting ring preparation. The electron blocking efficiency of the superlattice back barrier and the electric field equalization coefficient of the bottom shielding layer of the trench are used to jointly verify the process window of each process to obtain an appropriate process control scheme.

[0093] Precise control of four core process parameters is achieved by adjusting the adaptive process control thresholds, establishing a complete superlattice back barrier basic process. The back superlattice epitaxial rate directly determines the forming thickness of the superlattice monolayer film. Too high a rate will cause large fluctuations in film thickness, while too low a rate will prolong the growth time and introduce excess residual stress. Therefore, the control threshold defines a stable range for the rate, ensuring a uniform and consistent superlattice periodic stacking structure. The RF power for front trench etching controls the trench sidewall tilt angle and bottom fillet curvature. Power values ​​exceeding the upper limit of the threshold will cause excessively sharp bottom fillets, inducing local electric field concentration. Power values ​​below the lower limit of the threshold will result in insufficient etching depth. By locking the power range using the threshold, the optimal trench morphology can be maintained stably. The segmented dose of ion implantation at the bottom of the trench corresponds to the concentration distribution of the gradient doped shielding layer along the trench depth direction. Matching different doses at different depths can smooth the bottom electric field peak. The threshold constrains the fluctuation range of the implantation dose in each segment, avoiding doping concentration imbalance that weakens the shielding effect. The holding time of the shielding layer annealing step is used to control the degree of impurity activation. Insufficient holding time will prevent the implanted ions from being fully activated, while excessive holding time will cause the aluminum component to diffuse and deviate from the original structure of the superlattice. The segmented holding time of the step is set according to the threshold to balance the impurity activation efficiency and the stability of the superlattice structure. After all four parameters are calibrated according to the control threshold, they are combined to form a standardized superlattice back barrier process.

[0094] The complete device structure is fabricated based on the basic process steps, and two core performance indicators are introduced simultaneously to jointly verify the process windows of all processes, ultimately forming an adapted process control scheme. Following the established process steps, the passivated gate oxide layer and polysilicon gate structure are first fabricated on the inner wall of the trench. The passivated gate oxide layer is used to isolate the gate and channel charges and reduce the interface trap charge density, while the polysilicon gate ensures the controllability of the device's threshold voltage. Subsequently, source region ion implantation, ohmic contact metallization, and chip edge gradient field limiting ring fabrication are carried out sequentially. Source region ion implantation adjusts the device's on-resistance, ohmic contact metallization reduces signal transmission loss, and the gradient field limiting ring further distributes the high-voltage electric field at the device edge. The entire process covers all structural forming steps from the trench to the wafer edge. In the verification phase, two types of key performance indicators are used to complete the full process verification: the electron blocking efficiency of the superlattice back barrier is used to measure the ability of the back barrier structure to bind channel electrons and suppress off-state leakage current; the numerical fluctuation directly reflects whether the superlattice epitaxial rate and annealing time deviate from the standard range. The electric field equalization coefficient of the trench bottom shielding layer is used to evaluate the matching effect between the trench etching RF power and the segmented ion implantation dose. The higher the coefficient value, the smoother the electric field distribution at the bottom of the trench, and the lower the risk of breakdown. By traversing the performance change curves corresponding to each fabrication process, process ranges where both indicators cannot be met simultaneously are eliminated, and process windows that can stably maintain qualified electron blocking efficiency and electric field equalization coefficient are retained. All qualified process standards are integrated to form a complete adaptive process control scheme.

[0095] This approach starts with the core pre-process of superlattice growth trench etching to complete parameter constraints, and then combines it with the back-end processes such as gate fabrication metallization field limiting rings to perform overall performance verification. The two core performance parameters of electron blocking and electric field equalization are used to inversely constrain the entire process window, ensuring that the entire fabrication process can simultaneously achieve device performance with low leakage current and high withstand voltage.

[0096] The benchmark stacking unit with the smallest deviation in the back barrier superlattice process benchmark dataset is selected, and the trench morphology parameters corresponding to the benchmark stacking unit are extracted. The trench morphology parameters are then matched with the collaborative performance control database to obtain the appropriate process control threshold. The specific steps include:

[0097] If the current back-side superlattice epitaxial growth rate exceeds the epitaxial window corresponding to the adaptive control threshold, the gas supply rate of the MOCVD chamber will be adjusted to slow down or speed up the superlattice stacking growth rate.

[0098] If the current trench dry etching RF power exceeds the morphology window corresponding to the adaptation control threshold, the plasma RF output power is adjusted up or down to correct the rounded corner curvature at the bottom of the trench.

[0099] If the dose of a single segment of P-type ion implantation at the bottom of the trench is lower than the dose standard corresponding to the adaptive control threshold, the output intensity of the ion source will be increased segment by segment to supplement the doping concentration of the shielding layer.

[0100] If the current isothermal annealing time of each segment of the shielding layer does not reach the activation standard corresponding to the adaptation control threshold, the isothermal annealing time of the corresponding temperature range will be extended until the electric field balance coefficient of the bottom shielding layer and the electron blocking efficiency of the superlattice back barrier both reach the preset qualified standard.

[0101] In the back-barrier superlattice process benchmark dataset, the benchmark stacking cell with the smallest measured structural parameters and theoretical standard deviation is selected. The superlattice period thickness, aluminum composition, and residual stress of this type of cell are all in the optimal range, which can stably suppress the off-state leakage current of the device. The complete set of trench morphology parameters matching this cell is extracted and entered into the collaborative performance control database for data retrieval. Based on the electric field interface polarization performance law after the trench and superlattice are coupled, the database outputs the corresponding adaptation control thresholds for four types of processes: epitaxy, etching, ion implantation, and annealing. Each set of thresholds defines the safe range for the process parameters to fluctuate, which serves as the basis for judgment of real-time correction in subsequent processes.

[0102] The system collects operational parameters for four key processes in real time and compares them with control thresholds, performing targeted adjustments based on the specific circumstances. The first type is the back-side superlattice epitaxial growth rate. The growth rate directly determines the thickness of the superlattice monolayer film. Once the measured value exceeds the epitaxial window defined by the threshold, the system adjusts the rate by changing the supply rates of various gas sources within the MOCVD chamber. Increasing the gas supply accelerates atomic deposition, while decreasing it slows down the stacking growth rate, thus bringing the thickness of each superlattice layer back to the standard range and ensuring the electron confinement capability of the superlattice's back barrier. The second type is the trench dry etching RF power. RF power directly controls the plasma etching intensity. Power deviation from the threshold corresponding to the morphology window will change the curvature of the trench bottom fillet. Insufficient curvature can easily cause electric field concentration breakdown. The system precisely corrects the fillet curvature to the threshold range by adjusting the plasma RF output power up or down, evenly distributing the electric field at the bottom of the trench. The third category involves segmented P-type ion implantation dose at the bottom of the trench. When the single-segment implantation dose is lower than the threshold dose standard, insufficient doping concentration along the trench depth direction weakens the shielding electric field effect. The system segmentally increases the ion source output intensity and replenishes the doping concentration inside the shielding layer in layers to achieve a uniform charge shielding effect along the depth gradient. The fourth category involves the holding time of segmented isothermal annealing of the shielding layer. When the holding time in any temperature range does not reach the impurity activation standard corresponding to the threshold, the implanted P-type ions cannot be fully activated, and the conductivity of the shielding layer decreases. The system extends the isothermal holding time in the corresponding temperature range to promote uniform impurity activation.

[0103] All parameter adjustment operations will not stop individually. After each correction is completed, two core indicators will be checked simultaneously: the electric field balance coefficient of the bottom shielding layer of the trench and the electron blocking efficiency of the superlattice back barrier. The electric field balance coefficient is used to evaluate the effect of trench morphology and doping process on the distribution of local high voltage electric field, while the electron blocking efficiency is used to measure the ability of the superlattice stacked structure to block electron tunneling in the channel. The parameter correction process will only be terminated when both indicators reach the preset qualified standards simultaneously.

[0104] The entire mechanism achieves closed-loop dynamic control of multiple processes, including superlattice epitaxy, trench etching, ion implantation, and annealing. It uses the control threshold output by the database as a unified evaluation standard and matches exclusive correction methods for various process deviations. It activates the entire chain of synchronous constraints on the withstand voltage and leakage current performance of the device from the impurities in the formation of trenches during thin film growth, avoiding the performance degradation problem caused by the mismatch of parameters in one process but the parameters of another process being in compliance with the standard.

[0105] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure, characterized in that, The method includes the following specific steps: A back barrier superlattice process benchmark dataset was constructed by collecting superlattice single-layer thickness, composition gradient, number of periodic stacks, and in-situ growth stress values. The optimal back barrier benchmark stacking unit was calibrated in the back barrier superlattice process benchmark dataset based on device off-state buffer leakage current and back-side heat dissipation thermal resistance. Based on the etching parameters of trench depth, sidewall tilt angle, and bottom fillet curvature, a trench morphology process set is formed. The ultimate breakdown failure trench parameters in the trench morphology process set are marked as boundary control units. Combined with the optimal back barrier reference stacking unit and the boundary control unit, a synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology is generated. Based on the synergistic electrical correlation feature surface and the trench morphology process set, a target optimized trench unit is generated. Based on the target optimization of the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation law of trench unit, a collaborative performance control database of superlattice and trench is constructed. A suitable process control scheme is generated by combining the back barrier superlattice process benchmark dataset with the collaborative performance control database.

2. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 1, characterized in that, A back-barrier superlattice process benchmark dataset was constructed by collecting superlattice single-layer thickness, composition gradient, number of periodic stacks, and in-situ growth stress values. The optimal back-barrier benchmark stacking cells in the dataset were then calibrated based on device off-state buffer leakage current and back-side thermal resistance. The specific steps include: The epitaxial chamber growth temperature, V / III gas source ratio, and component doping flow rate of AlGaN barrier sublayer and GaN channel sublayer in the continuous alternating epitaxial growth of the substrate back side are collected to obtain the continuous alternating epitaxial growth data of the substrate back side. Based on the thickness of each layer of the wafer superlattice, the component gradient range, the total number of cycles, and the residual stress inside the thin film in the continuous alternating epitaxial growth data of the substrate back side, a back barrier superlattice process benchmark dataset is generated. A multi-dimensional screening scheme is generated by setting the upper limit threshold of the off-state buffer leakage current and the upper limit threshold of the back thermal resistance of the chip. Based on the historical stacking parameter combinations of the back barrier superlattice process benchmark dataset, the process parameter combinations that meet the multi-dimensional screening scheme are selected, and the superlattice stacking structure corresponding to the parameter combination is marked as the optimal back barrier benchmark stacking unit.

3. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 2, characterized in that, Based on the target optimization of the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation law of the trench unit, a collaborative performance control database for superlattice and trench is constructed, which specifically includes the following steps: The trench morphology process set is formed by collecting the trench depth, sidewall tilt angle, and bottom fillet curvature etching parameters. Based on the ultimate breakdown failure trench parameters in the trench morphology process set, the boundary reference cell is obtained. The device blocking voltage, gate oxide interface trap charge, and bottom electric field peak data corresponding to the optimal back barrier reference stack cell and the boundary reference cell are calculated to generate the synergistic electrical correlation feature surface between the superlattice back barrier and the trench morphology. The first target optimized trench cell is generated based on the synergistic electrical correlation feature surface and the trench morphology process set. Obtain the appropriate high-temperature operating conditions from the historical fabrication database of the same power level to form the second target optimized trench unit; A database for the coordinated performance management of superlattices and trenches is formed by integrating the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation patterns of the trench unit optimized by the first objective and the trench unit optimized by the second objective.

4. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 3, characterized in that, A collaborative performance management database for superlattices and trenches is formed by integrating the electric field dispersion coefficient, interface defect density, and superlattice polarization shielding efficiency variation patterns of the first and second objective optimized trench units. This specifically includes the following steps: Extract the bottom electric field peak, gate oxide interface trap charge density, and polarization electron blocking coefficient corresponding to the back barrier layer of the superlattice of different periods in the first target optimization trench unit, and construct the first cooperative performance feature subset; Extract the annealing activation uniformity, chip thermal resistance, and blocking leakage level of the matching gradient component superlattice back barrier layer in the second target optimization trench unit to construct the second cooperative performance feature subset. The first and second subsets of collaborative performance features are combined to form a collaborative performance management database that can be retrieved in real time and linked across processes.

5. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 4, characterized in that, The process involves calculating the device blocking voltage, gate oxide interface trap charge, and bottom electric field peak data corresponding to the optimal back barrier reference stack cell and boundary control cell to generate a synergistic electrical correlation feature surface between the superlattice back barrier and trench morphology. Based on the synergistic electrical correlation feature surface and the trench morphology process set, a first target optimized trench cell is generated. This process includes the following steps: The optimal back barrier reference stacking cell is matched with the trench structure of the trench morphology process to obtain the multi-physics joint relationship. The corresponding blocking withstand voltage value, total trap charge of the gate oxide interface, and peak electric field at the bottom corner of the trench are calculated in the multi-physics joint relationship to generate the first set of cooperative electrical parameter datasets. By matching the limit breakdown failure trench boundary reference cell with the optimal back barrier reference stacked cell of the same specification, a second set of cooperative electrical parameter datasets is obtained. Based on the numerical difference between the first set of collaborative electrical parameter datasets and the second set of collaborative electrical parameter datasets, a three-dimensional collaborative electrical correlation feature surface is generated by combining the number of superlattice periods, the curvature of the bottom fillet of the trench, and the leakage current and withstand voltage performance of the device. A preset threshold for the concentration suppression of the electric field at the bottom of the trench is set. The morphological parameters selected by the trench morphology process are matched with the cooperative electrical correlation feature surface to obtain the cooperative electrical correlation value. The trench units with the bottom electric field peak value lower than the suppression threshold in the cooperative electrical correlation value are marked as the first target optimized trench units.

6. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 5, characterized in that, A suitable process control scheme is generated by combining the back barrier superlattice process benchmark dataset and the collaborative performance control database, specifically including the following steps: Multi-gradient P-type ion segmented implantation is carried out according to the depth direction of the bottom of the trench, and the gradient doped shielding layer at the bottom of the trench is prepared by segmented isothermal activation annealing to obtain the back superlattice back barrier layer of the wafer. The actual composition and periodic parameters of the back superlattice back barrier layer of the wafer are monitored to obtain the back barrier superlattice process benchmark dataset. The benchmark stacking unit with the smallest deviation in the back barrier superlattice process benchmark dataset is selected, and the trench morphology parameters corresponding to the benchmark stacking unit are extracted. The trench morphology parameters are then matched with the collaborative performance control database to obtain the appropriate process control threshold. Generate an adaptive process control scheme based on the adaptive process control threshold.

7. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 6, characterized in that, Generate an adaptive process control plan based on the adaptive process control threshold, specifically including the following steps: The superlattice back barrier process is obtained by adjusting the back superlattice epitaxial rate, front trench etching RF power, trench bottom ion implantation segmented dose, and shielding layer annealing step holding time based on the adaptive process control threshold. Based on the superlattice back barrier process, a passivated gate oxide layer and a polysilicon gate structure are prepared on the inner wall of the trench. The device is then subjected to source region ion implantation, ohmic contact metallization, and chip edge gradient field limiting ring preparation. The electron blocking efficiency of the superlattice back barrier and the electric field equalization coefficient of the bottom shielding layer of the trench are used to jointly verify the process window of each process to obtain an appropriate process control scheme.

8. The method for fabricating a high-voltage GaNHEMT device with a superlattice back barrier structure according to claim 7, characterized in that, The benchmark stacking unit with the smallest deviation in the back barrier superlattice process benchmark dataset is selected, and the trench morphology parameters corresponding to the benchmark stacking unit are extracted. The trench morphology parameters are then matched with the collaborative performance control database to obtain the appropriate process control threshold. The specific steps include: If the current back-side superlattice epitaxial growth rate exceeds the epitaxial window corresponding to the adaptive control threshold, the gas supply rate of the MOCVD chamber will be adjusted to slow down or speed up the superlattice stacking growth rate. If the current trench dry etching RF power exceeds the morphology window corresponding to the adaptation control threshold, the plasma RF output power is adjusted up or down to correct the rounded corner curvature at the bottom of the trench. If the dose of a single segment of P-type ion implantation at the bottom of the trench is lower than the dose standard corresponding to the adaptive control threshold, the output intensity of the ion source will be increased segment by segment to supplement the doping concentration of the shielding layer. If the current isothermal annealing time of each segment of the shielding layer does not reach the activation standard corresponding to the adaptation control threshold, the isothermal annealing time of the corresponding temperature range will be extended until the electric field balance coefficient of the bottom shielding layer and the electron blocking efficiency of the superlattice back barrier both reach the preset qualified standard.

Images