A high-density insulating structure based on discrete gradient stress layers and a method of manufacturing the same

Abstract

The application relates to a high-density insulation structure based on a discrete gradient stress layer and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate formed with a groove structure, and preparing a shielding gate structure in the groove structure; adopting a high-density plasma chemical vapor deposition process to deposit a lower dielectric layer in a compressive stress state above the shielding gate structure; forming a fuzzy transition interface with continuously and gradually changed composition and stress above the lower dielectric layer by switching reaction gas; depositing an upper dielectric layer in a tensile stress state by switching gas again, and performing annealing treatment after the deposition is completed. The method can simultaneously improve the three indexes of time breakdown life, plasma damage and crack which are mutually contradictory in the past, significantly reduce cavities, and additionally realize low dielectric constant optimization or reflow planarization.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high-density insulating structure based on a discrete gradient stress layer and its fabrication method. Background Technology

[0002] The inter-gate dielectric layer of shielded gate trench power devices is typically formed using high-density plasma chemical vapor deposition (PDCVD). With each generation of device upgrades, the aspect ratio of the trenches continuously increases, and the filling quality and long-term reliability of the inter-gate insulating layer have gradually become the core bottlenecks restricting device performance and mass production yield.

[0003] In existing technologies, a single-layer constant-stress silicon oxide high-density plasma deposition process is commonly used to form the aforementioned insulating layer. For devices with relatively low aspect ratios, this single-layer process can barely meet the requirements for voids, cracks, and breakdown lifetime over time. However, when the same single-layer process is applied to next-generation high aspect ratio devices, several defects become apparent: First, deep trenches and sharp corners are difficult to fill, easily forming voids and leading to excessive gate leakage current; second, as the insulating layer thickens, stress accumulates continuously within the thick film, making it prone to cracking after deposition and even during subsequent high-temperature processes, potentially leading to crack propagation and device failure; third, plasma damage causes threshold voltage drift, resulting in poor parameter consistency across batches of devices; fourth, the long-term use of pure silicon oxide leads to a higher dielectric constant and greater resistance and capacitance delays, limiting further improvements in device switching speed. Even more challenging is that these performance indicators are mutually restrictive, making simultaneous optimization through a single process parameter difficult. For example, increasing the source power to increase film density and extend breakdown lifetime increases the internal stress, which exacerbates cracking; conversely, decreasing the bias voltage to mitigate plasma damage reduces film density and shortens breakdown lifetime. The requirements for density, stress, and damage are often contradictory. Summary of the Invention

[0004] Therefore, it is necessary to provide a high-density insulation structure based on discrete gradient stress layer and its preparation method to address the above-mentioned technical problems.

[0005] In a first aspect, this application discloses a method for fabricating a high-density insulating structure based on a discrete gradient stress layer, the method comprising the following steps:

[0006] A semiconductor substrate having a trench structure is provided, and a shielding gate structure is fabricated within the trench structure.

[0007] A lower dielectric layer under compressive stress is deposited above the shielding gate structure using a high-density plasma chemical vapor deposition process.

[0008] By switching the reactive gas above the lower dielectric layer, a fuzzy transition interface with continuously and gradually changing composition and stress is formed;

[0009] The gas deposition process is switched again to form an upper dielectric layer under tensile stress. After deposition, annealing is performed.

[0010] Furthermore, before depositing a lower dielectric layer under compressive stress above the shielding gate structure using a high-density plasma chemical vapor deposition process, the following steps are also included:

[0011] A silicon-rich silicon oxide pad layer is deposited on the surface of the shielding grid structure without applying a bias voltage during the deposition of the silicon-rich silicon oxide pad layer.

[0012] Furthermore, the fuzzy transition interface has a two-layer or one-layer structure, and the fuzzy transition interface is formed between dielectric layers.

[0013] On the other hand, this application also discloses a high-density insulation structure based on a discrete gradient stress layer, comprising:

[0014] A shielding gate structure located within a trench in a semiconductor substrate;

[0015] A discrete gradient stress dielectric layer formed above the shielding gate structure;

[0016] The discrete gradient stress dielectric layer includes at least two silicon oxide dielectric layers stacked sequentially from bottom to top, each formed by high-density plasma chemical vapor deposition. The bottommost dielectric layer is under compressive stress, and the topmost dielectric layer is under tensile stress. Adjacent dielectric layers form a fuzzy transition interface where the composition and stress change continuously and gradually along the thickness direction by switching reactive gases.

[0017] Furthermore, a silicon-rich silicon oxide pad layer is provided between the shielding gate structure and the discrete gradient stress dielectric layer, and the silicon-rich silicon oxide pad layer covers the top of the shielding gate structure.

[0018] Furthermore, the silicon-rich silicon oxide pad layer has a silicon-to-oxygen ratio greater than the stoichiometric ratio of silicon oxide and is in a compressive stress state, and the silicon-rich silicon oxide pad layer is a chemically deposited layer formed without applying bias voltage.

[0019] Furthermore, the discrete gradient stress dielectric layer is a three-layer structure consisting of a bottom dielectric layer, a middle dielectric layer, and a top dielectric layer stacked sequentially from bottom to top. A fuzzy transition interface is formed between the bottom dielectric layer and the middle dielectric layer, and between the middle dielectric layer and the top dielectric layer.

[0020] Furthermore, the bottom dielectric layer is silicon-rich silicon oxide, with a silicon-to-oxygen ratio greater than that of stoichiometric silicon oxide and is in a compressive stress state.

[0021] Furthermore, the middle dielectric layer is stoichiometric silicon oxide and is in a near-zero stress state, and the middle dielectric layer constitutes a barrier layer that prevents doped atoms in the top dielectric layer from diffusing into the shielding gate structure.

[0022] Furthermore, the top dielectric layer is in a state of tensile stress and is any one of oxygen-rich silicon oxide, fluorine-doped silicon oxide, and phosphorus-doped silicon oxide.

[0023] Furthermore, the discrete gradient stress dielectric layer has a two-layer structure, including a bottom doped silicon oxide in a compressive stress state and a top doped silicon oxide in a tensile stress state, and the fuzzy transition interface is formed between the bottom doped silicon oxide and the top doped silicon oxide by switching reactive gases.

[0024] The aforementioned high-density insulation structure and its fabrication method based on discrete gradient stress layers achieve the following beneficial effects: 1. The silicon-rich silicon oxide liner layer and the homogeneously deposited multilayer silicon oxide form a structure without obvious heterogeneous interfaces, and the interface defect density is far superior to that of traditional processes. Through the discrete gradient design of high-pressure stress in the bottom layer, near-zero stress in the middle layer, and moderate tensile stress in the top layer, the stress is released gradually in layers; the high-density high-pressure stress in the bottom layer optimizes breakdown over time, the stress buffer in the middle layer reduces cracks, and the tensile stress in the top layer reduces plasma damage. The three major reliability indicators are simultaneously improved by 50% to 99%, solving the contradiction that traditional single-stress processes cannot achieve simultaneously.

[0025] 2. The top layer can be made of various materials such as pure silicon oxide, fluorine-doped silicon oxide, and phosphorus-doped silicon oxide, respectively adaptable to different application scenarios such as general purpose, low k, and reflow planarization, covering all mainstream requirements of power devices. It effectively reduces resistance and capacitance delay, improves device switching speed, and is suitable for high-frequency applications. The phosphorus-doped top layer solution has reflow planarization characteristics, significantly improving surface flatness, while the middle layer thickness effectively blocks phosphorus diffusion, ensuring stable interface performance, making it suitable for high-current power devices.

[0026] 3. This process uses high-density plasma chemical vapor deposition for homogeneous deposition. The interlayer is naturally formed by gas switching, which eliminates the need for new equipment and is easy to implement in existing production lines. Furthermore, it significantly reduces the void ratio and crack ratio, greatly improves parameter consistency, and significantly reduces production costs. Attached Figure Description

[0027] Figure 1 This is a schematic flowchart of a method for fabricating a high-density insulation structure based on a discrete gradient stress layer in one embodiment;

[0028] Figure 2 This is a schematic diagram of a high-density insulation structure based on a discrete gradient stress layer in one embodiment;

[0029] Figure 3 This is a schematic diagram of a second type of high-density insulation structure based on a discrete gradient stress layer in one embodiment;

[0030] Figure 4 This is a schematic diagram of a third type of high-density insulation structure based on a discrete gradient stress layer in one embodiment;

[0031] Figure 5 This is a schematic diagram of the fourth type of high-density insulation structure based on discrete gradient stress layer in one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] In one embodiment, such as Figure 1 As shown, a method for fabricating a high-density insulation structure based on a discrete gradient stress layer is disclosed, the method comprising the following steps:

[0034] S1: A semiconductor substrate having a trench structure is provided, and a shielding gate structure is fabricated within the trench structure;

[0035] S2: A lower dielectric layer under compressive stress is deposited above the shielding gate structure using a high-density plasma chemical vapor deposition process.

[0036] S3: By switching the reactive gas above the lower dielectric layer, a fuzzy transition interface with continuously and gradually changing composition and stress is formed;

[0037] S4: Switch to gas deposition again to form an upper dielectric layer under tensile stress. After deposition, perform annealing.

[0038] This embodiment presents a method for fabricating the aforementioned insulating structure. The entire process is completed continuously in the same high-density plasma chemical vapor deposition (PDCVD) equipment, requiring no additional equipment and easily integrated into existing mass production lines. Specifically, the wafer with the pre-formed shielding gate structure is first fed into the equipment for pretreatment. Then, a lower dielectric layer under compressive stress is deposited above the shielding gate structure. Next, without stopping the machine or removing the wafer, only the reactive gas is switched to cultivate a blurred transition interface with gradually changing composition and stress on the lower dielectric layer, and a higher dielectric layer under tensile stress is deposited accordingly. Finally, the entire wafer is annealed to stabilize the stress within the film and repair any defects left during deposition. This embodiment uses a continuous process to blur the interlayer interfaces, avoiding contamination and heterogeneous interfaces caused by downtime during transfer. The process is consistent and highly efficient.

[0039] In this embodiment, the pre-processing steps of the fabrication method are first refined. Before the wafer enters the equipment, it undergoes a standard cleaning process to remove organic contaminants, particle residues, and the natural oxide layer from the surface. It is then dried and baked to thoroughly remove moisture, ensuring a clean and dry surface. Following this, a vacuum is applied for deposition. Before the formal deposition of the lower dielectric layer, a silicon-rich silicon oxide backing layer can be added to the surface of the shielding gate structure. This layer is deposited without bias voltage, relying solely on chemical reaction to form the film, thus preventing high-energy ions from impacting the lower gate oxide layer. After the backing layer is completed, the wafer is not removed but directly proceeds to the next layer deposition to maintain process continuity.

[0040] In this embodiment, a three-layer continuous deposition process is included. After the backing layer is completed, without moving the wafer, the gas and power are adjusted to deposit a silicon-rich lower dielectric layer. A slightly silicon-rich gas ratio and strong deposition conditions are used to make this layer dense and with sufficient compressive stress. Simultaneously, strong ion bombardment improves the coverage of the high aspect ratio trench sidewalls, suppressing voids. Then, a gas-cutting process is initiated: the silicon and oxygen sources are shut off, a carrier gas is used for purging, and the gas required for standard silicon oxide is introduced and stabilized for a short time, naturally forming a blurred transition interface. Next, a near-zero stress intermediate dielectric layer is deposited, making it the thickest possible layer to buffer the stress at both ends and filter out some upward-propagating defects. The same gas-cutting process is repeated above the intermediate layer to form a second blurred interface, preparing for the top layer. The entire process results in three homogeneous layers with blurred interfaces, stress transitioning from compressive to zero and then to tensile stress in a step-by-step manner, keeping defects and cracks at a very low level.

[0041] In this embodiment, a common preparation scheme of oxygen-enriched silicon oxide is used for the top layer. After the second fuzzy interface is formed above the middle layer, the ratio of silicon-oxygen gas is adjusted to the oxygen-enriched side, and the source power and bias voltage are reduced accordingly to deposit an oxygen-enriched silicon oxide top layer with moderate tensile stress. The lower energy achieves tensile stress and reduces the impact of plasma on the underlying gate oxide layer. After the top layer is deposited, it is annealed in place in a nitrogen atmosphere containing a small amount of hydrogen. The hydrogen is used to reduce dangling bonds in the film and repair defects. This step does not involve the addition of any extra elements, making the process the simplest and lowest cost.

[0042] In this embodiment, a fluorine-doped silicon oxide layer is used for the top layer, employing a low dielectric constant scheme for high-frequency devices. The pretreatment process is the same as the oxygen-enriched scheme, except that a fluorine-containing gas is additionally introduced into the reaction gas during top layer deposition. This introduces an appropriate amount of fluorine into the film, significantly lowering the dielectric constant of the top layer, resulting in a decrease in resistance, capacitance, and delay, thus improving the switching speed of the device. The fluorine-doped film also boasts strong filling capacity and good step coverage, which is beneficial for filling high aspect ratio trenches. It is important to note that fluorine is prone to leaching at high temperatures; therefore, the annealing process for this scheme requires different arrangements: the temperature is lower than in the oxygen-enriched scheme, and the atmosphere is changed to pure nitrogen without hydrogen doping to prevent fluorine from escaping and negatively impacting the dielectric constant and reliability. It is precisely this low-temperature, pure nitrogen annealing process that effectively retains the low dielectric constant advantage of the fluorine-doped top layer.

[0043] In this embodiment, a phosphorus-doped silicon oxide reflow planarization scheme is used for the top layer, targeting high-current devices. Similarly, a phosphorus-containing gas is introduced into the reaction gas during the deposition of the top layer to incorporate an appropriate amount of phosphorus into the film. Phosphorus-doped silicon oxide can be reflowed at high temperatures, making the surface smoother and improving the yield of subsequent photolithography and etching. Furthermore, phosphorus can absorb metallic impurities from the film, enhancing reliability. This scheme places an additional requirement on the intermediate dielectric layer: the thickness of the intermediate layer cannot be too thin; it must be sufficient to prevent phosphorus from diffusing downwards. Otherwise, if phosphorus reaches the shielding gate interface, it will damage the electrical properties of the interface. Specifically, the intermediate layer is thickened. Actual measurements show that phosphorus is essentially stopped halfway down, diffusing only shallowly, thus preserving the shielding gate interface. The annealing of the top layer is similar to the oxygen-enriched scheme, using a nitrogen-hydrogen mixed atmosphere to repair defects.

[0044] In this embodiment, a simplified two-layer fabrication scheme is used for products with cost sensitivity and moderate performance requirements. The process is shorter than the three-layer scheme: after pretreatment and the padding layer is completed as needed, the lower doped silicon oxide under compressive stress is directly deposited, followed by gas cutting to form a blurred transition interface, and then the upper doped silicon oxide under tensile stress is deposited. No near-zero stress intermediate layer is inserted in between, and finally, annealing is performed as usual. With one less layer, the deposition steps and cycle time are reduced, resulting in lower costs and faster production, while still retaining the gradient stress framework of low pressure and high tension, significantly outperforming traditional single-layer processes. The two-layer scheme also offers flexible material selection: for low dielectric constant, both layers can be doped with fluorine; for planarization, both layers can be doped with phosphorus. The core benefits of gradient stress are achieved with minimal steps, making it very cost-effective for low- to mid-range products.

[0045] In this embodiment, as Figures 2-4 As shown, a gradient stress high-density plasma chemical vapor deposition insulating structure is presented, primarily used as the inter-gate dielectric layer for shielding gate trench power devices. Among them, Figure 2 It is a standard plasma chemical vapor deposition insulating structure. Figure 3 For low-k optimized ionization chemical vapor deposition insulating structures, Figure 4 For ionization chemical vapor deposition insulation structure with reflow planarization; Figure 2 The standard plasma chemical vapor deposition insulation structure differs from the other three in that it is completely undoped, achieving its goal solely through undoped technology. Figure 4 Reflux planarization structure and front Figure 2 and Figure 3 The difference lies in the difference in phosphorus doping, and Figure 2 , Figure 3 and Figure 4 The difference lies in the fact that the reaction sources and reaction paths of the process technology for achieving tensile stress / fuzzy interface / near-zero stress / fuzzy interface / compressive stress laminated structures are completely different, and the technical effects achieved can be proportioned and adjusted according to actual needs.

[0046] like Figures 2-4Viewed from bottom to top, the bottom two layers are a substrate 1 and a shielding dielectric layer 2. Substrate 1 is made of silicon, and shielding dielectric layer 2 is made of silicon nitride. A shielding gate structure 3 is first formed within the trenches of the semiconductor substrate. Above the shielding gate structure 3 is a discrete gradient stress dielectric layer 5, and on top of the discrete gradient stress dielectric layer 5 is a control gate structure layer 6. Silicon-rich silicon oxide is deposited between the shielding gate structure 3 and the discrete gradient stress dielectric layer 5. The discrete gradient stress dielectric layer 5 is composed of several layers of silicon oxide stacked together, all homogeneously deposited in the same high-density plasma chemical vapor deposition (PDCVD) system. The bottommost layer is intentionally designed under compressive stress, while the topmost layer is designed under tensile stress, with the stress gradually transitioning from compressive to tensile along the film thickness direction. Between adjacent layers, only the reactive gas is switched without interrupting deposition, allowing the composition and stress to change gradually at the interface, thus forming a blurred transition interface rather than an abrupt physical heterogeneous interface. This arrangement of low-pressure top tension and blurred interface allows for the simultaneous consideration of several previously mutually restrictive indicators, such as time-induced breakdown, plasma damage, and thin film cracking, which is precisely what single-stress thin films struggle to achieve.

[0047] Continue to refer to Figure 2 As shown, in this embodiment, a silicon-rich silicon oxide backing layer 4 is added between the shielding gate structure 3 and the discrete gradient stress dielectric layer 5. This backing layer extends along the top of the shielding gate structure 3, completely covering the polysilicon shielding gate, and then the discrete gradient stress dielectric layer 5 is deposited on top of it. Since the interface between the shielding gate and the silicon oxide is often the first point of failure after time-induced breakdown, this thin layer of silicon-rich silicon oxide is added as a transition. With this backing layer, the defects at the interface are significantly reduced, the gate leakage current decreases, and the time-induced breakdown lifetime is further improved.

[0048] This embodiment further defines the composition and deposition method of the silicon-rich silicon oxide backing layer 4. The silicon content of this backing layer is higher than the stoichiometric silicon oxide, meaning the silicon-to-oxygen ratio is biased towards the silicon-rich side. Therefore, the film itself is relatively dense and has considerable compressive stress. During the deposition of this film, no bias voltage is applied; pure chemical deposition is used to avoid high-energy ion bombardment damaging the underlying gate oxide layer. In this way, the dense structure resulting from the silicon richness passivates the dangling bonds on the shielding gate surface, reduces the interface state density, and decreases gate leakage current. Furthermore, its own compressive stress can offset some of the tensile stress accumulated in subsequent layers, effectively providing a stress margin for the entire film stack. In this embodiment, this dense silicon-rich silicon oxide layer also serves as the nucleation substrate for the upper dielectric layer, making the upper film more uniform and reducing initial defects during initial growth, thus contributing to the overall quality of the stacked films.

[0049] like Figures 2-4The high-density plasma chemical vapor deposition insulating structure shown in this embodiment presents a preferred form of the discrete gradient stress dielectric layer 5, namely a three-layer structure. From bottom to top, it consists of a bottom dielectric layer, a middle dielectric layer, and a top dielectric layer. The thickness of the three layers is not evenly distributed; the middle layer is the thickest, while the bottom and top layers are roughly equal, resulting in an overall distribution that is thinner at both ends and thicker in the middle. Specifically, the discrete gradient stress dielectric layer 5 is a three-layer structure consisting of a bottom dielectric layer 501, a middle dielectric layer 503, and a top dielectric layer 505 stacked sequentially from bottom to top. A first fuzzy transition interface 502 is formed between the bottom dielectric layer and the middle dielectric layer, and a second fuzzy transition interface 504 is formed between the middle dielectric layer and the top dielectric layer. The middle layer is made the largest because it bears the primary responsibility for stress buffering and needs sufficient volume to smoothly transition the compressive stress of the bottom layer and the tensile stress of the top layer. The bottom and top layers each guard one end, respectively responsible for optimizing the breakdown over time and plasma damage on both sides. Attempts to make the three layers nearly identical resulted in insufficient buffer margin, leading to a steep transition of stress along the thickness of the membrane, and no significant improvement in crack formation. Only after thickening the middle layer to significantly exceed the thicknesses at both ends did the stress transition become truly smooth, and the number of cracks decreased substantially. As for the total thickness, it can be adjusted within a certain range according to the actual requirements of the device for the insulating layer, and this distribution of thinner ends and thicker middle is always a more reliable choice among three-layer solutions.

[0050] In this embodiment, the bottom dielectric layer of the three-layer structure will be further described. The bottom layer sits directly on the pad layer and is made of silicon-rich silicon oxide with a silicon-to-oxygen ratio biased towards the silicon-rich side. The entire layer is under significant compressive stress. By making the bottom layer silicon-rich and under compressive stress, the silicon richness makes the film denser, reduces defects, compresses leakage paths, and thus significantly extends the breakdown life over time. The compressive stress acts like a protective pad for the gate oxide layer below, offsetting the tensile stress that may arise in subsequent processes and reducing plasma damage to the gate oxide layer. This restraint in using sufficient compressive stress only on the bottom layer achieves the benefits of density and breakdown resistance without introducing the risk of cracking.

[0051] This embodiment illustrates the middle dielectric layer in a three-layer structure. The middle layer is the thickest layer in the entire film stack, using standard silicon dioxide with a near-stoichiometric ratio. Through process adjustments, it is brought to a near-zero stress state, adding almost no burden to the overall stress account. Its primary function is stress buffering, smoothly connecting the compressive stress of the bottom layer with the tensile stress of the top layer, preventing abrupt stress changes at the layer boundaries that could tear the film. Simultaneously, this thick film can also intercept some of the defects propagating upwards from the bottom layer, reducing the number of defects ultimately reaching the top layer. Another function of the middle layer is particularly crucial when the top layer contains phosphorus: it acts as a barrier layer against the downward diffusion of phosphorus atoms. Phosphorus tends to diffuse downwards at high temperatures; once it reaches the shielding gate interface, it increases interface impurities and degrades device performance. By making the middle layer sufficiently thick, phosphorus is essentially blocked halfway, diffusing only shallowly downwards, thus maintaining the electrical stability of the shielding gate interface.

[0052] This embodiment focuses on the top dielectric layer in a three-layer structure. The top layer, located at the very top of the stacked film and adjacent to the subsequent control gate structure, is designed with moderate tensile stress. Moderate tensile stress is chosen because it mitigates the impact of plasma on the gate oxide layer during deposition, suppressing threshold voltage drift and ensuring greater parameter consistency across devices in the same batch. The material of the top layer is not unique; it can be chosen from oxygen-rich silicon oxide, fluorine-doped silicon oxide, and phosphorus-doped silicon oxide depending on the application: oxygen-rich silicon oxide is used for general applications due to its simplest process and lowest cost; fluorine-doped silicon oxide is used for applications requiring high switching speeds, as it lowers the dielectric constant and reduces resistance-capacitance delay; and phosphorus-doped silicon oxide is chosen for high-current devices where surface flatness is crucial, allowing for surface smoothing through high-temperature reflow. Regardless of the choice, the tensile stress properties of the top layer and its fundamental responsibility to optimize plasma damage remain unchanged; only additional functions are added on top of these.

[0053] This embodiment focuses on illustrating the fuzzy transition interface between dielectric layers. In conventional multilayer films, the layers are separated by a clear physical interface, with composition and stress abruptly changing at the interface. This results in a high density of interface defects, which are precisely the weak points prone to time-induced breakdown and cracking. In this embodiment, several layers are continuously deposited in the same device in one go, with transitions between layers achieved only by switching reactive gases. This naturally creates a transition zone at the interface where composition and stress change gradually, rather than a steep interface. During the switching process, the silicon and oxygen sources are first shut off, and the residual gas in the chamber is purged with carrier gas before the gas required for the next layer is introduced, stabilized, and then deposition continues. Although the entire process is short, it is sufficient to cultivate a fuzzy interface of moderate thickness, significantly thinner than the functional layers, and the stress difference between the preceding and following layers is also minimized. This interface defect density is far lower than that of traditional heterogeneous interfaces, effectively preventing time-induced breakdown and mitigating the risk of cracking due to the gradual stress transition—a double benefit.

[0054] In other embodiments, considering that not all products pursue ultimate performance, such as Figure 5 As shown, this embodiment presents a simplified two-layer structure for use in cost-sensitive or moderately performance-critical applications. In this case, the discrete gradient stress dielectric layer 5 retains only the bottom and top layers: the bottom layer is compressive stress-doped silicon oxide 5001, and the top layer is tensile stress-doped silicon oxide 5003. A blurred transition interface 5002 is formed between the two layers by switching reactant gases, but a middle layer is no longer inserted. Specifically, the two-layer scheme simplifies the deposition process to two steps, resulting in faster cycle time and lower cost, while still preserving the gradient stress of the bottom pressure and top tension. The performance is significantly better than the traditional single-stress single-layer process. This structure offers considerable flexibility in material selection: if a low dielectric constant is desired, both the top and bottom layers can be fluorine-doped silicon oxide; if planarization is prioritized, both layers can be phosphorus-doped silicon oxide. In this way, the reliability provided by gradient stress can be achieved with minimal processing steps.

[0055] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a high-density insulating structure based on a discrete gradient stress layer, characterized in that, Includes the following steps: A semiconductor substrate having a trench structure is provided, and a shielding gate structure is fabricated within the trench structure. A lower dielectric layer under compressive stress is deposited above the shielding gate structure using a high-density plasma chemical vapor deposition process. By switching the reactive gas above the lower dielectric layer, a fuzzy transition interface with continuously and gradually changing composition and stress is formed; The gas deposition process is switched again to form an upper dielectric layer under tensile stress. After deposition, annealing is performed.

2. The method for fabricating a high-density insulating structure based on a discrete gradient stress layer according to claim 1, characterized in that, Before depositing a lower dielectric layer under compressive stress above the shielding gate structure using a high-density plasma chemical vapor deposition process, the following steps are also included: A silicon-rich silicon oxide pad layer is deposited on the surface of the shielding grid structure without applying a bias voltage during the deposition of the silicon-rich silicon oxide pad layer.

3. The method for fabricating a high-density insulating structure based on a discrete gradient stress layer according to claim 1, characterized in that, The fuzzy transition interface has a two-layer or one-layer structure, and the fuzzy transition interface is formed between dielectric layers.

4. A high-density insulation structure based on a discrete gradient stress layer, characterized in that, include: A shielding gate structure located within a trench in a semiconductor substrate; A discrete gradient stress dielectric layer formed above the shielding gate structure; The discrete gradient stress dielectric layer includes at least two silicon oxide dielectric layers stacked sequentially from bottom to top, each formed by high-density plasma chemical vapor deposition. The bottommost dielectric layer is under compressive stress, and the topmost dielectric layer is under tensile stress. Adjacent dielectric layers form a fuzzy transition interface where the composition and stress change continuously and gradually along the thickness direction by switching reactive gases.

5. The high-density insulation structure based on a discrete gradient stress layer according to claim 4, characterized in that, A silicon-rich silicon oxide pad layer is further provided between the shielding grid structure and the discrete gradient stress dielectric layer, and the silicon-rich silicon oxide pad layer covers the top of the shielding grid structure.

6. The high-density insulation structure based on a discrete gradient stress layer according to claim 5, characterized in that, The silicon-rich silicon oxide pad layer has a silicon-to-oxygen ratio greater than the stoichiometric ratio of silicon oxide and is under compressive stress. The silicon-rich silicon oxide pad layer is a chemically deposited layer formed without applying bias voltage.

7. The high-density insulation structure based on a discrete gradient stress layer according to claim 4, characterized in that, The discrete gradient stress dielectric layer is a three-layer structure consisting of a bottom dielectric layer, a middle dielectric layer, and a top dielectric layer stacked sequentially from bottom to top. A fuzzy transition interface is formed between the bottom dielectric layer and the middle dielectric layer, and between the middle dielectric layer and the top dielectric layer.

8. The high-density insulation structure based on a discrete gradient stress layer according to claim 7, characterized in that, The bottom dielectric layer is silicon-rich silicon oxide, with a silicon-to-oxygen ratio greater than that of stoichiometric silicon oxide and is in a compressive stress state.

9. The high-density insulation structure based on a discrete gradient stress layer according to claim 7, characterized in that, The middle dielectric layer is stoichiometric silicon oxide and is in a near-zero stress state. The middle dielectric layer also forms a barrier layer that prevents doped atoms in the top dielectric layer from diffusing into the shielding gate structure.

10. The high-density insulation structure based on a discrete gradient stress layer according to claim 7, characterized in that, The top dielectric layer is under tensile stress and is any one of oxygen-rich silicon oxide, fluorine-doped silicon oxide, and phosphorus-doped silicon oxide.

11. The high-density insulation structure based on a discrete gradient stress layer according to claim 4, characterized in that, The discrete gradient stress dielectric layer has a two-layer structure, including a bottom doped silicon oxide in a compressive stress state and a top doped silicon oxide in a tensile stress state. The fuzzy transition interface is formed between the bottom doped silicon oxide and the top doped silicon oxide by switching reactive gases.

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