Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle
Patent Information
- Application Number
- CN202611188967.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-06
- Publication Date
- 2026-10-27
Smart Images
Figure CN122995183A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Technology
[0002] Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) made of third-generation wide-bandgap semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) possess characteristics such as large critical breakdown electric field strength, high thermal conductivity, large bandgap width, and high electron saturation drift velocity. These characteristics have made SiC or GaN a research hotspot for power semiconductor devices. In high-power applications such as high-speed rail, hybrid electric vehicles, and intelligent high-voltage direct current transmission, SiC devices are highly anticipated.
[0003] In the fabrication process of superjunction silicon carbide MOSFETs, the alternating doped columnar structures require multiple ion implantations to form. However, existing manufacturing processes require additional photomasks for multiple ion implantations, leading to a significant increase in overlay misalignment.
[0004] Application content This application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle to effectively improve overlay deviation and simplify the manufacturing process.
[0005] In a first aspect, a method for manufacturing a semiconductor device is provided, comprising: A semiconductor body is provided; the semiconductor body is configured with a first conductivity type and includes a transition surface and a second surface disposed opposite to each other; The operation of forming a well region in a portion of the transition surface and forming an epitaxial layer on the transition surface is repeated at least twice using a self-aligned process to form at least two stacked well regions to form a doped pillar region; wherein the well region is configured with a second conductivity type; the second conductivity type is different from the first conductivity type; the semiconductor body includes a first surface opposite to the second surface; A body region, a source region, and a first region are formed on the first surface; wherein the source region is configured with the first conductivity type, the first region is configured with the second conductivity type, and both are located on the first surface; the body region is configured with the second conductivity type, located on the side of the source region away from the first surface, and is in contact with the doped pillar region; A gate is formed on the first surface, and a dielectric layer is formed on the side of the gate away from the first surface; the dielectric layer encapsulates the gate. A source electrode is formed on the side of the dielectric layer away from the first surface; the source electrode penetrates the dielectric layer and contacts the source region and the first region, respectively; A drain electrode is formed on the second surface.
[0006] Optionally, the transition surface includes at least a first transition surface and a second transition surface; the at least two well regions include a first well region and a second well region; the epitaxial layer includes at least a first epitaxial layer and a second epitaxial layer. The repeated execution of the self-aligned process at least twice to form a well region in a portion of the transition surface and to form an epitaxial layer on the transition surface includes: A first sidewall structure is formed on the first transition surface, and the first well region is formed in the semiconductor body by ion implantation using a first self-aligned process; and a first epitaxial layer is formed on the first transition surface; wherein the first epitaxial layer includes a second transition surface opposite to the second surface; A second sidewall structure is formed on the second transition surface, and a second self-aligned process is used to perform ion implantation on the second transition surface to form the second well region in the semiconductor body; and a second epitaxial layer is formed on the second transition surface; wherein the second epitaxial layer includes the first surface opposite to the second surface.
[0007] Optionally, the step of forming the first sidewall structure on the first transition surface, employing a first self-aligned process to perform ion implantation on the first transition surface to form the first well region in the semiconductor body; and forming the first epitaxial layer on the first transition surface includes: A first mask layer is formed on the first transition surface; the first mask layer is provided with a first opening, the first opening exposing a portion of the first transition surface; A first oxide layer covering the first opening is formed on the side of the first mask layer away from the first transition surface, and the first oxide layer is etched to form a first sidewall structure; the first sidewall structures have a first spacing between them; Ion implantation is performed on the first transition surface to form the first well region in the semiconductor body; Remove the first sidewall structure and the first mask layer, and form the first epitaxial layer on the first transition surface; The process of forming the second sidewall structure on the second transition surface, employing a second self-aligned process, involves ion implantation of the second transition surface to form the second well region in the semiconductor body; and forming the second epitaxial layer on the second transition surface, including: A second mask layer is formed on the second transition surface; the second mask layer is provided with a second opening, the second opening exposing a portion of the second transition surface; A second oxide layer covering the second opening is formed on the side of the second mask layer away from the second transition surface, and the second oxide layer is etched to form a second sidewall structure; the second sidewall structures have a second spacing between them; Ion implantation is performed on the second transition surface to form the second well region in the semiconductor body; Remove the second sidewall structure and the second mask layer, and form the second epitaxial layer on the second transition surface.
[0008] Optionally, forming a trap region in a portion of the transition surface includes: A first well region with a first width is formed on the first transition surface, and a second well region with a second width is formed on the second transition surface; Wherein, in the thickness direction perpendicular to the semiconductor body, the second width is equal to the first width; the second spacing is equal to the first spacing; or, in the thickness direction perpendicular to the semiconductor body, the second width is greater than the first width; the second spacing is greater than the first spacing.
[0009] Optionally, forming a trap region in a portion of the transition surface includes: A first well region with a first ion concentration is formed on the first transition surface, and a second well region with a second ion concentration is formed on the second transition surface; Wherein, the second ion concentration is equal to the first ion concentration.
[0010] In a second aspect, a semiconductor device is provided, comprising: A semiconductor body, configured for a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a body region, a source region, a first region, and a doped pillar region; the source region is configured for the first conductivity type, the first region is configured for a second conductivity type, and both are located on the first surface; the body region is configured for the second conductivity type, located on the side of the source region away from the first surface, and is in contact with the doped pillar region; the doped pillar region includes at least two stacked well regions, and the well regions are configured for the second conductivity type; The gate is located on the first surface; A dielectric layer is located on the side of the gate away from the first surface and encapsulates the gate; The source electrode is located on the side of the dielectric layer away from the first surface; the source electrode penetrates the dielectric layer and contacts the source region and the first region respectively; The drain electrode is located on the second surface.
[0011] Optionally, the well region includes at least a first well region and a second well region; In the thickness direction perpendicular to the semiconductor body, the width of the second well region is equal to the width of the first well region; Alternatively, in the thickness direction perpendicular to the semiconductor body, the width of the second well region is greater than the width of the first well region.
[0012] Optionally, the ion concentration in the second well region is equal to the ion concentration in the first well region.
[0013] Thirdly, a power module is provided, including a substrate and a semiconductor device as described in any embodiment of the second aspect, wherein the substrate is used to support the semiconductor device.
[0014] Fourthly, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the second aspect, the semiconductor device being electrically connected to the circuit board.
[0015] Fifthly, a vehicle is provided, including a load and a power conversion circuit as described in the fourth aspect embodiment, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.
[0016] The semiconductor device manufacturing method provided in this application predefines the ion implantation region on the transition surface of the semiconductor body using a self-aligned process, forms a well region by ion implantation on the transition surface, and then forms a new epitaxial layer to repeat the self-aligned process. This forms at least two well regions in the thickness direction of the semiconductor body, thereby creating a doped pillar region. Compared to related technologies that use multiple masks for ion implantation, resulting in overlay misalignment in the multi-layered well regions, this application method, by employing at least two self-aligned processes to define the well region formed by each ion implantation, achieves precise alignment of each well region, eliminating the need for additional masks, simplifying the manufacturing process, and effectively reducing the manufacturing cost of the semiconductor device.
[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 2 to 5 yes Figure 1 A structural diagram corresponding to each relevant step in the process; Figure 6 This is a schematic flowchart of step S120 in a semiconductor device manufacturing method according to an embodiment of this application; Figures 7 to 15 yes Figure 6 A structural diagram corresponding to the relevant steps in the process; Figure 16 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. Detailed Implementation
[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] This application provides a method for manufacturing a semiconductor device. Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figures 2 to 5 yes Figure 1 A structural diagram corresponding to each relevant step. See also... Figures 1 to 5 The manufacturing method of this semiconductor device specifically includes the following steps: S110, Provide a semiconductor body; the semiconductor body is configured as a first conductivity type, including a transition surface and a second surface disposed opposite to each other.
[0023] Specifically, see Figure 2 The semiconductor body 100 is configured with a first conductivity type, including a transition surface 101 and a second surface 102 disposed opposite to each other. Exemplarily, the semiconductor body 100 may include a substrate stacked together and an initially formed epitaxial layer 10; in some embodiments of this application, the semiconductor body 100 may also include only the initially formed epitaxial layer 10; in other embodiments of this application, the semiconductor body 100 may also include a substrate and a semiconductor layer formed by other processes. The initially formed epitaxial layer 10 is a semiconductor layer formed on the substrate by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).
[0024] S120. Repeat the operation of forming a well region in a portion of the transition surface and forming an epitaxial layer on the transition surface at least twice using a self-aligned process to form at least two stacked well regions to form a doped pillar region; wherein the well region is configured as a second conductivity type; the second conductivity type is different from the first conductivity type; the semiconductor body includes a first surface opposite to the second surface.
[0025] Specifically, see Figure 3 The operation of forming a well region 103 in a portion of the transition surface 101 and forming an epitaxial layer 104 in the transition surface 101 is repeated at least twice using a self-aligned process to form at least two stacked well regions 103 to form a doped pillar region 105; wherein the well region 103 is configured as a second conductivity type; the second conductivity type is different from the first conductivity type; the semiconductor body 100 includes a first surface 106 opposite to the second surface 102.
[0026] For the doped pillar region 105 in the fabrication of a superjunction silicon carbide MOSFET, due to its considerable depth, at least two ion implantations are required during the manufacturing process. Related technologies employ a mask for at least two ion implantations to form at least two well regions 103, resulting in the doped pillar region 105. However, multiple ion implantations using a mask along the thickness of the semiconductor body can lead to overlay misalignment, causing inaccurate alignment between the implanted well regions 103. Furthermore, for well regions 103 with varying widths, multiple different masks are required for corresponding ion implantations, significantly increasing the manufacturing cost of the semiconductor device and complicating the manufacturing process.
[0027] In this embodiment, a self-aligned process is used to predefine the corresponding sidewall structure to be formed in the region requiring ion implantation, and ion implantation is performed according to the sidewall structure to form the well region 103. For the deep doped pillar region 105 in the fabrication of a superjunction silicon carbide MOSFET, the above steps can be repeated at least twice to form at least two well regions 103 in the thickness direction of the semiconductor body, thereby obtaining the doped pillar region 105. Exemplarily, Figure 3 The diagram illustrates a doped pillar region 105 comprising four well regions 103. Therefore, it requires four repetitions of the self-aligned ion implantation process. The number of well regions 103 in the doped pillar region 105 can be determined based on the actual thickness of the semiconductor body 100 and the depth of each ion implantation, and is not limited here. This eliminates the need for additional mask fabrication, effectively reducing the manufacturing cost of semiconductor devices and simplifying the manufacturing process. Furthermore, the dimensions of the sidewall structures formed in the self-aligned process can be adjusted as needed, allowing for the implantation of well regions 103 of arbitrary width without a mask, thus obtaining the corresponding doped pillar region 105. In the self-aligned process, the position and size of the sidewall structures can be precisely controlled. Therefore, each well region 103 can be precisely aligned, and its width in the direction perpendicular to the thickness can be adjusted. The number of layers, implantation depth, and width of the doped pillar region 105 can be flexibly designed according to the actual on-resistance and charge balance requirements of the semiconductor device, adapting the semiconductor device to various application scenarios and improving the electrical performance of the fabricated semiconductor device. For example, a MOSFET semiconductor device may include an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. In this embodiment, an N-type MOSFET semiconductor device is used as an example for illustration. If the semiconductor body 100 is an N-type semiconductor body, then the doped pillar region 105 is a P-type pillar region.
[0028] S130. A body region, a source region, and a first region are formed on the first surface; wherein the source region is configured with a first conductivity type, the first region is configured with a second conductivity type, and both are located on the first surface; the body region is configured with a second conductivity type, located on the side of the source region away from the first surface, and is in contact with the doped pillar region.
[0029] Specifically, see Figure 4 A body region 107, a source region 108, and a first region 109 are formed on the first surface 106. The source region 108 is configured as a first conductivity type, and the first region 109 is configured as a second conductivity type, both located on the first surface 106. The body region 107 is configured as a second conductivity type, located on the side of the source region 108 away from the first surface 106, and is in contact with the doped pillar region 105.
[0030] For example, taking an N-type MOSFET semiconductor device as an example, if the semiconductor body 100 is an N-type semiconductor body, then the body region 107 is a P-type doped region, the source region 108 is an N+ type doped region, and the first region 109 is a P+ type doped region.
[0031] S140, A gate is formed on the first surface, and a dielectric layer is formed on the side of the gate away from the first surface; the dielectric layer encapsulates the gate.
[0032] Specifically, see Figure 5 A gate 110 is formed on the first surface 106, and a dielectric layer 111 is formed on the side of the gate 110 away from the first surface 106; the dielectric layer 111 encloses the gate 110. For the planar silicon carbide MOSFET provided in this application, the gates 110 are located on the first surface 106 and are spaced apart. The gate 110 includes a gate oxide layer 1101 and a gate polysilicon layer 1102. The gate polysilicon layer 1102 is located on the side of the gate oxide layer 1101 away from the first surface 106. The dielectric layer 111 encloses the spaced-apart gates 110 to achieve insulation between the gates 110 and other conductive structures.
[0033] S150, A source electrode is formed on the side of the dielectric layer away from the first surface; the source electrode penetrates the dielectric layer and contacts the source region and the first region respectively.
[0034] Specifically, see [link to relevant documentation] Figure 5 A source electrode 112 is formed on the side of the dielectric layer 111 away from the first surface 106. The source electrode 112 penetrates the dielectric layer 111 and contacts the source region 108 and the first region 109, respectively. The contact between the source electrode 112 and the source region 108 and the first region 109 located on the first surface 106 allows for ohmic contact. The source electrode 112 is insulated from the gate electrode 110 through the dielectric layer 111.
[0035] S160, a drain electrode is formed on the second surface.
[0036] Specifically, see [link to relevant documentation] Figure 5 A drain 113 is formed on the second surface 102. The drain 113 is formed on the second surface 102 of the semiconductor body 100. The drain 113 may include a stack of metals Ti, Ni, and Ag.
[0037] The semiconductor device manufacturing method provided in this application predefines the ion implantation region on the transition surface 101 of the semiconductor body 100 using a self-alignment process, performs ion implantation on the transition surface 101 to form a well region 103, and then forms a new epitaxial layer 104 so that the self-alignment process can be repeated to form at least two well regions 103 in the thickness direction of the semiconductor body 100, thereby obtaining a doped pillar region 105. Compared with the related technology that uses multiple masks for ion implantation, resulting in multi-layer well regions with overlay deviations, this application embodiment uses at least two self-alignment processes to define the region of the well region 103 formed by each ion implantation, which can achieve precise alignment of each well region 103, eliminate the need for additional masks, simplify the manufacturing process, and effectively reduce the manufacturing cost of semiconductor devices.
[0038] Based on the above embodiments, optionally, the transition surface 101 includes at least a first transition surface 1011 and a second transition surface 1012; at least two well regions 103 include a first well region 1031 and a second well region 1032; and the epitaxial layer 104 includes at least a first epitaxial layer 1041 and a second epitaxial layer 1042.
[0039] Figure 6 This is a schematic flowchart of step S120 in a semiconductor device manufacturing method provided in an embodiment of this application. Figures 7 to 15 yes Figure 6 A structural diagram corresponding to the relevant steps. See also... Figures 6 to 15 The step S120, which involves repeating the self-aligned process at least twice to form a well region on a portion of the transition surface and an epitaxial layer on the transition surface, specifically includes the following steps: S121. A first sidewall structure is formed on the first transition surface. A first self-aligned process is used to perform ion implantation on the first transition surface to form a first well region in the semiconductor body. A first epitaxial layer is formed on the first transition surface. The first epitaxial layer includes a second transition surface opposite to the second surface.
[0040] Specifically, a first sidewall structure 1141 is formed on the first transition surface 1011. A first self-aligned process is used to perform ion implantation on the first transition surface 1011 to form a first well region 1031 in the semiconductor body 100. A first epitaxial layer 1041 is formed on the first transition surface 1011. The first epitaxial layer 1041 includes a second transition surface 1012 opposite to the second surface 102.
[0041] For example, see Figure 7 A first mask layer 1151 is formed on the first transition surface 1011. The first mask layer 1151 has a first opening T1, which exposes a portion of the first transition surface 1011. The first mask layer 1151 is obtained by depositing mask material on the first transition surface 1011 and etching away a portion of the area to form the first opening T1.
[0042] See Figure 8 and Figure 9 A first oxide layer 1161 covering the first opening T1 is formed on the side of the first mask layer 1151 away from the first transition surface 1011. The first oxide layer 1161 is etched to form a first sidewall structure 1141. The first sidewall structures 1141 have a first spacing d1 between them. By depositing an oxide material, such as silicon dioxide, on the surface of the first mask layer 1151, a first oxide layer 1161 with a stepped shape, i.e., with grooves, can be formed. According to the position of the sidewall of the groove, the first oxide layer 1161 is etched, retaining only the groove sidewall portion located in the same layer as the first mask layer 1151, to form the first sidewall structure 1141. The first spacing d1 between the first sidewall structures 1141 defines the region for the first ion implantation.
[0043] See Figure 10 Ion implantation is performed on the first transition surface 1011 to form a first well region 1031 in the semiconductor body 100. Ions of a second conductivity type are used to implant ions into the first transition surface 1011 according to the first spacing d1 of the first sidewall structure 1141 to form the first well region 1031 in the semiconductor body 100. The width of the first well region 1031 is the same as the dimension of the first spacing d1.
[0044] See Figure 11 The first sidewall structure and the first mask layer are removed, and a first epitaxial layer 1041 is formed on the first transition surface 1011. After the first well region 1031 is formed, the first sidewall structure and the first mask layer are etched away by wet etching, and a first epitaxial layer 1041 is epitaxially grown on the first transition surface 1011 so as to form the second well region 1032 in the future.
[0045] It should be noted that silicon carbide MOSFETs can include superjunction MOSFETs and semi-superjunction MOSFETs. For superjunction MOSFETs, the doped pillar region extends directly from the bulk region to the substrate surface in the semiconductor body 100. See [link to relevant documentation]. Figure 11 During the first self-aligned process to form the first well region 1031, its implantation depth extends from the first transition surface 1011 to the substrate surface. For a semi-superjunction MOSFET, the doped pillar region extends from the body region into the epitaxial layer 10 of the semiconductor body 100, without contacting the substrate surface. During the first self-aligned process to form the first well region 1031, its implantation depth extends from the first transition surface 1011 into the epitaxial layer 10, without contacting the substrate surface. The above two device manufacturing methods can be selected according to the user's actual needs, and are not restricted here.
[0046] S122. A second sidewall structure is formed on the second transition surface. A second self-aligned process is used to implant ions into the second transition surface to form a second well region in the semiconductor body. A second epitaxial layer is formed on the second transition surface. The second epitaxial layer includes a first surface opposite to the second surface.
[0047] Specifically, a second sidewall structure 1142 is formed on the second transition surface 1012. A second self-aligned process is used to perform ion implantation on the second transition surface 1012 to form a second well region 1032 in the semiconductor body 100. A second epitaxial layer 1042 is formed on the second transition surface 1012. The second epitaxial layer 1042 includes a first surface 106 opposite to the second surface 102.
[0048] For example, see Figure 12 A second mask layer 1152 is formed on the second transition surface 1012. The second mask layer 1152 has a second opening T2, which exposes a portion of the second transition surface 1012. The second mask layer 1152 is obtained by depositing mask material on the second transition surface 1012 and etching away a portion of the area to form the second opening T2. The width of the second opening T2 can be set according to actual manufacturing requirements and is not limited here. For example, for manufacturing a doped pillar region that is rectangular in shape, the width of the second opening T2 must be the same as the width of the first opening T1; for manufacturing a doped pillar region that is stepped, the width of the second opening T2 must be greater than the width of the first opening T1. Figure 12 This illustrates the case where the width of the second opening T2 is equal to the width of the first opening T1.
[0049] See Figure 13 and Figure 14A second oxide layer 1162 covering the second opening T2 is formed on the side of the second mask layer 1152 away from the second transition surface 1012. The second oxide layer 1162 is etched to form a second sidewall structure 1142. The second sidewall structures 1142 have a second spacing d2 between them. A second oxide layer 1162 with grooves is deposited on the surface of the second mask layer 1152. The second oxide layer 1162 is etched according to the sidewall position of the grooves, retaining only the groove sidewall portion located in the same layer as the second mask layer 1152 to form the second sidewall structure 1142. The second spacing d2 between the second sidewall structures 1142 defines the region for the second ion implantation.
[0050] See Figure 15 Ion implantation is performed on the second transition surface 1012 to form a second well region 1032 in the semiconductor body 100. Ions of a second conductivity type are used for ion implantation at a second spacing to form the second well region 1032. The width of the second well region 1032 is the same as the dimension of the second spacing.
[0051] See also Figure 15 The second sidewall structure and the second mask layer are removed, and a second epitaxial layer 1042 is formed on the second transition surface 1012. After forming the second well region 1032, the second sidewall structure and the second mask layer are removed by wet etching, and a second epitaxial layer 1042 is epitaxially grown on the second transition surface 1012 so that the body region, the source region and the first region can be formed on the first surface 106 of the second epitaxial layer 1042.
[0052] It should be noted that this application embodiment only specifically describes the process of forming two well regions 103 by repeatedly performing the self-alignment process twice, and does not limit the formation of only two well regions 103 in the actual manufacturing process of semiconductor devices. Based on the actual type of semiconductor device, the actual on-resistance requirements, and charge balance requirements, the actual thickness of the semiconductor body 100 and the implantation depth and width of the well regions 103 formed in each self-alignment process can be flexibly designed. This allows for arbitrary adjustment of the number of times the self-alignment process is repeated and the number of well regions 103 layers formed, without limitation, so that the resulting semiconductor device can adapt to various application scenarios. Furthermore, the operation of forming well regions 103 through multiple repeated self-alignment processes is the same as the operation of forming the first well region 1031 or the second well region 1032 described above, and will not be repeated here. For example, Figure 3 The case of forming a 4-layer trap region 103 by repeating the self-alignment process 4 times is shown.
[0053] Based on the above embodiments, optionally, a trap region is formed in a portion of the transition surface, including: A first well region with a first width is formed on a first transition surface, and a second well region with a second width is formed on a second transition surface; Specifically, in the thickness direction perpendicular to the semiconductor body, the second width is equal to the first width; the second spacing is equal to the first spacing; or, in the thickness direction perpendicular to the semiconductor body, the second width is greater than the first width; the second spacing is greater than the first spacing.
[0054] Specifically, in the process of forming the trap region, see Figure 15 Two well regions 103 can be fabricated, with the first well region 1031 having the same first width as the second well region 1032, forming a rectangular pillar-shaped doped pillar region 105. This increases the area of the drift region of the first conductivity type on both sides of the doped pillar region 105, thereby widening the electron transport path of the semiconductor device and improving its electrical performance. Alternatively, two well regions can be fabricated, with the first well region having a smaller first width than the second well region, forming a stepped doped pillar region. Figure 16 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. See also... Figure 16 This illustrates a stepped doped pillar region 105 forming a four-layer well region 103. This effectively reduces electric field concentration at the corners of the bulk region, thus improving the breakdown voltage performance of the semiconductor device. The second spacing between the second sidewall structures can be adjusted by adjusting the thickness of the second oxide layer, thereby adjusting the relationship between the width of the fabricated second well region and the width of the first well region.
[0055] Based on the above embodiments, optionally, a trap region is formed in a portion of the transition surface, including: A first well region with a first ion concentration is formed on a first transition surface, and a second well region with a second ion concentration is formed on a second transition surface; The concentration of the second ion is equal to the concentration of the first ion.
[0056] Specifically, by setting the ion concentrations of the first and second well regions formed by the repeated self-alignment process to the same concentration, the corresponding functions of a superjunction MOSFET or a semi-superjunction MOSFET can be achieved. Alternatively, the ion concentration of the first well region can be set to be less than that of the second well region, i.e., the ion concentration of the doped pillar region decreases towards the second surface; or the ion concentration of the first well region can be set to be greater than that of the second well region, i.e., the ion concentration of the doped pillar region increases towards the second surface. No limitation is imposed here. See also, for examples... Figure 5 The ion concentration of the four-layer well region 103 can be set to be the same, or the ion concentration of the four-layer well region 103 can be set to a decreasing trend or an increasing trend towards the side closer to the second surface 102, without any restrictions.
[0057] This application also provides a semiconductor device. See [link to relevant documentation]. Figure 5 The semiconductor device includes: The semiconductor body 100 is configured with a first conductivity type and includes a first surface 106 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a body region 107, a source region 108, a first region 109, and a doped pillar region 105. The source region 108 is configured with a first conductivity type, the first region 109 is configured with a second conductivity type, and both are located on the first surface 106. The body region 107 is configured with a second conductivity type and is located on the side of the source region 108 away from the first surface 106, and is in contact with the doped pillar region 105. The doped pillar region 105 includes at least two stacked well regions 103, and the well regions 103 are configured with a second conductivity type. Gate 110 is located on the first surface 106; The dielectric layer 111 is located on the side of the gate 110 away from the first surface 106 and encloses the gate 110; The source electrode 112 is located on the side of the dielectric layer 111 away from the first surface 106; the source electrode 112 penetrates the dielectric layer 111 and contacts the source region 108 and the first region 109 respectively; Drain 113 is located on the second surface 102.
[0058] Specifically, a drift region of a first conductivity type is provided between the body region 107 and the substrate in the semiconductor body 100, and a doped pillar region 105 of a second conductivity type is provided. The doped pillar region 105 may include at least two densely stacked well regions 103. For example, if the doped pillar region 105 extends from the body region 107 to the substrate surface, a superjunction MOSFET is formed; if the doped pillar region 105 extends from the body region 107 into the drift region without contacting the substrate surface, a semi-superjunction MOSFET is formed. By setting the drift region with alternating pillar regions of the first conductivity type and doped pillar regions of the second conductivity type, the electric field in the drift region can be uniformly distributed, effectively reducing the peak electric field; and it breaks the traditional relationship between reverse breakdown voltage and doping concentration, which can significantly increase the doping concentration of the pillar regions of the first conductivity type in the drift region, effectively reducing the specific on-resistance and improving the electrical performance of the semiconductor device.
[0059] The semiconductor device provided in this application embodiment is manufactured using the manufacturing method of the semiconductor device provided in any of the above embodiments, and has similar beneficial effects to the semiconductor device manufacturing method, which will not be described in detail here. Furthermore, by providing a doped pillar region 105 in the drift region, the doped pillar region 105 includes at least two stacked well regions 103. By designing whether the doped pillar region 105 is in contact with the substrate surface and adjusting the implantation depth of the doped pillar region 105, a superjunction MOSFET or a semi-superjunction MOSFET can be obtained accordingly. This allows for a uniform electric field distribution in the drift region, effectively reducing the peak electric field; and it can significantly increase the doping concentration of the pillar region of the first conductivity type in the drift region, effectively reducing the specific on-resistance, which is beneficial for improving the electrical performance of the semiconductor device.
[0060] Based on the above embodiments, see Figure 5 and Figure 16 Optionally, the well region 103 includes at least a first well region 1031 and a second well region 1032; In the thickness direction perpendicular to the semiconductor body 100, the width of the second well region 1032 is equal to the width of the first well region 1031; Alternatively, in the thickness direction perpendicular to the semiconductor body 100, the width of the second well region 1032 is greater than the width of the first well region 1031.
[0061] Specifically, Figure 5 The diagram illustrates a case where the width of the second well region 1032 is equal to the width of the first well region 1031, forming a rectangular pillar-shaped doped pillar region 105. This increases the area of the drift region of the first conductivity type on both sides of the doped pillar region, thereby widening the electron transport path of the semiconductor device and improving its electrical performance.
[0062] Figure 16 The diagram illustrates a case where the width of the second well region 1032 is greater than the width of the first well region 1031, forming a stepped doped pillar region 105. This effectively mitigates electric field concentration at the corners of the bulk region, thus improving the breakdown voltage performance of the semiconductor device. The second spacing between the second sidewall structures can be adjusted by regulating the thickness of the second oxide layer, thereby regulating the relationship between the width of the fabricated second well region and the width of the first well region.
[0063] Based on the above embodiments, see below. Figure 6 Optionally, the ion concentration of the second well region 1032 is equal to the ion concentration of the first well region 1031.
[0064] Specifically, by setting the ion concentration of the second well region 1032 to be the same as that of the first well region 1031, the corresponding functions of a superjunction MOSFET or a semi-superjunction MOSFET can be achieved. Alternatively, depending on actual needs, the ion concentration of the doped pillar region 105 can be set to decrease towards the side closer to the second surface 102; or the ion concentration of the doped pillar region 105 can be set to increase towards the side closer to the second surface 102. There are no restrictions on this.
[0065] This application provides a power module including a substrate and at least one semiconductor device provided in any of the embodiments of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including the semiconductor device provided in any of the embodiments of this application will not be elaborated further here.
[0066] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the embodiments of this application, and the semiconductor device is electrically connected to the circuit board.
[0067] Therefore, the beneficial effects of this power conversion circuit, which includes any of the semiconductor devices provided in the embodiments of this application, will not be elaborated further here.
[0068] This application also provides a vehicle, including a load and a power conversion circuit as provided in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power and then input it to the load. Therefore, the beneficial effects of this vehicle including the power conversion circuit provided in any embodiment of this application will not be elaborated further here.
[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided; the semiconductor body is configured with a first conductivity type and includes a transition surface and a second surface disposed opposite to each other; The operation of forming a well region in a portion of the transition surface and forming an epitaxial layer on the transition surface is repeated at least twice using a self-aligned process to form at least two stacked well regions to form a doped pillar region; wherein the well region is configured with a second conductivity type; the second conductivity type is different from the first conductivity type; the semiconductor body includes a first surface opposite to the second surface; A body region, a source region, and a first region are formed on the first surface; wherein the source region is configured with the first conductivity type, the first region is configured with the second conductivity type, and both are located on the first surface; the body region is configured with the second conductivity type, located on the side of the source region away from the first surface, and is in contact with the doped pillar region; A gate is formed on the first surface, and a dielectric layer is formed on the side of the gate away from the first surface; the dielectric layer encapsulates the gate. A source electrode is formed on the side of the dielectric layer away from the first surface; the source electrode penetrates the dielectric layer and contacts the source region and the first region, respectively; A drain electrode is formed on the second surface.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The transition surface includes at least a first transition surface and a second transition surface; the at least two well regions include a first well region and a second well region; the epitaxial layer includes at least a first epitaxial layer and a second epitaxial layer; The repeated execution of the self-aligned process at least twice to form a well region in a portion of the transition surface and to form an epitaxial layer on the transition surface includes: A first sidewall structure is formed on the first transition surface, and the first well region is formed in the semiconductor body by ion implantation using a first self-aligned process; and a first epitaxial layer is formed on the first transition surface; wherein the first epitaxial layer includes a second transition surface opposite to the second surface; A second sidewall structure is formed on the second transition surface, and a second self-aligned process is used to perform ion implantation on the second transition surface to form the second well region in the semiconductor body; and a second epitaxial layer is formed on the second transition surface; wherein the second epitaxial layer includes the first surface opposite to the second surface.
3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The first sidewall structure is formed on the first transition surface by using a first self-aligned process to perform ion implantation on the first transition surface to form the first well region in the semiconductor body. The first epitaxial layer is formed on the first transition surface, including: A first mask layer is formed on the first transition surface; the first mask layer is provided with a first opening, the first opening exposing a portion of the first transition surface; A first oxide layer covering the first opening is formed on the side of the first mask layer away from the first transition surface, and the first oxide layer is etched to form a first sidewall structure; the first sidewall structures have a first spacing between them; Ion implantation is performed on the first transition surface to form the first well region in the semiconductor body; Remove the first sidewall structure and the first mask layer, and form the first epitaxial layer on the first transition surface; The process of forming the second sidewall structure on the second transition surface, employing a second self-aligned process, involves ion implantation of the second transition surface to form the second well region in the semiconductor body; and forming the second epitaxial layer on the second transition surface, including: A second mask layer is formed on the second transition surface; the second mask layer is provided with a second opening, the second opening exposing a portion of the second transition surface; A second oxide layer covering the second opening is formed on the side of the second mask layer away from the second transition surface, and the second oxide layer is etched to form a second sidewall structure; the second sidewall structures have a second spacing between them; Ion implantation is performed on the second transition surface to form the second well region in the semiconductor body; Remove the second sidewall structure and the second mask layer, and form the second epitaxial layer on the second transition surface.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The formation of a well region in a portion of the transition surface includes: A first well region with a first width is formed on the first transition surface, and a second well region with a second width is formed on the second transition surface; Wherein, in the thickness direction perpendicular to the semiconductor body, the second width is equal to the first width; the second spacing is equal to the first spacing; or, in the thickness direction perpendicular to the semiconductor body, the second width is greater than the first width; the second spacing is greater than the first spacing.
5. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The formation of a well region in a portion of the transition surface includes: A first well region with a first ion concentration is formed on the first transition surface, and a second well region with a second ion concentration is formed on the second transition surface; Wherein, the second ion concentration is equal to the first ion concentration.
6. A semiconductor device, characterized in that, include: A semiconductor body, configured for a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a body region, a source region, a first region, and a doped pillar region; the source region is configured for the first conductivity type, the first region is configured for a second conductivity type, and both are located on the first surface; the body region is configured for the second conductivity type, located on the side of the source region away from the first surface, and is in contact with the doped pillar region; the doped pillar region includes at least two stacked well regions, and the well regions are configured for the second conductivity type; The gate is located on the first surface; A dielectric layer is located on the side of the gate away from the first surface and encapsulates the gate; The source electrode is located on the side of the dielectric layer away from the first surface; the source electrode penetrates the dielectric layer and contacts the source region and the first region respectively; The drain electrode is located on the second surface.
7. The semiconductor device according to claim 6, characterized in that, The well region includes at least a first well region and a second well region; In the thickness direction perpendicular to the semiconductor body, the width of the second well region is equal to the width of the first well region; Alternatively, in the thickness direction perpendicular to the semiconductor body, the width of the second well region is greater than the width of the first well region.
8. The semiconductor device according to claim 7, characterized in that, The ion concentration in the second well region is equal to the ion concentration in the first well region.
9. A power module, characterized in that, The invention includes a substrate and the semiconductor device according to any one of claims 6 to 8, wherein the substrate is used to support the semiconductor device.
10. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 6 to 8, the semiconductor device being electrically connected to the circuit board.
11. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 10, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.