Flexible ferroelectric floating gate transistor based on two-dimensional ultrathin heterojunction and preparation process thereof

Abstract

The application discloses a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction and a preparation process thereof, which comprises, from bottom to top, a flexible polymer substrate film, a bottom gate metal electrode formed on the surface of the flexible polymer substrate film, a ferroelectric dielectric film layer covering the surface of the bottom gate metal electrode and the flexible polymer substrate film, a metal floating gate island located in a preset region on the surface of the ferroelectric dielectric film layer, an ultrathin tunneling dielectric layer covering the metal floating gate island and deposited on the surface of the ferroelectric dielectric film layer, a two-dimensional semiconductor channel sheet located on the surface of the ultrathin tunneling dielectric layer and serving as a semiconductor channel of the transistor, and a source metal electrode and a drain metal electrode respectively located at two ends of the two-dimensional semiconductor channel sheet and forming ohmic contact. The application solves the technical problems of incompatibility between high-temperature ferroelectric phase transition annealing and a flexible substrate, low alignment precision of micro-nano processing of the flexible substrate and large damage of device peeling.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device and flexible bioelectronics manufacturing technology, and more specifically, to a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction, and also to a fabrication process for a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction. Background Technology

[0002] In the field of bioelectronics, storage has always been a major challenge. Conventional silicon-based memories often fail in living organisms subjected to extensive mechanical bending and movement. To address this problem, flexible non-volatile memories and neuromorphic computing devices are core components for next-generation wearable electronics and biomedical applications. Among these, two-dimensional materials (such as molybdenum disulfide) are crucial. Due to its atomic-level thickness, high mobility, and excellent mechanical flexibility, it has become an ideal material for constructing flexible transistor channels. However, the following technical challenges exist in the current fabrication process of flexible ferroelectric / floating gate transistors:

[0003] High-temperature annealing has poor compatibility: HZO ( Ferroelectric thin films require high-temperature rapid thermal annealing (RTA) at 400℃~500℃ to induce the formation of an orthorhombic (o-phase) ferroelectric phase. However, most flexible polymer substrates (such as PDMS, PET, and PET / PI composite films) are prone to deformation, decomposition, or even carbonization at such high temperatures, leading to device failure.

[0004] Low alignment accuracy in micro-nano fabrication: The large thermal expansion coefficient of flexible substrates and their susceptibility to deformation under stress make submicron-level photolithography alignment and multilayer patterning processes extremely difficult.

[0005] Charge leakage and insufficient bending reliability: Under bending stress, traditional floating gate devices are prone to microcracks in the gate dielectric layer, leading to charge loss. Furthermore, mechanical peeling of a single flexible substrate can easily cause stress damage to the extremely thin two-dimensional channel.

[0006] Therefore, there is an urgent need to develop a high-performance flexible ferroelectric floating gate transistor and its fabrication process that can be compatible with HZO high-temperature ferroelectric phase transition annealing, achieve high-precision multilayer micro-nano processing, and be non-destructive to peel off. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction and its fabrication process, solving the technical problems of incompatibility between high-temperature ferroelectric phase transition annealing and flexible substrates, low alignment accuracy of flexible substrate micro-nano processing, and large device peeling damage.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A fabrication process for a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction includes the following steps:

[0010] Step 1: The first flexible layer and the second flexible layer are spin-coated sequentially on the surface of the rigid glass substrate, and then baked and cured to form a double-layer flexible substrate;

[0011] Step 2: Define the bottom gate pattern on the double-layer flexible substrate using photolithography, deposit a metal layer, and then form the bottom gate metal electrode using a lift-off process;

[0012] Step 3: Using atomic layer deposition (ALD) technology, a hafnium zirconium oxide ferroelectric thin film is deposited on the surface of the bottom gate metal electrode and the double-layer flexible substrate; then, rapid thermal annealing is performed under a nitrogen protective atmosphere to induce the crystallization of the hafnium zirconium oxide ferroelectric thin film to form an orthorhombic ferroelectric phase, thus obtaining a ferroelectric dielectric thin film layer.

[0013] Step 4: Define the floating gate region using photolithography, deposit a nanoscale metal thin film, and then use a lift-off process to form a metal floating gate island on the surface of the ferroelectric thin film layer;

[0014] Step 5: Using atomic layer deposition technology, a hafnium dioxide film is deposited on the surface of the metal floating gate island and the ferroelectric thin film layer to form an ultrathin tunneling dielectric layer covering the metal floating gate island;

[0015] Step 6: Transfer the two-dimensional semiconductor wafer to the surface of the ultrathin tunneling dielectric layer, remove interface residues by annealing and perform patterning to form a two-dimensional semiconductor channel wafer;

[0016] Step 7: Align the two ends of the channel and define the source and drain regions using photolithography. After depositing the metal layer, a lift-off process is used to form the source metal electrode and drain metal electrode with ohmic contact at both ends of the two-dimensional semiconductor channel wafer.

[0017] Step 8: The flexible chip containing the first flexible layer, the second flexible layer and the complete device structure is peeled off from the glass substrate without damage to obtain an independent flexible ferroelectric floating gate transistor; the first flexible layer and the second flexible layer together serve as a flexible polymer substrate film.

[0018] Further, in step one, the first flexible layer is water-soluble polyvinyl alcohol or polyamic acid, with a thickness of 150~300nm and a drying temperature of 80~120℃; the second flexible layer is polyimide, with a thickness of 8~15μm after curing.

[0019] Furthermore, in step two, the bottom gate metal electrode adopts a Cr / Au stacked structure and is deposited using electron beam evaporation or magnetron sputtering processes; wherein Cr is the binder layer with a thickness of 3~10nm, and Au is the main conductive layer with a thickness of 20~60nm.

[0020] Furthermore, in step three, hafnium zirconium oxide is... The precursors for atomic layer deposition are TDMAHf, TDMAZr, and The deposition temperature is 220~280℃, and the thickness of the deposited film is 10~20nm; the rapid thermal annealing temperature is 400~500℃, and the annealing time is 30~60s.

[0021] Furthermore, in step four, the metal floating island is a Pt nanofilm with a thickness of 2-5 nm, deposited using an electron beam evaporation process.

[0022] Furthermore, in step five, the ultrathin tunneling dielectric layer is... Thin films with a thickness of 3-8 nm are deposited using atomic layer deposition at 180-220°C.

[0023] Furthermore, in step six, the two-dimensional semiconductor wafer is 1 to 4 Thin sheets were transferred using PDMS-assisted dry transfer technology; after transfer, they were annealed in an argon atmosphere at 160~200℃ for 1~3h to eliminate interfacial residues and gas adsorption.

[0024] Furthermore, in step eight, the first flexible layer is naturally detached from the surface of the rigid glass substrate by immersion in warm water.

[0025] This invention also provides a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction, fabricated using the aforementioned fabrication process for a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction, comprising:

[0026] Flexible polymer substrate thin film;

[0027] The bottom gate metal electrode is formed on the upper surface of the flexible polymer substrate thin film;

[0028] A ferroelectric thin film layer is applied to the upper surface of the bottom gate metal electrode and the flexible polymer substrate film to provide ferroelectric polarization control.

[0029] Metal floating gate islands, located in a predetermined area on the upper surface of the ferroelectric thin film layer, are used to capture and store charges;

[0030] An ultrathin tunneling dielectric layer, which covers the metal floating gate island and is deposited on the upper surface of the ferroelectric dielectric thin film layer, is used to provide charge tunneling and blocking functions.

[0031] Two-dimensional semiconductor channel wafers are located on the upper surface of an ultrathin tunneling dielectric layer, serving as semiconductor channels for transistors;

[0032] The source metal electrode and the drain metal electrode are located at both ends of the two-dimensional semiconductor channel sheet and form an ohmic contact.

[0033] In summary, the present invention has the following beneficial effects:

[0034] Using a glass substrate and a double-layer flexible substrate as a rigid-flexible composite support platform not only meets the process requirements for HZO to form an orthogonal ferroelectric phase at 400℃~500℃, but also avoids high-temperature deformation of the flexible substrate.

[0035] In the entire process of micro-nano fabrication (photolithography, evaporation, ALD, transfer), rigid glass supports eliminate alignment errors caused by the stretching and deformation of flexible substrates, greatly improving device yield.

[0036] Through HZO ferroelectric polarization and The synergistic effect of charge trapping in nano-floating gates enables a large storage window, ultra-low operating voltage (<3V), and long charge retention time (>3V). s).

[0037] By designing a double-layer flexible substrate, serving as a flexible sacrificial layer (first flexible layer) and a flexible support layer (second flexible layer) respectively, stress concentration during device release is concentrated at the interface of the flexible sacrificial layer, effectively protecting the top ultrathin layer. The channel and each dielectric layer are protected from mechanical peeling damage, and the electrical performance can be maintained even with a bending radius of less than 2mm. Attached Figure Description

[0038] Figure 1 This is a flowchart of the fabrication process of a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction in Example 1;

[0039] Figure 2 This is a schematic diagram of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction in Example 1.

[0040] Figure reference numerals: 1. Flexible polymer substrate thin film; 2. Bottom gate metal electrode; 3. Ferroelectric dielectric thin film layer; 4. Metal floating gate island; 5. Ultrathin tunneling dielectric layer; 6. Two-dimensional semiconductor channel sheet; 7. Source metal electrode; 8. Drain metal electrode. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1:

[0043] This embodiment describes a fabrication process for a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction. The specific fabrication process is as follows:

[0044] Step 1: Fabrication of a rigid glass substrate and a double-layer flexible substrate;

[0045] Take a 1cm×1cm quartz glass substrate and ultrasonically clean it in acetone, isopropanol and deionized water for 10 minutes each. After drying with nitrogen, bake it on a hot plate at 120℃ for 15 minutes to completely remove surface moisture and impurities.

[0046] A 200nm thick layer of water-soluble polyvinyl alcohol (PVA) is spin-coated onto the surface of a glass substrate as the first flexible layer, also known as the flexible sacrificial layer; it is then baked and cured at 100°C.

[0047] A polyimide (PI) precursor solution is spin-coated over the first flexible layer and cured by gradient temperature increase. The specific curing process is as follows: hold at 100℃ for 30 min, hold at 200℃ for 30 min, and hold at 350℃ for 1 h. Finally, a second flexible layer with a thickness of about 10 μm is formed, which serves as the flexible support layer. This is the flexible polymer substrate film 1 of the device.

[0048] Step 2: Deposition of the bottom gate electrode;

[0049] A positive resist (LOR10A, S1818) is coated on the surface of a flexible polymer substrate film 1, and the bottom grid pattern is defined by ultraviolet lithography exposure and development.

[0050] Electron beam evaporation (EBE) deposition was used to deposit a 5 nm Cr binder layer and a 30 nm Au gate metal layer sequentially. The photoresist and the overlying metal layer were removed by acetone immersion and stripping to obtain the patterned bottom gate metal electrode 2.

[0051] Step 3: Growth of HZO ferroelectric dielectric layer and ferroelectric phase induced annealing;

[0052] The sample was placed in the atomic layer deposition (ALD) reaction chamber with TDMAHf, TDMAZr, and Using the precursor, a 15nm thick layer was grown at a deposition temperature of 250℃. (HZO) thin films. Among them, TDMAHf and TDMAZr are tetra(dimethylamino)hafnium and tetra(dimethylamino)zirconium, respectively, which are standard organometallic precursors for preparing hafnium zirconium oxide (HZO) thin films in atomic layer deposition process. Both are amino-based organometallic compounds.

[0053] The sample was placed in a rapid thermal annealing furnace and annealed at 450°C for 40s under a nitrogen protective atmosphere to induce the crystallization of HZO thin film to form an orthogonal ferroelectric phase, thus obtaining ferroelectric thin film layer 3.

[0054] Step 4: Fabrication of the floating gate layer;

[0055] Photoresist is spin-coated again and photolithography is performed to define the floating gate region; a 3nm thick Pt film is deposited using electron beam evaporation to serve as a nano-metal floating gate; the photoresist and excess metal are removed by acetone stripping to form discrete metal floating gate islands 4 on the surface of the ferroelectric thin film layer 3.

[0056] Step 5: Deposition of tunneling medium layer;

[0057] Atomic layer deposition (ALD) technology was used to deposit a 5 nm thick layer at 200°C. A thin film, serving as a charge tunneling insulating layer, uniformly coats the surfaces of the metal floating gate island 4 and the ferroelectric thin film layer 3, forming an ultrathin tunneling dielectric layer 5.

[0058] Step Six: Two-dimensional semiconductor channel transfer;

[0059] The few-layer polymer (FLP) prepared by mechanical exfoliation was transferred using PDMS-assisted dry transfer technology. Thin sheets (typically 1-4 layers) are precisely transferred onto the surface of the ultrathin tunneling dielectric layer 5. The sheets are annealed at 180°C in an argon atmosphere for 2 hours. Annealing removes interface residues and performs patterning to eliminate gas adsorption, forming a two-dimensional semiconductor channel sheet 6.

[0060] Step 7: Source / drain electrode deposition;

[0061] Photoresist is spin-coated and photolithography is performed at both ends of the channel to define the source and drain regions; 10nm Cr and 50nm Au metal layers are deposited sequentially by electron beam evaporation; after acetone stripping, ohmic contact source metal electrode 7 and drain metal electrode 8 are formed at both ends of the two-dimensional semiconductor channel sheet 6; wherein the channel length is 5μm and the width is 10μm.

[0062] Step 8: Delamination of the double-layer flexible substrate and release of the flexible device;

[0063] Immersing a glass substrate with the complete device structure in warm water allows the thin first flexible layer to detach from the glass substrate surface. The device film, containing both the first flexible layer (PVA) and the second flexible layer (PI), naturally peels off, resulting in an independent and complete flexible ferroelectric floating gate transistor. This peeling process requires only warm water immersion, eliminating the need for additional peeling solutions and minimizing impact on device performance.

[0064] This embodiment also discloses a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction, which is fabricated by the fabrication process in the above embodiment, including: a flexible polymer substrate thin film 1, a bottom gate metal electrode 2, a ferroelectric dielectric thin film layer 3, a metal floating gate island 4, an ultrathin tunneling dielectric layer 5, a two-dimensional semiconductor channel thin film 6, a source metal electrode 7, and a drain metal electrode 8.

[0065] Specifically, the flexible polymer substrate film 1 is composed of a first flexible layer and a second flexible layer. The first flexible layer remains on the back side of the second flexible layer. Since the thickness of the first flexible layer is much smaller than that of the second flexible layer, its main body is a high-temperature resistant polyimide film formed by the second flexible layer. The overall thickness of the flexible polymer substrate film 1 is approximately 10 μm, possessing both good mechanical flexibility and high-temperature stability, serving as a flexible support substrate for the device. The bottom gate metal electrode 2 is a Cr / Au stacked structure, wherein the Cr bonding layer is 5 nm thick and the Au main conductive layer is 30 nm thick. It is patterned using a photolithography lift-off process and is used to apply the gate control voltage.

[0066] Ferroelectric thin film layer 3 is an orthorhombic crystalline phase. The (HZO) thin film, with a thickness of 15 nm, is the core functional layer for the ferroelectric storage characteristics of the device, which regulates the channel potential through the ferroelectric polarization effect.

[0067] The metal floating gate island 4 is a Pt nanofilm island structure with a thickness of 3 nm, discretely distributed in a predetermined region on the surface of the ferroelectric thin film layer; the metal floating gate island 4 can capture and store tunneling charges, and work synergistically with ferroelectric polarization to expand the device's storage window.

[0068] Ultrathin tunneling dielectric layer 5 is A thin film, 5 nm thick, uniformly coats the metal floating gate island and covers the entire ferroelectric layer surface; it provides a quantum tunneling path for charge under operating voltage and acts as an insulating layer to block reverse leakage of floating gate charge under normal conditions.

[0069] Two-dimensional semiconductor channel wafer 6 is a few-layer Thin sheets (typically 1 to 4 layers) with a channel length of 5 μm and a channel width of 10 μm serve as the conductive channel for transistors, combining high carrier mobility with excellent mechanical flexibility.

[0070] The source metal electrode 7 and drain metal electrode 8 are both Cr / Au stacked structures, with a Cr binder layer thickness of 10 nm and an Au main conductive layer thickness of 50 nm. The two electrodes are formed at both ends of a two-dimensional semiconductor channel sheet, respectively. To form a good ohmic contact for the input and output of charge carriers.

[0071] Example 2:

[0072] This embodiment fabricates a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction. Its fabrication process is basically the same as in Example 1, except that:

[0073] In step one, the first flexible layer is water-soluble polyvinyl alcohol (PVA) with a thickness of 150 nm and a drying temperature of 80 °C; the second flexible layer is polyimide (PI) and is cured using a gradient temperature curing process, with a thickness of 8 μm after curing.

[0074] In step two, the bottom gate metal electrode adopts a Cr / Au stacked structure and is deposited using an electron beam evaporation process; Cr is the binder layer with a thickness of 3nm, and Au is the main conductive layer with a thickness of 20nm.

[0075] In step three, atomic layer deposition (ALD) is used with TDMAHf, TDMAZr and water as precursors to grow a 10 nm thick hafnium zirconium oxide (HZO) ferroelectric thin film at a deposition temperature of 220 °C. Subsequently, rapid thermal annealing at 400 °C for 30 s is performed under a nitrogen protective atmosphere to induce crystallization of the hafnium zirconium oxide ferroelectric thin film to form an orthorhombic ferroelectric phase, thus obtaining a ferroelectric dielectric thin film layer.

[0076] In step four, the metal floating gate island is a Pt nanofilm with a thickness of 2 nm, which is deposited using an electron beam evaporation process.

[0077] In step five, the ultrathin tunneling dielectric layer is hafnium dioxide (H2O). A thin film with a thickness of 3 nm was deposited at 180°C using atomic layer deposition.

[0078] In step six, the two-dimensional semiconductor wafer is a few-layer wafer. Thin sheets (usually 1-4 layers) are transferred using PDMS-assisted dry transfer technology; after transfer, they are annealed in an argon atmosphere at 160℃ for 1 hour to eliminate interfacial residues and gas adsorption.

[0079] In step seven, both the source metal electrode and the drain metal electrode adopt a Cr / Au stacked structure, where Cr is the bonding layer with a thickness of 3nm and Au is the main conductive layer with a thickness of 20nm. The two electrodes are formed at both ends of the two-dimensional semiconductor channel sheet and form an ohmic contact. The channel length is 5μm and the width is 10μm.

[0080] Step eight is the same as the operation in Example 1.

[0081] Example 3:

[0082] This embodiment fabricates a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction. The fabrication process is basically the same as in Embodiment 1, except that each process parameter is taken as the upper limit of the scope of protection of the claims, as detailed below:

[0083] In step one, the first flexible layer is water-soluble polyvinyl alcohol (PVA) with a thickness of 300 nm and a drying temperature of 120 °C; the second flexible layer is polyimide (PI) and is cured using a gradient temperature curing process, with a thickness of 15 μm after curing.

[0084] In step two, the bottom gate metal electrode adopts a Cr / Au stacked structure and is deposited using an electron beam evaporation process; Cr is the binder layer with a thickness of 10 nm, and Au is the main conductive layer with a thickness of 60 nm.

[0085] In step three, atomic layer deposition (ALD) is used with TDMAHf, TDMAZr, and water as precursors to grow a 20 nm thick hafnium zirconium oxide (HZO) ferroelectric thin film at a deposition temperature of 280 °C. Subsequently, rapid thermal annealing at 500 °C for 60 s is performed under a nitrogen protective atmosphere to induce crystallization of the hafnium zirconium oxide ferroelectric thin film to form an orthorhombic ferroelectric phase, thus obtaining a ferroelectric dielectric thin film layer.

[0086] In step four, the metal floating gate island is a Pt nanofilm with a thickness of 5 nm, which is deposited using an electron beam evaporation process.

[0087] In step five, the ultrathin tunneling dielectric layer is hafnium dioxide (H2O). A thin film with a thickness of 8 nm was deposited at 220°C using atomic layer deposition.

[0088] In step six, the two-dimensional semiconductor wafer is a few-layer wafer. Thin sheets (usually 1-4 layers) are transferred using PDMS-assisted dry transfer technology; after transfer, they are annealed in an argon atmosphere at 200℃ for 3 hours to eliminate interfacial residues and gas adsorption.

[0089] In step seven, both the source metal electrode and the drain metal electrode adopt a Cr / Au stacked structure, where Cr is the bonding layer with a thickness of 10 nm and Au is the main conductive layer with a thickness of 60 nm. The two electrodes are formed at both ends of the two-dimensional semiconductor channel sheet and form an ohmic contact. The channel length is 5 μm and the width is 10 μm.

[0090] Step eight is the same as the operation in Example 1.

[0091] Example 4:

[0092] This embodiment fabricates a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction. Its fabrication process is basically the same as in Example 1, except that:

[0093] In step one, the first flexible layer is polyamic acid with a thickness of 200 nm and a drying temperature of 100 °C; the second flexible layer is polyimide (PI) and is cured using a gradient temperature curing process, with a thickness of 10 μm after curing.

[0094] In step two, the bottom gate metal electrode adopts a Cr / Au stacked structure and is deposited by magnetron sputtering; Cr is the binder layer with a thickness of 5nm, and Au is the main conductive layer with a thickness of 30nm.

[0095] In step three, atomic layer deposition (ALD) is used with TDMAHf, TDMAZr, and water as precursors to grow a 15 nm thick hafnium zirconium oxide (HZO) ferroelectric thin film at a deposition temperature of 250 °C. Subsequently, rapid thermal annealing at 450 °C for 40 s is performed under a nitrogen protective atmosphere to induce crystallization of the hafnium zirconium oxide ferroelectric thin film to form an orthorhombic ferroelectric phase, thus obtaining a ferroelectric dielectric thin film layer.

[0096] In step four, the metal floating gate island is a Pt nanofilm with a thickness of 3 nm, which is deposited using an electron beam evaporation process.

[0097] In step five, the ultrathin tunneling dielectric layer is hafnium dioxide (H2O). A thin film with a thickness of 5 nm was deposited at 200°C using atomic layer deposition.

[0098] In step six, the two-dimensional semiconductor wafer is a few-layer wafer. Thin sheets (usually 1-4 layers) are transferred using PDMS-assisted dry transfer technology; after transfer, they are annealed in an argon atmosphere at 180℃ for 2 hours to eliminate interfacial residues and gas adsorption.

[0099] In step seven, both the source metal electrode and the drain metal electrode adopt a Cr / Au stacked structure, where Cr is the bonding layer with a thickness of 10nm and Au is the main conductive layer with a thickness of 50nm. The two electrodes are formed at both ends of the two-dimensional semiconductor channel sheet and form an ohmic contact. The channel length is 5μm and the width is 10μm.

[0100] Step eight is the same as the operation in Example 1.

[0101] For the devices fabricated in the above embodiments, when a scan voltage of ±3V is applied to the bottom gate, the devices exhibit greater than It has a high and low conductivity ratio, a clear storage window and ferroelectric hysteresis characteristics; when a continuous weak electrical pulse is applied to the gate, the floating gate capture charge exhibits good linear gain and attenuation, and has excellent synaptic integral characteristics.

[0102] The device was attached to a bending die with a radius of 1.5 mm and bent repeatedly for 3000 times. The device's transfer characteristic curve, switching ratio and storage window showed no significant attenuation, demonstrating excellent bending reliability and mechanical stability.

[0103] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A fabrication process for a flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction, characterized in that, Includes the following steps: Step 1: The first flexible layer and the second flexible layer are spin-coated sequentially on the surface of the rigid glass substrate, and then baked and cured to form a double-layer flexible substrate; Step 2: Define the bottom gate pattern on the double-layer flexible substrate using photolithography, deposit a metal layer, and then form the bottom gate metal electrode using a lift-off process (2); Step 3: Using atomic layer deposition technology, a hafnium zirconium oxide ferroelectric thin film is deposited on the bottom gate metal electrode (2) and the surface of the double-layer flexible substrate; then, rapid thermal annealing is performed under a nitrogen protective atmosphere to induce the hafnium zirconium oxide ferroelectric thin film to crystallize and form an orthogonal ferroelectric phase, thus obtaining a ferroelectric dielectric thin film layer (3); Step 4: Define the floating gate region through photolithography, deposit a nanoscale metal thin film, and then form a metal floating gate island (4) on the surface of the ferroelectric thin film layer (3) through a lift-off process; Step 5: Using atomic layer deposition technology, a hafnium dioxide film is deposited on the surface of the metal floating gate island (4) and the ferroelectric dielectric thin film layer (3) to form an ultrathin tunneling dielectric layer (5) covering the metal floating gate island (4); Step 6: Transfer the two-dimensional semiconductor wafer to the surface of the ultrathin tunneling dielectric layer (5), remove the interface residue by annealing and perform patterning to form a two-dimensional semiconductor channel wafer (6); Step 7: Align the two ends of the channel and define the source and drain regions through photolithography. After depositing the metal layer, form the source metal electrode (7) and drain metal electrode (8) with ohmic contact at both ends of the two-dimensional semiconductor channel sheet (6) through a lift-off process. Step 8: The flexible chip containing the first flexible layer, the second flexible layer and the complete device structure is peeled off from the glass substrate without damage to obtain an independent flexible ferroelectric floating gate transistor; the first flexible layer and the second flexible layer together serve as a flexible polymer substrate film (1).

2. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 1, characterized in that, In step one, the first flexible layer is water-soluble polyvinyl alcohol or polyamic acid, with a thickness of 150~300nm and a drying temperature of 80~120℃; the second flexible layer is polyimide, with a thickness of 8~15μm after curing.

3. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 1, characterized in that, In step two, the bottom gate metal electrode (2) adopts a Cr / Au stacked structure and is deposited by electron beam evaporation or magnetron sputtering process; wherein Cr is the binder layer with a thickness of 3~10nm and Au is the main conductive layer with a thickness of 20~60nm.

4. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 1, characterized in that, In step three, hafnium zirconium oxide is ; The precursors for atomic layer deposition are TDMAHf, TDMAZr, and The deposition temperature is 220~280℃, and the thickness of the deposited film is 10~20nm; the rapid thermal annealing temperature is 400~500℃, and the annealing time is 30~60s.

5. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 1, characterized in that, In step four, the metal floating island (4) is a Pt nanofilm with a thickness of 2~5nm, which is deposited by electron beam evaporation process.

6. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 1, characterized in that, In step five, the ultrathin tunneling dielectric layer (5) is Thin films with a thickness of 3-8 nm are deposited using atomic layer deposition at 180-220°C.

7. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 1, characterized in that, In step six, the two-dimensional semiconductor wafer consists of 1 to 4 layers. Thin sheets were transferred using PDMS-assisted dry transfer technology; after transfer, they were annealed in an argon atmosphere at 160~200℃ for 1~3h to eliminate interfacial residues and gas adsorption.

8. The fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction according to claim 2, characterized in that, In step eight, the first flexible layer is naturally detached from the surface of the rigid glass substrate by immersion in warm water.

9. A flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction, characterized in that, Fabricated using the fabrication process of the flexible ferroelectric floating gate transistor based on a two-dimensional ultrathin heterojunction as described in any one of claims 1-8, comprising: Flexible polymer substrate thin film (1); The bottom gate metal electrode (2) is formed on the upper surface of the flexible polymer substrate thin film (1); A ferroelectric dielectric thin film layer (3) is covered on the upper surface of the bottom gate metal electrode (2) and the flexible polymer substrate thin film (1) to provide ferroelectric polarization control; Metal floating islands (4) are located in a predetermined area on the upper surface of the ferroelectric thin film layer (3) and are used to capture and store charges; An ultrathin tunneling dielectric layer (5) is coated with a metal floating gate island (4) and deposited on the upper surface of a ferroelectric dielectric thin film layer (3) to provide charge tunneling and blocking functions. A two-dimensional semiconductor channel thin film (6) is located on the upper surface of the ultrathin tunneling dielectric layer (5) and serves as the semiconductor channel of the transistor; The source metal electrode (7) and drain metal electrode (8) are located at both ends of the two-dimensional semiconductor channel sheet (6) and form an ohmic contact.

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