Method for manufacturing power device cell structure, power device

Abstract

This application relates to a method for fabricating a cell structure of a power device and a power device. The method includes: providing a substrate; the substrate includes a base region disposed near a first surface of the substrate, and the orthographic projection of the first surface is in the shape of a "well" shaped grid, and a source region whose top surface is located within the top surface of the base region; forming a split gate and doped regions that penetrate the base region along a direction toward the substrate and are alternately arranged at intervals along a first direction; doped pillars are disposed one-to-one on the bottom surface of the split gate; the conductivity type of the doped pillars and doped regions is opposite to the conductivity type of the substrate; forming a metal layer on the first surface and the outer surface of the split gate, the metal layer including a first extension in contact with the exposed top surface of the substrate and a second extension in contact with the doped regions; wherein the split gate includes a core conductive layer whose top surface is higher than the first surface and extends toward the first extension along the first direction, and a dielectric region surrounding the outer surface of the core conductive layer; at least significantly densifying the channel and obtaining a lower on-resistance.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for fabricating a power device cell structure and a power device. Background Technology

[0002] With the continuous development of modern electronic technology, higher requirements are being placed on semiconductor materials, especially in fields such as high voltage, high frequency, high power, high temperature, and radiation resistance. Silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] With the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of the physical size of devices has driven the continuous reduction of the design pitch of their cells. The size of planar cells has approached the process limit, while trench cell designs have problems such as reliability and high on-resistance at high temperatures. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the technical problems in the prior art, which can at least significantly densify the channel while reducing the gate-source capacitance, thereby increasing the switching speed.

[0005] In a first aspect, this application provides a method for fabricating a power device cell structure, comprising:

[0006] A substrate is provided; the substrate includes a base region disposed near a first surface of the substrate, and the orthographic projection of the first surface is in the shape of a grid, and a source region with its top surface located within the top surface of the base region;

[0007] A split gate and a doped region are formed, which penetrate the base region in a direction toward the substrate and are alternately arranged at intervals in a first direction parallel to the first surface; a doped pillar is provided one-to-one on the bottom surface of the split gate; the conductivity type of the doped pillar and the doped region is opposite to the conductivity type of the substrate.

[0008] A metal layer is formed on the first surface and the outer surface of the split gate. The metal layer includes a first extension that contacts the exposed top surface of the substrate and a second extension that contacts the doped region. The split gate includes a core conductive layer whose top surface is higher than the first surface and extends toward the first extension in a first direction, and a dielectric region surrounding the outer surface of the core conductive layer.

[0009] In some embodiments, doped regions and doped pillars are prepared simultaneously in the same process steps.

[0010] In some embodiments, forming a doped pillar includes:

[0011] Etch the substrate to form a gate trench that penetrates the base region along the direction toward the substrate;

[0012] A shielding region surrounding the interface between the gate trench and the substrate is formed using a high-energy ion implantation process.

[0013] After tilting the substrate by 4°, room temperature ion implantation is performed on the bottom of the gate trench to form a doped pillar at the bottom of the gate trench by utilizing the channel effect.

[0014] Ion implantation is used to form a doped region that extends through the base region.

[0015] In some embodiments, the dielectric region includes: a gate oxide layer;

[0016] Forming a split gate includes:

[0017] A gate oxide layer is formed covering the first surface and the inner surface of the gate trench;

[0018] A conductive material layer is formed that fills the gate trench and covers the gate oxide layer, with its top surface being higher than the first surface by a predetermined thickness.

[0019] A core conductive layer and a first dielectric layer are formed, which surround the core conductive layer and are in contact with a portion of the gate oxide layer; the core conductive layer is spaced within the gate trench.

[0020] In some embodiments, the metal layer further includes:

[0021] The third extension, located within the first dielectric layer between adjacent core conductive layers, extends in the direction toward the substrate to form an electrical contact with the doped pillar.

[0022] In some embodiments, the medium region further includes:

[0023] The second dielectric layer is located inside the core conductive layer. Its top surface is located between the top surface of the core conductive layer and the first surface, and its bottom surface is flush with the bottom surface of the source region. The orthographic projection of the source region near the first extension on the first surface is located within the orthographic projection of the second dielectric layer on the first surface.

[0024] The third dielectric layer is located between the first dielectric layer and the first surface and is in contact with the first extension.

[0025] In some embodiments, the metal layer further includes:

[0026] The third extension is disposed at intervals in the first dielectric layer between adjacent core conductive layers along the second direction, and extends in the direction toward the substrate to form an electrical contact with the doped pillar;

[0027] The second direction is perpendicular to the first direction.

[0028] In some embodiments, a first extension and a second extension are formed, including:

[0029] After the first dielectric layer is formed, the first dielectric layer is etched to form first contact holes that extend along the second direction and are spaced apart along the first direction; the bottom surface of the first contact holes is lower than the first surface.

[0030] The first dielectric layer located on the top surface of the doped region is etched back to expose part of the top surface of the source region, thereby increasing the width of the first contact hole and obtaining the second contact hole;

[0031] A metal layer is formed, wherein the metal layer located in the first contact hole constitutes the first extension and the metal layer located in the second contact hole constitutes the second extension.

[0032] In some embodiments, the bottom surface of the doped region is not lower than the bottom surface of the source region.

[0033] Secondly, this application provides a power device comprising: a cellular structure prepared by any of the above-described methods.

[0034] The embodiments of this application may / at least have the following unexpected technical effects:

[0035] In the cell structure provided in this application, by setting the base region in a "well" shape layout on the first surface, and combining it with the split gate structure that is alternately arranged along the first direction and penetrates the base region, the base region and source region on both sides of each split gate can independently form a conductive channel. Electrons can flow bidirectionally laterally down into the substrate to complete the current path. With the conductive path formed by the planar gate channel, three sets of parallel conductive current paths are formed simultaneously under the same cell pitch, thereby achieving a doubling of channel density.

[0036] Meanwhile, the doped pillars arranged one-to-one on the bottom surface of the split gate and the lightly doped epitaxial layer in the substrate form a superjunction structure. This allows for a higher doping concentration in the drift region while maintaining the breakdown voltage, further reducing the on-resistance. Moreover, the doped pillars are compatible with the base region implantation process, eliminating the need for an additional photolithography layer and reducing process complexity. The outer surface of the core conductive layer is surrounded by a dielectric region, effectively reducing the overlap area between the gate and drain regions, lowering the gate-source capacitance and gate-drain capacitance, and shortening the gate charging and discharging time, thereby improving the switching speed and reducing switching losses.

[0037] Based on this, the second extension in the metal layer that contacts the exposed top surface of the substrate directly forms a Schottky junction, which preferentially conducts during device switching, thereby achieving a better forward voltage drop V at the device level. f With its reverse recovery characteristics, it makes up for performance shortcomings. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A schematic diagram of the structure of a pair of transistors provided in the example;

[0040] Figure 2 This is a schematic diagram of the fabrication method of the power device cell structure provided in Embodiment 1 of this application;

[0041] Figure 3 This is a cross-sectional schematic diagram of the substrate structure provided in Embodiment 1 of this application;

[0042] Figure 4 This is a cross-sectional schematic diagram of the structure obtained after forming a base region and a source region in the substrate as provided in Embodiment 1 of this application;

[0043] Figure 5 This is a cross-sectional schematic diagram of the structure obtained after step S201 in Embodiment 1 of this application;

[0044] Figure 6 This is a cross-sectional schematic diagram of the structure obtained after step S202 in Embodiment 1 of this application;

[0045] Figure 7 This is a cross-sectional schematic diagram of the structure obtained after step S203 in Embodiment 1 of this application;

[0046] Figure 8 This is a cross-sectional schematic diagram of the structure obtained after step S204 in Embodiment 1 of this application;

[0047] Figure 9 This is a cross-sectional schematic diagram of the structure obtained after step S205 in Embodiment 1 of this application;

[0048] Figure 10 This is a cross-sectional schematic diagram of the structure obtained after step S301 in Embodiment 1 of this application;

[0049] Figure 11 This is a cross-sectional schematic diagram of the structure obtained after step S302 in Embodiment 1 of this application;

[0050] Figure 12 This is a cross-sectional schematic diagram of the structure obtained after step S303 in Embodiment 1 of this application;

[0051] Figure 13This is a schematic diagram of the electron flow of the cellular structure obtained using the preparation method provided in Example 1;

[0052] Figure 14 This is a cross-sectional schematic diagram of the structure obtained after step S205 in Embodiment 2 of this application;

[0053] Figure 15 This is a cross-sectional schematic diagram of the structure obtained after step S206 in Embodiment 2 of this application;

[0054] Figure 16 This is a cross-sectional schematic diagram of the structure obtained after step S207 in Embodiment 2 of this application;

[0055] Figure 17 This is a schematic diagram of the cellular structure obtained using the preparation method provided in Example 2 of this application.

[0056] Explanation of reference numerals in the attached figures:

[0057] 10. Substrate; 101. Base; 102. Buffer layer; 103. Epitaxial layer; 21. Base region; 22. Source region; 23. Shielding region; 24. Doped pillar; 25. Doped region; 300. Gate trench; 30. Split gate; 31. Core conductive layer; 311. Conductive material layer; 32. Dielectric region; 320. Gate oxide layer; 321. First dielectric layer; 322. Second dielectric layer; 323. Third dielectric layer; 40. Metal layer. Detailed Implementation

[0058] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0060] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0061] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0062] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0063] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0064] Figure 1 For a composite transistor structure provided in a pair ratio, such as Figure 1 As shown, the cell structure includes spaced-apart composite gates, each containing interconnected and perpendicular trench gates and planar gates. To improve gate reliability, a shielding region surrounding the interface between the composite gate and the substrate is provided at the lower right of the composite gate. While this structure can densify the channel to some extent, it still suffers from problems such as planar channels being effective only on one side, deep P-pillars occupying layout space, difficulty in miniaturizing cell pitch, poor parasitic diode performance, and gate-source capacitance Cgs, which limit the device's power and high-frequency performance.

[0065] Example 1

[0066] Based on this, please refer to Figure 2 This embodiment provides a method for fabricating a power device cell structure, including steps S1-S3. For ease of understanding, in this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and directions toward the substrate include a third direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and second directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the Y-axis direction, the second direction as the X-axis direction, and the third direction as the Z-axis direction.

[0067] The following is combined with Figures 3-13 The following details the steps involved in fabricating the power device cell structure according to this embodiment. It should be noted that the films shown in the accompanying drawings as rectangles or other shapes are for illustrative purposes only and are not drawn to the actual scale of the device; they are merely illustrative examples.

[0068] Please see Figures 3-4 Step S1: Provide a substrate 10; the substrate 10 includes a base region 21 disposed near a first surface 10a of the substrate, and the orthographic projection of the first surface 10a is a "well" shape, and a source region 22 whose top surface is located within the top surface of the base region 21.

[0069] To clearly demonstrate the cellular structure provided in this embodiment, Figure 3 Image (a) shows a top view of the semiconductor structure. Figure 3 (b) in the figure is a cross-sectional view of the cell structure along line A-A'. Figure 3 (c) in the figure is a cross-sectional view of the cell structure along line B-B'. Figure 3 (d) is a cross-sectional view of the cell structure along line C-C'. It should be understood that (a)-(d) in other views also correspond to the top view, line A-A', line B-B' and cross-sectional views of the device in the corresponding steps, respectively. The following steps will not repeat the explanation.

[0070] For example, in this embodiment, the cross-sectional width (dimension along the OX direction) along line A-A' is 2μm, and the cross-sectional width (dimension along the OX direction) along line BB is 2μm, in order to obtain the best effect of densified channel and avoid the problem of excessive cross-sectional width along line BB leading to a large proportion of source region resistance.

[0071] like Figure 3 As shown, the substrate 10 includes a heavily doped N+ substrate 101, an N+ buffer layer 102, and a lightly doped N- epitaxial layer 103 arranged sequentially along the OZ direction. In this embodiment, the typical concentration of the substrate 101 is 1e20cm³. -3 The typical concentration of buffer layer 102 is 1e18cm. -3 The typical concentration of the epitaxial layer 103 is 5e16cm. -3 This is beneficial for achieving a lower MOSFET on-resistance Ron while maintaining the device's voltage rating.

[0072] The steps for forming the base region 21 and the source region 22 include, through photolithography and ion implantation processes, sequentially employing P-type and N-type impurity elements to obtain, as shown below. Figure 4 As shown, the base region 21 and source region 22 are arranged in a grid pattern. The source region 22 can be formed within the base region 21 using a self-aligned process to save one layer of photomask.

[0073] For example, the doping concentration of base region 21 is 1e17cm. -3 ~5e18cm -3 For example, 2e17cm -3 5e17cm -3 Or 5e18cm -3The injection depth is approximately 0.3μm to 1μm, for example, 0.3μm, 0.5μm, 0.7μm or 0.1μm.

[0074] For example, the doping concentration of source region 22 is 1e19cm. -3 ~5e20cm -3 For example, 1e19cm -3 1e20cm -3 Or 5e20cm -3 The injection depth is approximately 0.02μm to 0.3μm, for example, 0.02μm, 0.04μm, 0.06μm, 0.08μm or 0.1μm.

[0075] In this embodiment, the doping concentration of the base region 21 is 1e18cm. -3 The implantation depth is 0.8 μm. The doping concentration of source region 22 is 1.5e20cm. -3 The injection depth was 0.15 μm.

[0076] It is important to note that although both base region 21 and source region 22 are located within the substrate, for the sake of clarity in describing the positional relationship and contact type of each region, "exposed top surface of the substrate" refers to the area on the top surface of the substrate that has not undergone ion implantation to form the base and source regions. That is, this area remains the original semiconductor material surface of the epitaxial layer (lightly doped drift region) of the substrate, rather than a surface covered with an implanted doped layer or dielectric layer. The first surface 10a includes the top surface of the source region 22 and the top surface of the area that has not undergone ion implantation.

[0077] Please see Figures 5-10 Step S2: Form a split gate and a doped region that penetrate the base region 21 along the OZ direction and are alternately arranged along the OY direction; a doped pillar is provided on the bottom surface of the split gate one by one; the conductivity type of the doped pillar and the doped region is opposite to the conductivity type of the substrate 10.

[0078] The extension step S2 also includes:

[0079] Step S201: Using photolithography and etching processes, a gate trench is formed in the substrate 10, penetrating the base region 21 along the OZ direction and with a width smaller than that of the base region 21, as shown in the following figure. Figure 5 As shown.

[0080] For example, the width ranges from 0.5 to 1.5 μm (e.g., 0.5 μm, 1 μm, or 1.5 μm, etc.), and the depth ranges from 0.5 to 1.2 μm (e.g., 0.5 μm, 1 μm, or 1.2 μm, etc.). In this embodiment, the typical values ​​for the width and depth of the gate trench are 2 μm and 1 μm, respectively.

[0081] Step S202: Using a high-current equipment and a high-energy ion implantation process, a shielding region 23 is formed around the interface between the gate trench and the substrate 10. After tilting the substrate 10 at 4°, room-temperature P+ ion implantation is performed on the bottom of the gate trench. Utilizing the channel effect, a doped pillar 24 is formed at the bottom of the gate trench, specifically as follows... Figure 6 As shown.

[0082] For example, the doping concentration of the shielding region 23 is 1e20cm. -3 ~1e21cm -3 For example, 1e20cm -3 5e20cm -3 or 1e21cm -3 The implantation depth of the shielding region 23 is approximately 0.3 μm. In this embodiment, the doping concentration of the shielding region 23 is 4e20cm. -3 .

[0083] For example, the doping concentration of doped column 24 is 2e16cm. -3 ~5e19cm -3 For example, 2e16cm -3 2e17cm -3 2e18cm -3 2e19cm -3 Or 5e19cm -3 In this embodiment, the doping concentration of the doped column 24 is 1e17cm. -3 .

[0084] In the above structure, each doped pillar 24 can form a superjunction unit with the surrounding epitaxial layer 103, and these units are arranged alternately throughout the device. When a voltage is applied, the depletion layer expands horizontally and quickly merges to form a depletion layer with the same depth as the doped pillar. This structural design allows current to flow through a lower resistance path in the on-state, while still being able to withstand high voltages in the off-state. The superjunction MOSFET breaks through the material limitations of traditional high-voltage power MOSFETs, allowing for a significant increase in the doping concentration of its n-voltage support layer and a substantial reduction in on-resistance under the same breakdown voltage conditions. This helps to reduce power loss and improve efficiency.

[0085] Step S203: Using an ion implantation process, a doped region 25 is formed located in the base region 21, specifically as follows... Figure 7 As shown. After all injections are completed, high-temperature annealing is performed to activate the impurities. The process conditions are 1750°C, 30 min, and Ar atmosphere. Since this is not the focus of this embodiment, it will not be described further.

[0086] For example, the doping concentration of doped region 25 is 1e20cm. -3 ~1e21cm-3 For example, 1e20cm -3 5e20cm -3 or 1e21cm -3 The typical implantation depth is approximately 0.5~1.5 μm, for example, 0.5 μm, 1 μm, or 1.5 μm. In this embodiment, the typical doping concentration is 3e20 cm⁻¹. -3 The depth can exceed the depth of base region 21, and it can also be like... Figure 7 As shown, the bottom surface is flush with the bottom surface of the base area 21.

[0087] Step S204: Using any oxidation process (e.g., thermal oxidation or high-temperature oxidation), a gate oxide layer 320 is formed covering the gate trench 300 and the first surface 10a to improve the flatness of the sidewalls of the gate trench 300 and reduce the interface states. Then, using any deposition process, a conductive material layer 311 is first formed to fill the gate trench 300 and the first surface 10a, with the specific structure as follows: Figure 8 As shown.

[0088] For example, the thickness of the gate oxide layer 320 is 40nm~50nm, such as 40nm, 45nm or 50nm.

[0089] For example, the conductive material layer 311 is about 300 nm to 400 nm above the first surface 10a, such as 300 nm, 350 nm or 400 nm.

[0090] Step S205: Etch back the conductive material layer, so that the remaining conductive material layer forms a spaced core conductive layer 31 within the gate trench, extending along the OY direction to partially cover the top surface of the base region 21. Subsequently, a first dielectric layer 321 is formed to fill the gaps and cover the first surface 10a. The first dielectric layer 321 and the gate oxide layer 320 together constitute the dielectric region 32, and the remaining conductive material layer constitutes the core conductive layer 31, as shown in the specific structure. Figure 9 As shown.

[0091] For example, the first dielectric layer 321 includes, but is not limited to, one or more high dielectric materials, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0092] In the above structure, the split gate minimizes the parasitic gate-source capacitance Cgs and gate-drain capacitance Cgd, resulting in comprehensive optimization of dynamic performance. It should be noted that in actual manufacturing processes, due to limitations in photolithography alignment accuracy, there is a certain overlay deviation between the orthographic projection of the core conductive layer 31 onto the top surface of the substrate and the orthographic projection of the base region 21 onto the top surface of the substrate. Therefore, Figures 9 to 13 In the structure shown, the core conductive layer 31 does not exactly and completely cover the base region 21, but exhibits a relative offset due to process tolerances. This deviation does not change the core structural layout and conduction mechanism of this application. Those skilled in the art should understand that, within the allowable overlay accuracy range of the process, this offset does not affect the realization of the device function.

[0093] Please see Figures 10-12 Step S3: A metal layer 40 is formed on the first surface 10a and the outer surface of the split gate 30. The metal layer includes a second extension in contact with the doped region and a first extension in contact with the exposed top surface of the substrate.

[0094] Step S3 includes the following steps:

[0095] Step S301: Etch the first dielectric layer 321 to form first contact holes extending along the OX direction and spaced apart along the OY direction on the exposed surfaces of the doped region 25 and the substrate 10. The width of the first contact holes is the same as that of the doped region 25, and the specific structure is as follows. Figure 10 As shown.

[0096] Step S302: While forming the third contact hole in the first dielectric layer 321 between adjacent core conductive layers 31, the first contact hole located above the doped region 25 is laterally supplemented by etching to increase the width and depth of this portion of the first contact hole, thereby obtaining the second contact hole. The second contact hole passes through the source region 22 and contacts the base region 21. Due to the increased width, the ohmic contact area between the metal layer 40 subsequently filled within it and the top surface of the source region 22 is increased. At the same time, the bottom of the second contact hole is embedded in the base region 21, forming a reliable grounding contact with the base region 21. The bottom of the third contact hole exposes the top surface of the shielding region 23. The specific structure is as follows: Figure 11 As shown.

[0097] Step S303: Form a metal layer 40, which covers the first surface 10a. The metal layer located in the first contact hole forms a first extension, the metal layer located in the second contact hole forms a second extension, and the metal layer located in the third contact hole forms a third extension. The specific structure is as follows: Figure 12 As shown.

[0098] In the above structure, the third extension forms an electrical contact with the doped pillar 24, the first extension forms a Schottky contact with the lightly doped substrate 10, the second extension forms an ohmic contact with the doped region 25, and forms a PIN structure with the epitaxial layer 103, the buffer layer 102, and the substrate 101. A Schottky diode is added inside the superjunction device to suppress the turn-on of the parasitic PiN diode, thereby obtaining a better forward voltage drop V at the device level. fWith its reverse recovery characteristics, PiN diodes compensate for performance shortcomings. They are used solely to conduct large currents through conductivity modulation during surge current impacts, thus improving the device's surge resistance.

[0099] Following step S3, the fabrication method further includes backside thinning and metallization processes, which are conventional MOSFET processes and will not be described in detail here. The split gate 30 consists of alternating trench gates and planar gates along the OX direction. Figure 13 The current flow direction of the semiconductor structure provided in this embodiment 1 is shown. Path ① is the channel electron flow direction along the split gate line A-A', path ② is the electron conduction path that first flows through the source region of path ① and then through the trench sidewall channel, and path ③ is the planar channel electron flow direction along the split gate line B-B'. Through the coordinated conduction of the above three paths, the current transport capability and conduction efficiency of the device can be effectively improved.

[0100] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0101] Example 2

[0102] Please see Figures 14-17 This embodiment provides another method for preparing the cell structure of a power device. The main difference from Embodiment 1 is that after forming the conductive material layer in step S2, it also includes forming a second dielectric layer 322 and a third dielectric layer 323.

[0103] Steps S201-S204 are the same as in Embodiment 1 and will not be described in detail here. In step S205, the conductive material layer 311 is etched back so that its top surface is as flush as possible with the bottom surface of the source region 22 or slightly higher than the bottom surface of the source region 22; subsequently, a second dielectric material layer covering the first surface 10a and the conductive material layer 311 is formed, with the specific structure as follows. Figure 14 As shown.

[0104] In step S206, the second dielectric material layer is etched to form a second dielectric layer 322 located within the core conductive layer 31, and a third dielectric layer 323 on the substrate between adjacent source regions 22, as shown in the specific structure. Figure 15 As shown.

[0105] For example, the second dielectric material layer may contain, but is not limited to, high-K materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), and tantalum pentoxide (Ta2O5).

[0106] In step S207, a secondary conductive material layer is deposited, covering the second dielectric layer 322, the third dielectric layer 323, and the top surface of the exposed gate oxide layer 320. Subsequently, the conductive material layer is etched back, so that the remaining conductive material layer forms a spaced core conductive layer 31 within the gate trench, extending along the OY direction to partially cover the surface of the base region 21, as shown in the specific structure. Figure 16 As shown.

[0107] In step S208, a first dielectric layer 321 is formed to fill the gap and cover the first surface 10a. The first dielectric layer 321, the second dielectric layer 322, the third dielectric layer 323 and the gate oxide layer 320 together constitute the dielectric region 32, and then the same step S301 as in Embodiment 1 is performed.

[0108] In step S302, the third contact holes are spaced apart along the OX direction within the first dielectric layer 321 between adjacent core conductive layers 31. After step S303 forms the metal layer 40, backside thinning and metallization are performed, resulting in the structure shown below. Figure 17 The source region 22 near the first extension has its orthographic projection on the first surface falling within the orthographic projection range of the second dielectric layer 322. The core conductive layer 31 and the source region 22 are separated in the OX, OY and OZ directions, further reducing the gate-source capacitance Cgs and optimizing the reliability problem of gate-source punch-through caused by process deviations to a certain extent.

[0109] The use of a high-K material in the third dielectric layer 323 can prevent adjacent core conductive layers 31 from penetrating each other; the spacing of the third extension can further reduce the gate-source capacitance Cgs based on Embodiment 1.

[0110] Example 3

[0111] The steps are basically the same as those in Example 1, except that in the same step of preparing the shielding region 23 in step S2, the doped region 25 is prepared at the same time to reduce the number of process steps and costs.

[0112] Example 4

[0113] This embodiment provides a power device comprising multiple cellular structures prepared using the method described in any of the above embodiments. In the power device, such as... Figure 17 Or such as Figure 13 The multiple cell structures shown are arranged sequentially along the OX and OY directions.

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A method for fabricating a power device cell structure, characterized in that, include: Provide substrate; The substrate includes a base region disposed near a first surface of the substrate, and the orthographic projection of the first surface is in the shape of a "well" shaped grid, and a source region whose top surface is located within the top surface of the base region; A split gate and a doped region are formed, which penetrate the base region in a direction toward the substrate and are alternately arranged at intervals in a first direction parallel to the first surface; a doped pillar is provided one-to-one on the bottom surface of the split gate; the conductivity type of the doped pillar and the doped region is opposite to the conductivity type of the substrate; A metal layer is formed on the first surface and the outer surface of the split gate. The metal layer includes a first extension that contacts the exposed top surface of the substrate and a second extension that contacts the doped region. The split gate includes a core conductive layer whose top surface is higher than the first surface and extends toward the first extension along the first direction, and a dielectric region surrounding the outer surface of the core conductive layer.

2. The preparation method according to claim 1, characterized in that, The doped region and the doped pillar are prepared simultaneously in the same process steps.

3. The preparation method according to claim 1, characterized in that, Forming the doped pillar and the doped region includes: The substrate is etched to form a gate trench that penetrates the base region along a direction toward the substrate; A shielding region surrounding the interface between the gate trench and the substrate is formed using a high-energy ion implantation process. After tilting the substrate by 4°, room temperature ion implantation is performed on the bottom of the gate trench to form the doped pillar at the bottom of the gate trench by utilizing the channel effect; Ion implantation is used to form a doped region that extends through the base region.

4. The preparation method according to claim 3, characterized in that, The dielectric region includes: a gate oxide layer; Forming the split gate includes: A gate oxide layer is formed covering the first surface and the inner surface of the gate trench; A conductive material layer is formed that fills the gate trench and covers the gate oxide layer, with its top surface being higher than the first surface by a predetermined thickness. The core conductive layer is formed and a first dielectric layer surrounds the core conductive layer and contacts a portion of the gate oxide layer; the core conductive layer is spaced within the gate trench.

5. The preparation method according to claim 4, characterized in that, The metal layer further includes: The third extension is located within the first dielectric layer between adjacent core conductive layers and extends in the direction toward the substrate to form an electrical contact with the doped pillar.

6. The preparation method according to claim 4, characterized in that, The medium region further includes: The second dielectric layer is located within the core conductive layer, with its top surface located between the top surface of the core conductive layer and the first surface, and its bottom surface flush with the bottom surface of the source region; the orthographic projection of the source region near the first extension on the first surface is located within the orthographic projection of the second dielectric layer on the first surface. The third dielectric layer is located between the first dielectric layer and the first surface and is in contact with the first extension.

7. The preparation method according to claim 6, characterized in that, The metal layer further includes: The third extension is disposed at intervals in the first dielectric layer between adjacent core conductive layers along the second direction, and extends in the direction toward the substrate to form an electrical contact with the doped pillar; The second direction is perpendicular to the first direction.

8. The preparation method according to claim 7 or 5, characterized in that, The first extension and the second extension include: After the first dielectric layer is formed, the first dielectric layer is etched to form first contact holes that extend along the second direction and are spaced apart along the first direction; the bottom surface of the first contact holes is lower than the first surface. The first dielectric layer located on the top surface of the doped region is etched back to expose part of the top surface of the source region, thereby increasing the width of the first contact hole and obtaining the second contact hole; The metal layer is formed such that the metal layer located in the first contact hole constitutes the first extension, and the metal layer located in the second contact hole constitutes the second extension.

9. The preparation method according to any one of claims 1-7, characterized in that, The bottom surface of the doped region is not lower than the bottom surface of the source region.

10. A power device, characterized in that, include: The cellular structure prepared by any one of claims 1-9.

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