Method for manufacturing a semiconductor device, electronic device

Abstract

The application relates to a semiconductor device manufacturing method and electronic equipment. The device comprises: providing a substrate; forming a plurality of doped columns and alternately arranged first base regions and second base regions in contact with the sidewalls of the doped columns in the substrate; wherein the width of the first base regions is greater than that of the second base regions and equal to the spacing between adjacent doped columns; forming a gate trench penetrating the first base regions and the second base regions; the gate trench extends in a first direction to partially embed the doped columns; forming a gate structure in the gate trench; the top surface of the gate structure is higher than the top surface of the substrate and comprises a conductive part arranged at intervals in a second direction and covering the second base regions; forming an interlayer dielectric layer covering the gate structure and a metal plug between adjacent interlayer dielectric layers; the metal plug is in contact with the top surface of the first base regions, the top surface of the substrate between adjacent first base regions and part of the top surface of the doped columns in the second direction, which can significantly increase the channel density, obtain lower on-resistance and improve the dynamic characteristics of the device.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor device and an electronic device. Background Technology

[0002] With the continuous development of modern electronic technology, higher requirements are being placed on semiconductor materials, especially in fields such as high voltage, high frequency, high power, high temperature, and radiation resistance. Silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] With the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of the physical size of devices has driven the continuous reduction of the design pitch of their cells. The size of planar cells has approached the process limit, while trench cell designs have problems such as reliability and high on-resistance at high temperatures. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for fabricating semiconductor devices and electronic devices that can at least significantly improve the channel density and enhance the dynamic characteristics of the devices, addressing the technical problems in the existing technology.

[0005] In a first aspect, this application provides a method for fabricating a semiconductor device, comprising:

[0006] Provide substrate;

[0007] A plurality of doped pillars are formed in the substrate at intervals along a first direction and extending along a second direction, and a first base region and a second base region are alternately arranged along the second direction in contact with the sidewalls of the doped pillars; wherein the width of the first base region is greater than that of the second base region and equal to the spacing between adjacent doped pillars.

[0008] A gate trench is formed that penetrates the first base region and the second base region along a third direction; the gate trench extends along a first direction to partially embed the doped pillar;

[0009] A gate structure is formed within a gate trench, and a first isolation layer is embedded within the gate structure; the top surface of the gate structure is higher than the top surface of the substrate, and includes conductive portions spaced along a second direction that cover a second base region; the first isolation layer extends along the second direction, and its maximum width within the gate trench is less than half the width of the gate trench; the width is used to characterize the dimension along the first direction.

[0010] An interlayer dielectric layer covering the gate structure is formed, and a metal plug is located in the adjacent interlayer dielectric layer; the metal plug is in contact with the top surface of the first base region, the top surface of the substrate between adjacent first base regions, and a portion of the top surface of the doped pillar along the second direction.

[0011] In some embodiments, the first base region includes a first source region extending inwardly through the top surface of the first base region;

[0012] The second base region includes a second source region disposed near the conductive portion; the width of the second source region is smaller than that of the second base region.

[0013] In some embodiments, forming a second source region and a first source region includes:

[0014] An initial base region and an initial source region are sequentially formed within the substrate; the orthographic projections of the initial base region and the initial source region onto the top surface of the substrate are both in a grid pattern; the top surface of the initial source region is located inside the top surface of the initial base region;

[0015] A multi-step ion implantation process is performed on the initial base region, the initial source region, and the substrate between adjacent initial base regions to form multiple doped pillars; the remaining initial source regions constitute the first source region and the second source region.

[0016] In some embodiments, performing a multi-step ion implantation process includes:

[0017] A high-energy ion implantation process is used to form an initial doped pillar that penetrates the source region along a third direction and extends into the base region or substrate;

[0018] The substrate is tilted at 4° and a room temperature ion implantation process is performed to deepen the initial doped pillars by utilizing the channel effect.

[0019] In some embodiments, forming the first isolation layer further includes:

[0020] A gate oxide layer and a first polysilicon layer with a top surface lower than the first source region and the second source region are sequentially formed in the gate trench;

[0021] A first isolation layer is formed on the top surface of the first polysilicon layer on the side away from the doped pillar, and a second isolation layer is formed on the top surface of the substrate and the top surface of the doped pillar between the second base region and the first base region; the first isolation layer covers the top surface of the second source region.

[0022] In some embodiments, forming a conductive portion includes:

[0023] A second polysilicon layer is formed on the top surface of the exposed first polysilicon layer and the top surface of the first isolation layer; wherein the second polysilicon layer located directly above the second base region is used to form a conductive part, and the conductive part surrounds the outer surface of the first isolation layer.

[0024] In some embodiments, the gate oxide layer extends along the inner surface of the gate trench and in a first direction to beneath the interlayer dielectric layer.

[0025] The second isolation layer is located between the interlayer dielectric layer and the gate oxide layer.

[0026] In some embodiments, the ratio of the length of the first base region to the length of the second base region is 1:1.

[0027] In some embodiments, the preparation method includes at least one of the following technical features;

[0028] The substrate includes a base, a buffer layer, and an epitaxial layer arranged sequentially in a direction opposite to a third direction;

[0029] The conductivity type of the substrate is opposite to that of the doped pillars, the first base region, and the second base region, but the same as that of the first source region and the second source region.

[0030] The first and second isolation layers consist of materials with high dielectric constants.

[0031] Secondly, this application also provides an electronic device, including a semiconductor device fabricated using the fabrication method described in any of the above embodiments.

[0032] The embodiments of this application may / at least have the following unexpected technical effects:

[0033] In the fabrication method provided in this application, doped pillars are formed in the substrate at intervals, and first and second base regions with different widths are arranged alternately, so that the doped pillars and the substrate constitute a superjunction unit, and ground connection is achieved through the first base region; by forming a gate structure covering the second base region, the sidewall of the gate structure and the surface of the second base region form a parallel conductive channel, and the metal plug is made to contact the substrate in the gap between the first and second base regions to form a Schottky structure, thereby introducing an effective planar channel region and MPS structure on the device surface without increasing the cell pitch, significantly improving the effective channel density per unit area, and possessing excellent low reverse recovery characteristics and strong surge resistance.

[0034] The fabrication method provided in this application achieves a comprehensive improvement in channel densification, superjunction breakdown voltage, reverse recovery characteristics, and surge tolerance in the same fabrication process by synergistically limiting process steps such as doped pillar formation, differentiated base region layout, and gate structure spatial configuration. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of the structure of a pair of transistors provided in the example;

[0037] Figure 2 This is a schematic diagram of the fabrication method of the semiconductor device provided in the embodiments of this application;

[0038] Figure 3 This is a schematic diagram of the substrate structure in the preparation method provided in the embodiments of this application;

[0039] Figure 4 This is a schematic diagram of the structure obtained after forming the initial base region and the initial source region in the preparation method provided in the embodiments of this application;

[0040] Figure 5 for Figure 4 A schematic diagram of the structure obtained after the doped pillars are formed.

[0041] Figure 6 for Figure 5 A schematic diagram of the structure obtained after the grid trench is formed;

[0042] Figure 7 for Figure 6 The diagram shows the structure obtained after the gate oxide layer and the first polysilicon layer are formed.

[0043] Figure 8 for Figure 7 The diagram shows the structure obtained after the first and second isolation layers are formed.

[0044] Figure 9 for Figure 8 A schematic diagram of the structure obtained after the conductive part is formed in the structure shown;

[0045] Figure 10 for Figure 9 A schematic diagram of the structure obtained after the interlayer dielectric layer is formed in the structure shown;

[0046] Figure 11 for Figure 10 A schematic diagram of the structure obtained after the contact hole is formed in the structure shown;

[0047] Figure 12 for Figure 11 A schematic diagram of the structure obtained after the structure shown is formed into a metal plug;

[0048] Figure 13 This is a schematic diagram of the electron flow of a semiconductor device fabricated using the method provided in this application.

[0049] Explanation of reference numerals in the attached figures:

[0050] 100, Substrate; 110, Base; 120, Buffer layer; 130, Epitaxial layer; 140, Initial base region; 141, First base region; 142, Second base region; 150, Initial source region; 151, First source region; 152, Second source region; 160, Doped pillar; 170, Gate trench; 180, Gate oxide layer; 221, First isolation layer; 222, Second isolation layer; 200, Interlayer dielectric layer; 210, Metal plug. Detailed Implementation

[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0057] Figure 1 For a composite transistor structure provided in a pair ratio, such as Figure 1 As shown, the cell structure includes spaced-apart composite gates, each containing interconnected and perpendicular trench gates and planar gates. To improve gate reliability, a shielding region surrounding the interface between the composite gate and the substrate is provided at the lower right of the composite gate.

[0058] While the aforementioned structure can densify the channel to some extent, the P-pillars located between adjacent composite gates occupy layout space, making it difficult to miniaturize the cell pitch. Furthermore, the poor performance of parasitic diodes and the large MOS gate-source capacitance (Cgs) result in prolonged charging and discharging times, increased switching delay, and a surge in dynamic losses at high frequencies. Therefore, these issues need to be addressed and optimized.

[0059] To address the aforementioned problems, this application provides a method for fabricating a semiconductor device, the specific process of which is as follows: Figure 2 As shown. Figures 3 to 13 This is a cross-sectional schematic diagram of the semiconductor device corresponding to each process step in the embodiments of this application. For ease of understanding, in the embodiments of this application, the substrate may include a first surface located on the front side and a back surface opposite the front side, i.e., a second surface. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and directions toward the substrate include a third direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and second directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In the embodiments of this application, the first direction is defined as the Y-axis direction, the second direction as the X-axis direction, and the third direction as the Z-axis direction. The term "conductivity type" refers to the doping type of the semiconductor, including N-type and P-type.

[0060] The following is combined with Figures 3 to 13 The fabrication method of semiconductor devices includes the following steps:

[0061] First, step S100 is performed to provide substrate 100.

[0062] See Figure 3 A substrate 100 is provided. In this embodiment, the substrate 100 is a silicon carbide substrate, which is an epitaxial SiC material obtained through open market procurement. The substrate 100 includes, from bottom to top, an N+ substrate 110, an N+ buffer layer 120, and an N- epitaxial layer 130, each layer being N-type doped with nitrogen. The typical doping concentration of the substrate 110 is 1e20 cm⁻³, and the typical doping concentration of the buffer layer 120 is 1e18 cm⁻³. The epitaxial layer 130 is a lightly doped layer, denoted by N-, with a typical doping concentration of 5e16 cm⁻³. Figure 3 Image (a) shows a top view of the semiconductor structure. Figure 3 (b) in the figure is a cross-sectional view of the cell structure along line A-A'. Figure 3 (c) is a cross-sectional view of the cell structure along line B-B'. It should be understood that (a)-(c) in other views also correspond to the top view, line A-A', and line B-B' of the device in the corresponding steps, respectively. The following steps will not repeat the explanation.

[0063] It should be noted that the illustration only schematically shows one device unit region; in actual fabrication, the substrate 100 contains multiple arrayed device unit regions. The doping concentration values ​​in this embodiment are merely illustrative and can be adjusted according to actual device design requirements in other embodiments.

[0064] In this embodiment, the doping concentration of the epitaxial layer 130 is significantly higher than the drift region doping concentration (1e16cm) of conventional non-superjunction devices. -3 This allows for lower MOSFET on-resistance Ron while maintaining the device's voltage rating.

[0065] Next, step S102 is performed, in which a plurality of doped pillars 160 are spaced apart along the Y direction and extended along the X direction, and a first base region 141 and a second base region 142 are alternately arranged along the X direction in contact with the sidewalls of the doped pillars 160; wherein, the width of the first base region 141 is greater than that of the second base region 142, and is equal to the spacing between adjacent doped pillars 160.

[0066] Please see Figure 4 P-type initial base region 140 and N+ type initial source region 150 are injected into epitaxial layer 130.

[0067] The initial base region 140 was implanted with aluminum, with a doping concentration ranging from 1e17cm. -3 ~5e18cm -3 (For example, 2e17cm) -3 5e17cm -3 Or 5e18cm -3 The implantation depth is approximately 0.3 μm to 1.0 μm (e.g., 0.3 μm, 0.5 μm, 0.7 μm, or 1 μm). In this embodiment, the initial base region 140 has a doping concentration of 1e18 cm⁻³ and an implantation depth of 0.9 μm.

[0068] The implantation region of the initial source region 150 employs a self-aligned implantation process, which saves one photomask layer. The implanted element in the initial source region 150 is nitrogen, with a doping concentration of 1e19cm⁻¹. -3 ~5e20cm -3 (For example, 1e19cm) -3 5e19cm -3 1e20cm -3 Or 5e20cm -3 The implantation depth is approximately 0.02 μm to 0.3 μm (e.g., 0.02 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, or 0.3 μm, etc.). In this embodiment, the doping concentration of the initial source region 150 is 1.5e20cm.-3 The injection depth was 0.15 μm.

[0069] Please see Figure 5 An ion implantation process is performed on substrate 100 to form doped pillars 160.

[0070] In some embodiments, a multi-step ion implantation process is used to form the doped pillar 160. Specifically, a high-current ion implantation device can be used to implant shallow P+ at the boundary between the initial base region 140 and the unimplanted region to form the initial doped pillar. Aluminum is selected as the dopant element, and the doping concentration is 1e20cm. -3 ~1e21cm -3 (For example, 1e20cm) -3 5e20cm -3 or 1e21cm -3 The implantation depth is typically 0.5 μm to 1.5 μm (e.g., 0.5 μm, 1 μm, or 1.5 μm). In this embodiment, the typical doping concentration of the initial doped column is 3e20 cm⁻³, and the typical implantation depth is 1.3 μm.

[0071] Then, the wafer was tilted at 4° and ion implanted at room temperature to deepen the initial doped pillars using the channel effect, resulting in doped pillar 160. Aluminum was chosen as the dopant element, with a doping concentration of 6e16cm. -3 ~1e19cm -3 (For example, 1e16cm) -3 1e17cm -3 1e18cm -3 or 1e19cm -3 (etc.). In this embodiment, the typical doping concentration of the doped pillar 160 is 9e16 cm⁻³. The P-type doped pillar 160 and the N-type epitaxial layer 130 form multiple superjunction units arranged sequentially along the Y direction. When a voltage is applied, the depletion layer expands horizontally and quickly merges to form a depletion layer with the same depth as the superjunction pillar. This allows the doping concentration of the epitaxial layer 130 to be significantly increased and the on-resistance to be greatly reduced under the same breakdown voltage conditions. This helps to reduce power loss and improve efficiency.

[0072] At this point, the remaining initial base regions 140 constitute alternating first base regions 141 and second base regions 142 along the X direction. The sidewalls of the doped pillars 160 are in contact with the first base regions 141 and second base regions 142. The width of the first base region 141 is greater than that of the second base region 142, and the width of the first base region 141 is equal to the spacing between adjacent doped pillars 160 (i.e., connecting adjacent doped pillars 160). The remaining initial source regions 150 constitute a first source region located within the first base region and a second source region located within the second base region. The width of the cross-section along line B-B' determines the density of the subsequent planar gate channel. If the cross-section along line B-B' is too wide, the source region resistance ratio will be large; if the cross-section along line B-B' is too narrow, it will be no different from a conventional trench structure, failing to achieve the optimal effect of densifying the channel. In this embodiment, the typical ratio of the width of the cross-section along line A-A' to the width of the cross-section along line B-B' is set to 2μm:2μm, that is, the ratio of the length of the first base region 141 to the length of the second base region 142 is 1:1.

[0073] Please see Figure 6 Step S104 is executed to form a gate trench 170 that runs through the first base region 141 and the second base region 142 along the Z direction; the gate trench 170 extends along the Y direction to the partially embedded doped pillar 160.

[0074] A longitudinally penetrating gate trench 170 is etched in the first base region 141, the second base region 142, and the doped pillar 160. The width of the gate trench 170 ranges from 0.5 μm to 2.5 μm (e.g., 0.5 μm, 1 μm, 2 μm, or 2.5 μm), and the depth ranges from 0.5 to 1.2 μm (e.g., 0.5 μm, 0.7 μm, 0.9 μm, or 1.2 μm). In this embodiment, the typical values ​​for the width and depth of the gate trench 170 are 0.8 μm and 1.1 μm, respectively.

[0075] In this embodiment, the formed gate trenches 170 are arranged at intervals along the first direction X and extend along the second direction Y, with some doped pillars 160 embedded in them, and some sidewalls and bottom surfaces are surrounded by doped pillars 160, which alleviates the phenomenon of electric field concentration at the corners of the gate trenches.

[0076] Please see Figures 7-8 In step S106, a gate structure is formed in the gate trench 170, and a first isolation layer 221 is embedded in the gate structure. The top surface of the gate structure is higher than the top surface of the substrate 100 and includes conductive portions arranged at intervals along the X direction, covering the second base region 142. The first isolation layer 221 extends along the X direction, and its maximum width in the gate trench 170 is less than half the width of the gate trench 170.

[0077] First, after completing the aforementioned implantation process, the substrate 100 is subjected to high-temperature annealing to activate the implanted impurities. In this embodiment, the annealing conditions are 1750°C, 30 min, and an argon (Ar) atmosphere.

[0078] Next, a gate oxide layer 180 is grown on the inner surface of the gate trench 170 to make the sidewalls of the gate trench 170 smoother and reduce the interface state density. For example... Figure 7 The gate oxide layer 180 shown covers the bottom surface and sidewalls of the gate trench 170 and extends to the top surface of the substrate 100.

[0079] For example, the thickness of the gate oxide layer 180 is typically 40 nm to 50 nm (e.g., 40 nm, 45 nm, or 50 nm). In this embodiment, the thickness of the gate oxide layer 180 is 45 nm. The material of the gate oxide layer 180 includes, but is not limited to, silicon oxide (SiO2).

[0080] Then, a first polysilicon layer is formed within the gate trench 170. Polysilicon material is deposited on the side of the gate oxide layer 180 away from the substrate 100, filling the gate trench 170 and extending above the top surface of the substrate 100. Subsequently, the polysilicon material is etched back so that the bottom surface of the first polysilicon layer is flush with or slightly higher than the bottom surfaces of the first source region 151 and the second source region 152. The specific structure is as follows... Figure 7 As shown.

[0081] Further, please refer to Figure 8 A first isolation layer 221 is formed on the top surface of the first polysilicon layer on the side away from the doped pillar 160, covering the top surface of the second source region 152. A second isolation layer 222 is formed on the top surface of the substrate 100 between the second base region 142 and the first base region 141, and on a portion of the top surface of the doped pillar 160. The second isolation layer 222 and the first isolation layer 221 are fabricated simultaneously. The dimensions of the first isolation layer 221 along the X direction are the same as the dimensions of the gate structure along the X direction, and its width is less than half the width of the gate trench, so as to avoid affecting the connection effect between the polysilicon in the gate trench and the polysilicon on the substrate surface.

[0082] For example, the materials of the first isolation layer 221 and the second isolation layer 222 include materials with high dielectric constants, such as one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or titanium oxide (TiO2).

[0083] A second polysilicon layer is formed on the top surface of the exposed first polysilicon layer and the top surface of the first isolation layer 221. A second polysilicon material is deposited on the surface of substrate 100 using a deposition process, filling the remaining space of the gate trench and extending above the top surface of substrate 100. Next, please refer to... Figure 9The second polysilicon material is etched to form conductive portions. These conductive portions are spaced apart along the second direction Y and cover the second base region 142. The second polysilicon layer located directly above the second base region 142 constitutes the conductive portions, and the conductive portions surround the outer surface of the first isolation layer 221. The gate structure includes conductive portions and a gate oxide layer 180, a first polysilicon layer, and a second polysilicon layer filled within the gate trench.

[0084] At this point, the gate structure is complete. In the formed gate structure, the sidewalls of the gate structure and the surface of the second base region 142 can form parallel conductive channels, providing a structural basis for channel densification during subsequent device operation. Simultaneously, the internal first isolation layer 221 separates the first and second polysilicon layers from the first and second source regions in the Y and Z directions, effectively reducing the gate-source capacitance Cgs. In the Z direction, the first isolation layer 221 increases the equivalent dielectric thickness and dielectric constant between the conductive portion and the drain, further reducing the gate-drain capacitance Cgd. The synergistic effect of these structural features allows the device to achieve higher channel density while optimizing its switching characteristics and effectively suppressing dynamic losses.

[0085] Subsequently, step S108 is performed to form an interlayer dielectric layer 200 covering the gate structure and a metal plug located between adjacent interlayer dielectric layers 200; the metal plug is in contact with the top surface of the first base region 141, the top surface of the substrate 100 between adjacent first base regions 141, and a portion of the top surface of the doped pillar 160 along the X direction.

[0086] Please see Figure 10 An interlayer dielectric material is formed by a deposition process, and then planarized by chemical mechanical polishing to obtain an interlayer dielectric layer 200 with a flat top surface.

[0087] For example, the material of the interlayer dielectric layer 200 includes, but is not limited to, silicon oxide or a material with a high dielectric constant.

[0088] Then, please see Figure 11 The interlayer dielectric layer 200 and the gate oxide layer 180 are etched to form source contact holes. The location and size of the contact holes are defined by the photolithography pattern. The contact holes penetrate the interlayer dielectric layer 200 and the gate oxide layer 180, exposing the top surface of the first base region 141, the top surface of the substrate 100 between adjacent first base regions 141 (i.e., the substrate regions on both sides of the second base region 142), and part of the top surface of the doped pillar 160.

[0089] Next, please refer to Figure 12 A metal plug 210 is formed in the contact hole. The metal plug 210 is in contact with the top surface of the first base region 141, the top surface of the substrate 100 between adjacent first base regions 141, and a portion of the top surface of the doped pillar 160 along the second direction Y.

[0090] For example, this step also includes front-side metallization processes such as NiSilicide generation, titanium (Ti) / titanium nitride (TiN) deposition, tungsten (W) deposition, and aluminum (Al) / copper (Cu) deposition to form a front-side metal layer. The metal plug 210 of the front-side metal layer simultaneously contacts the top surface of the first base region 141, the top surface of the substrate 100 between adjacent first base regions 141, and a portion of the top surface of the doped pillar 160, forming a PiN structure with the doped pillar 160 and the substrate 100. At the same time, a Schottky contact is formed between the metal plug 210 and the un-ion-implanted substrate 100.

[0091] In addition, since the height of the gate structure exceeds the substrate surface, the contact area between the second polysilicon layer and the front metal layer in the gate structure is increased, thereby reducing the contact resistance of the gate structure.

[0092] Finally, the back side of the substrate 100 is thinned and metallized to form a back metal layer, thus completing the fabrication of the semiconductor device.

[0093] Figure 13 This diagram illustrates the electron flow in the semiconductor device structure fabricated using the above method. The device structure shows that during MOS operation, three electron flow directions exist: ① ordinary trench sidewall channel electrons, ② electrons that first flow through the source region along path ① and then through the trench sidewall channel, and ③ planar gate channel electrons. These three electron flow directions work synergistically to densify the channel and reduce Rsp.

[0094] In some embodiments, this application also provides an electronic device, including a semiconductor device prepared by the above-described preparation method.

[0095] The technical features of the embodiments described can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A plurality of doped pillars are formed in the substrate at intervals along a first direction and extending along a second direction, and a first base region and a second base region are alternately arranged along the second direction in contact with the sidewalls of the doped pillars; wherein the width of the first base region is greater than that of the second base region and equal to the spacing between adjacent doped pillars; A gate trench is formed that penetrates the first base region and the second base region along a third direction; the gate trench extends along a first direction to partially embed the doped pillar; A gate structure is formed within the gate trench, and a first isolation layer is embedded in the gate structure; the top surface of the gate structure is higher than the top surface of the substrate, and includes conductive portions spaced along the second direction that cover the second base region; the first isolation layer extends along the second direction, and its maximum width within the gate trench is less than half the width of the gate trench; the width is used to characterize the dimension along the first direction; An interlayer dielectric layer covering the gate structure is formed, and a metal plug is located adjacent to the interlayer dielectric layer; the metal plug is in contact with the top surface of the first base region, the top surface of the substrate between the adjacent first base regions, and a portion of the top surface of the doped pillar along the second direction.

2. The preparation method according to claim 1, characterized in that, The first base region includes a first source region extending inward from the top surface of the first base region; The second base region includes a second source region disposed near the conductive portion; the width of the second source region is smaller than that of the second base region.

3. The preparation method according to claim 2, characterized in that, The formation of the second source region and the first source region includes: An initial base region and an initial source region are sequentially formed within the substrate; the orthographic projections of the initial base region and the initial source region onto the top surface of the substrate are both in a grid pattern; the top surface of the initial source region is located inside the top surface of the initial base region. A multi-step ion implantation process is performed on the initial base region, the initial source region, and the substrate between adjacent initial base regions to form the plurality of doped pillars; the remaining initial source regions constitute the first source region and the second source region.

4. The preparation method according to claim 3, characterized in that, Perform a multi-step ion implantation process, including: A high-energy ion implantation process is used to form an initial doped pillar that penetrates the source region along the third direction and extends into the base region or the substrate; The substrate is tilted at 4° and subjected to a room-temperature ion implantation process to deepen the initial doped pillars by utilizing the channel effect, thereby forming the doped pillars.

5. The preparation method according to claim 2, characterized in that, Forming the first isolation layer further includes: A gate oxide layer and a first polysilicon layer with a top surface lower than the first source region and the second source region are sequentially formed in the gate trench; A first isolation layer is formed on the top surface of the first polysilicon layer on the side away from the doped pillar, and a second isolation layer is formed on the top surface of the substrate and the top surface of the doped pillar between the second base region and the first base region; the first isolation layer covers the top surface of the second source region.

6. The preparation method according to claim 5, characterized in that, Forming the conductive portion includes: A second polysilicon layer is formed on the top surface of the exposed first polysilicon layer and the top surface of the first isolation layer; wherein the second polysilicon layer located directly above the second base region is used to form a conductive portion, and the conductive portion surrounds the outer surface of the first isolation layer.

7. The preparation method according to claim 6, characterized in that, The gate oxide layer covers the inner surface of the gate trench and extends along the first direction to below the interlayer dielectric layer; The second isolation layer is located between the interlayer dielectric layer and the gate oxide layer.

8. The preparation method according to any one of claims 5-7, characterized in that, The ratio of the length of the first base region to the length of the second base region is 1:

1.

9. The preparation method according to claim 8, characterized in that, Includes at least one of the following technical features; The substrate includes a base, a buffer layer, and an epitaxial layer arranged sequentially in a direction opposite to the third direction; The conductivity type of the substrate is opposite to that of the doped pillar, the first base region, and the second base region, but the same as that of the first source region and the second source region. The first isolation layer and the second isolation layer comprise materials with high dielectric constants.

10. An electronic device, characterized in that, This includes semiconductor devices prepared using the preparation method described in any one of claims 1-9.

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