Group iii nitride transistor device

Abstract

III-Nitride transistor devices are disclosed. In embodiments, a III-Nitride transistor device is provided that includes a III-Nitride body including an active region contributing to a load switch, a III-Nitride channel layer, and a III-Nitride barrier layer disposed on the III-Nitride channel layer and forming a heterojunction therebetween; a source finger, a gate finger, and a drain finger disposed on the III-Nitride barrier layer; a source pad electrically coupled to the source finger, a gate pad coupled to the gate finger, and a drain pad coupled to the drain finger; and a gate resistor electrically coupled between the gate pad and the gate finger of the transistor device. The gate resistor is at least partially located on the active region of the transistor device.

Description

Background Technology

[0001] To date, transistors used in power electronics applications have typically been fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs). Recently, silicon carbide (SiC) power devices have been considered. Group III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying high currents, supporting high voltages, and providing very low on-resistance and fast switching times.

[0002] Publicly available U.S. patent application US 2016 / 0211337 A1 describes a group III nitride power device including a HEMT (High Electron Mobility Transistor) with a solderable pre-metal structure having multiple interconnecting metal layers and using solder strips for external circuit connections. The solderable pre-metal structure may include a trimetallic material such as TiNiAg and may be configured to provide the source and drain contacts of the HEMT as alternating elongated fingers or strips.

[0003] The goal is to provide III-nitride-based transistor devices that are compact in size and can be more easily integrated into applications. Summary of the Invention

[0004] In one embodiment, a group III nitride transistor device is provided, comprising a group III nitride body, the group III nitride body including: an active region contributing to load switching; a group III nitride channel layer and a group III nitride barrier layer disposed on the group III nitride channel layer and forming a heterojunction therebetween; source fingers, gate fingers, and drain fingers disposed on the group III nitride barrier layer; source pads electrically coupled to the source fingers, gate pads coupled to the gate fingers, and drain pads coupled to the drain fingers; and a gate resistor electrically coupled between the gate pads and the gate fingers of the transistor device. The gate resistor is at least partially located on the active region of the transistor device.

[0005] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0006] The elements in the accompanying drawings are not necessarily to scale. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and are described in detail in the following description.

[0007] Figure 1 includes Figure 1A and Figure 1B ,in Figure 1A The illustration shows a schematic perspective view of a portion of a group III nitride transistor device, and Figure 1B The illustration shows a schematic cross-sectional view of a portion of a group III nitride transistor device.

[0008] Figure 2 includes Figure 2A and Figure 2B ,in Figure 2A The illustration shows a schematic top view of the front-side metallization structure of a group III nitride transistor device according to an embodiment, and Figure 2B The illustration shows a schematic cross-sectional view of the front metallization structure of a group III nitride transistor device according to an embodiment.

[0009] include Figures 3A to 3C Figure 3 illustrates a method for manufacturing group III nitride transistor devices.

[0010] include Figure 4A and Figure 4B Figure 4 illustrates a group III nitride transistor device according to an embodiment.

[0011] include Figures 5A to 5D Figure 5 illustrates a method for fabricating a gate resistor in a groove formed in the second main surface of a support substrate of a group III nitride transistor device.

[0012] Figure 6 The illustration shows a group III nitride transistor device according to an embodiment.

[0013] Figure 7 A top view of a group III nitride device according to an embodiment is illustrated. Detailed Implementation

[0014] In the following detailed description, reference is made to the accompanying drawings, which form part of this document, and specific embodiments in which the invention may be practiced are illustrated by way of illustration. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “front end,” “end,” etc., are used to indicate orientation with reference to the figures(s) being described. Because components of the embodiments may be positioned in many different orientations, these directional terms are for illustrative purposes and are not intended to be limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description should not be viewed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0015] Several exemplary embodiments will now be explained. In this context, the same structural features are identified by the same or similar reference numerals in the figures. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or range generally parallel to the lateral extent of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. Conversely, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0016] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on" or "directly extending onto" another element, no intermediate elements are present.

[0017] As used in this specification, when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, no intermediate components are present.

[0018] Depletion-type devices, such as high-voltage depletion-type transistors, have a negative threshold voltage, meaning they can conduct current at zero gate voltage. These devices are normally on. Enhancement-type devices, such as low-voltage enhancement-type transistors, have a positive threshold voltage, meaning they cannot conduct current at zero gate voltage and are normally off.

[0019] As used herein, the term "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including, but not limited to, any of their alloys, such as, for example, aluminum gallium nitride (Al). x Ga （1-x） N), Indium gallium nitride (In) y Ga （1-y） N), aluminum indium gallium nitride (Al) x In y Ga （1-x-y） N), gallium arsenide phosphide (GaAs) a P b N （1-a-b） ) and aluminum indium gallium arsenide phosphide (Al x In y Ga （1-x-y） Asa P b N （1-a-b） AlGaN and AlGaN refer to aluminum gallium nitride (AlGaN) derived from the formula AlGaN. x Ga （1-x） N describes the alloy, where 0 <x<1。

[0020] For group III nitride high electron mobility transistors (HEMTs), appropriate chip-level thermal management strategies mitigate any self-heating effects of the two-dimensional electron gas (2DEG), increasing reliability, improving output power, and widening the safe operating area of ​​the device.

[0021] When the goal is higher operating voltage, lateral GaN devices can have a larger chip size. When such devices are integrated into a module, a considerable amount of space within the module is occupied by wiring connections leading to the source / drain-gate contacts. For a predefined package, this can limit the package's power density.

[0022] As an alternative to wiring bonding methods for group III nitride-based devices, chip-side mounting can be used, for example, using bump technology. Flip-chip bumps serve several purposes, including electrical connectivity, thermal connectivity, and mechanical robustness. To enhance heat transfer, bumps are mounted on the outer surface of the transistor. If the gate, source, and drain contacts are placed on only one side of the device, this can reduce the heat dissipation rate. In the case of the flip-chip method, solder bumps or Cu pillars on the gate, drain, and source pads are the only conductive means of transferring heat to the substrate. Therefore, channel heat moves from the gate through two distinct paths: the group III nitride and the underlying Si substrate. Since both have similar thermal conductivity, most channel heat passes through the bumps. The three parameters of a thermal bump are its cross-sectional area, its height, and its material. For example, for GaN power devices designed to block higher voltages (e.g., greater than 650V), the effective cross-sectional area of ​​the bump may be a limiting parameter due to current congestion.

[0023] One approach to mitigate the problems described in this disclosure is to place the source and drain contacts on opposite sides of the chip. Alternatively or additionally, this disclosure proposes a gate structure that is deployed in a layer above or below the active portion of the chip (i.e., the 2-DEG layer), but not within the active portion of the chip. This alleviates the typically inherent design constraints of HEMTs and gate resistors competing for space within the 2-DEG layer. A larger portion of the active region having its 2-DEG can be occupied by the HEMT structure. This can be used to provide reduced chip R... DS,on While maintaining the same die size, or being used to achieve a given R DS,on The chip shrinks.

[0024] Further embodiments of the present invention provide a semiconductor structure or device having one or more gate contact structures (e.g., one or more gate contact vias) deployed on the active portion of the gate electrode of the semiconductor structure or device.

[0025] The present invention also provides a gate contact structure, which includes a gate pad and an additional gate resistor, the additional gate resistor having an additional resistance R. G,int The gate is spatially removed from the active portion of the device. For example, the gate structure can be deployed above the active cell region and located on either of the two opposing main surfaces of the die. Methods for forming such gate contacts are also provided. A group III nitride-based HEMT die with two gate pads can be utilized to achieve a higher active region to chip size ratio with the proposed design. A gate resistor is provided for each gate pad. Such a dual-gate pad arrangement can be used to provide bidirectional switching.

[0026] Lateral GaN HEMTs with source / drain / gate contacts on opposite sides can be fabricated using through-silicon vias (TSVs) or through-substrate vias (TSVs). Such heterogeneous integration and advanced packaging provide increased functionality. This allows for vertically direct routing of drain / source / gate signals, unlike routing to the periphery and wiring to an interposer or printed circuit board. This vertical routing enables shorter electrical path lengths, which reduces electrical parasitics such as resistive and capacitive time delays. In addition to electrical improvements, the use of TSVs allows for an increased number of inputs and outputs, as they can be distributed across the entire chip area instead of utilizing only the chip periphery. In this embodiment, TSV processing is used to route the gate contact to the back side of the wafer. This allows the front side of the lateral GaN HEMT chip to be directly contacted to the substrate using die-attach technology in a flip-chip approach. A similar TSV concept can be used to vertically route the source pads on the same chip side as the gate pads and the drain pads on the opposite chip side to provide a vertical GaN HEMT architecture. A similar manufacturing concept can be used to accommodate the additional gate resistor R located away from the 2-DEG. G,int Furthermore, a gate pad is formed on the side of the 2-DEG opposite to the gate fingers.

[0027] The method for manufacturing the proposed chip design includes forming contact patterns aligned with existing gate fingers (nodes). Selective contact etching can be used to etch and form via structures in the support substrate, group III nitride materials, and / or electrically insulating layers (e.g., interlayer dielectrics). Materials such as SiO2, Si3N4, and AlO2 can be used, for example. xAn insulating layer, or any other dielectric material, is deposited on the etched sidewalls of the support substrate and the group III nitride, and then one or more materials are conformally deposited into the via to form a conductive via, i.e., a vertically penetrating contact.

[0028] In this embodiment, the gate resistor is routed to the back side of the device along with the source potential. The gate resistor is formed on or in the back surface of a supporting substrate (e.g., silicon). A trench for the gate resistor is formed (e.g., etched) into the back side of the silicon substrate before TSV insulation for gate and source routing is implemented. (The last sentence appears to be incomplete and possibly refers to a specific R...) G,int The required width is greater than that of these gate resistor trenches. During the TSV insulation process, for example, the same process used for vias through the substrate utilizing electrically insulating pads is employed to utilize these gate resistor trenches, thereby reducing the trench width to produce the desired gate resistance R. G,int Furthermore, the gate potential is electrically isolated from the source potential of the substrate. Conductive material (e.g., one or more metal layers) is also deposited into the gate resistor trench and onto the back side of the supporting substrate to form the gate and source pads. It has a resistance R... G,int The additional gate resistor is integrated as an isolated entity within the support substrate of the group III nitride device.

[0029] Therefore, a group III nitride transistor device is provided, wherein the gate resistance R is adjustable for devices used in modules or packages where parallelization is important. G,int This allows for appropriate adjustment of the gate resistance value to suppress any oscillations or inter-chip oscillations that may occur at high switching speeds. The size of the gate pads can also be adjusted. This enables a more flexible application of diverse pools of so-called back-end interconnect technologies (such as wiring joints, jigs, etc.), thus increasing design freedom in back-end routing.

[0030] Figure 1 includes Figure 1A and Figure 1B ,in Figure 1A The illustration shows a schematic perspective view of a portion of a group III nitride transistor device 10 according to an embodiment, and Figure 1B The figure shows a schematic cross-sectional view of a portion of a group III nitride transistor device 10 according to an embodiment.

[0031] The group III nitride transistor device 10 includes a group III nitride body 11. The group III nitride body 11 includes a group III nitride channel layer 12 and a group III nitride barrier layer 13. The group III nitride barrier layer 13 is disposed on the group III nitride channel layer 12 and forms a heterojunction 14 therebetween. The heterojunction 14 may be capable of supporting a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG). The group III nitride channel layer 12 has a different composition and a different bandgap from the group III nitride barrier layer 13. In one embodiment, the group III nitride channel layer 12 is formed of gallium nitride (GaN), and the group III nitride barrier layer 13 is formed of aluminum gallium nitride Al x Ga （1-x） N, where 0<x<1. The group III nitride body 11 includes an active region 15 that contributes to a load switch. The group III nitride transistor device 10 may be a HEMT (high electron mobility transistor).

[0032] The group III nitride transistor device 10 further includes a source finger 16, a gate finger 17 and a drain finger 18 disposed on the group III nitride barrier layer 13. The source finger 16, the gate finger 17 and the drain finger 18 have elongated strip-shaped structures and extend substantially parallel to each other. The gate finger 17 is laterally disposed between the source finger 16 and the drain finger 18. This arrangement of the source finger 16, the gate finger 17 and the drain finger 18 may be referred to as a transistor cell. The group III nitride transistor device 10 further includes a source pad 19 electrically coupled to the source finger 16, a gate pad 20 electrically coupled to the gate finger 17, and a drain pad 21 electrically coupled to the drain finger 18.

[0033] Generally, the group III nitride transistor device 10 includes a plurality of transistor cells, each of which includes the source finger 16, the gate finger 17 and the drain finger 18. Adjacent transistor cells among the transistor cells may include a common drain finger 18 and / or a common source finger 18, such that the fingers are arranged on the group III nitride barrier layer 13 in a repeating pattern of source-gate-drain-gate-source-gate-drain. The active region 15 corresponds to the region of the group III nitride body 11 directly below the transistor cells.

[0034] Each of the source fingers 16 can be connected to a common source pad 19, each of the drain fingers 18 can be connected to a common drain pad 21, and each of the gate fingers 17 can be connected to a common gate pad 20. However, for a group III nitride transistor device 10, it is possible to include more than one source pad 19 and / or more than one gate pad 20 and / or more than one drain pad 21. In these embodiments, a sub-portion of the total number of source fingers can be connected to each of two or more source pads, a sub-portion of the total number of gate fingers can be connected to each of two or more gate pads, and a sub-portion of the total number of drain fingers can be connected to each of two or more drain pads.

[0035] Gate fingers 17 may include: p-doped group III nitride fingers 45 located on and in direct contact with the group III nitride barrier layer 13; and gate metal fingers 46 located on and in direct contact with the p-doped group III nitride fingers 45. For example, p-doped group III nitride fingers 17 may include Mg-doped GaN. This arrangement of gate fingers 17 produces a normally closed enhancement-mode device. In addition to or instead of p-doped group III nitride fingers 45, gate fingers 17 may have a recessed structure to form a normally closed enhancement-mode device.

[0036] Typically, the group III nitride body is a cuboid 11, thus the first main surface 24 is square or rectangular. In this embodiment, the first main surface 24 is provided by a group III nitride barrier layer 13. Gate pads 20 may be located at the corners of the first main surface 24 of the group III nitride body 11. In other embodiments, gate pads 20 may be located on the first main surface 24 of the group III nitride body 11, at the midpoint of the length of one side of the group III nitride body 11. In embodiments including two gate pads, the two gate pads may be located at two adjacent corners of the first main surface 24.

[0037] The group III nitride transistor device 10 also includes an additional gate resistor 22 electrically coupled between the gate pad 20 and the gate fingers(s) 17 of the transistor device 10. It can be... Figure 1A The gate resistor 22 is seen in the perspective view. The gate resistor 22 is located at least partially above and above the active region 15 of the semiconductor device 10.

[0038] In embodiments where multiple gate fingers 17 are located on a group III nitride barrier layer 13, these gate fingers 17 may be connected at one end via a gate channel not visible in FIG. 1. A gate resistor 22 is connected between the gate channel and the gate pad 20, such that the gate resistor 22 provides additional resistance in the electrical path between the common gate pad 20 and the gate channel.

[0039] Since the gate resistor 22 is located above the active region 15 of the transistor device 10, no additional region on the group III nitride body 11 is required to separately support or form the gate resistor 22. Therefore, it is not necessary to increase the lateral size of the group III nitride body 11 to accommodate the gate resistor 22. In some embodiments, the gate resistor 22 may be fabricated from one or more conductive layers of a metallization structure formed on the front and / or back sides of the group III nitride transistor device 11. Therefore, the gate resistor 22 can be considered integrated into the metallization structure.

[0040] An electrically insulating layer 23 may be formed on a first main surface 24 of a Group III nitride body covering the source finger 16, gate finger 17, and drain finger 18. Gate pads 20 and gate resistors 22 are positioned on the insulating layer 23. In these embodiments, a gate via 25 extends from the gate finger 17, or typically a gate channel, through the insulating layer 23 to the gate resistor 22 located on the upper surface of the insulating layer 23. The gate pads 20 and gate resistors 22 are located in a different lateral plane than the gate channel and gate finger 17. Optionally, source pads 19 and drain pads 21 are also located on the insulating layer 23.

[0041] Reference Figure 1AGate resistor 22 extends between gate via 25 and gate pad 20. Gate resistor 22 has the form of a planar metal trace with a zigzag or serpentine shape. This allows gate resistor 22 to have a large resistance and be housed in a small area. This also allows the resistance of gate resistor 22 to be adjusted or regulated, for example, by changing the thickness and / or width of the trace or by adjusting the length of the metal trace. The serpentine shape includes a plurality of elongated strip segments 28 and connecting segments 29, whereby the connecting segments extend at alternating ends between the elongated segments to form a continuous zigzag shape. The serpentine shape includes at least one bend, each bend including two substantially parallel elongated metal traces 28, 28' having a first end and an opposing second end, and a bend-connecting metal trace 29 connecting the first ends of the two substantially metallic traces to form a U-shape. The bend-connecting trace 29 may extend substantially perpendicular to the elongated metal traces 28. The second curved connecting trace 29' extends from the second end of one of the two elongated metal traces 28' to the second end of the third elongated metal trace 28'', the third lead connecting metal trace 29'' extends from the first end of the third elongated metal trace 28'' to the first end of the fourth elongated metal trace 28''', and so on.

[0042] The transistor device 10 illustrated in Figure 1 enables independent adjustment of the gate resistor 22 and its resistance R. G,int This is useful for group III nitride devices housed in modules or packages where parallelization is important. The value of gate resistor 22, R... G,int It can be appropriately customized, for example by changing the dimensions (e.g., length) of the planar metal trace providing the gate resistor 22, to suppress oscillations or inter-chip oscillations due to high switching speeds. Increased design freedom for constructing the gate pad dimensions is also provided, which offers greater flexibility for the interconnect parameters to be optimized, such as wiring bonding settings / design rules.

[0043] The electrically insulating layer 23 on which the gate resistor 22 and the gate pad 20 are formed allows for the construction of a larger template for the gate resistor 22. This provides greater design freedom, allowing the gate resistor to be adapted to the needs of a specific application.

[0044] In one embodiment, the planar metal trace of the gate resistor 22 includes an outermost bend, which comprises an elongated trace 30 extending from the gate via 25 and parallel to the first elongated trace 28, and a lateral segment 31. The lateral segment 31 extends from the elongated trace 30 adjacent to the first distal end of the metal trace 28 and parallel to the lateral bend connecting segment 29. The lateral segment 31 then extends into the serpentine outermost elongated metal trace 28 located on the side opposite to the first elongated trace 28. The first metal trace 28, located adjacent to the first bend of the elongated metal trace 30 extending from the gate via 25, extends into the gate pad 20. Thus, the gate pad 20 and the gate via 25 are connected to opposite ends of the planar trace 22 and positioned adjacent to each other on one side of the gate resistor 22 and the insulating layer 23. The arrangement of the outermost bends of the elongated traces 30 and the transverse segments 31 on both sides of the bends surrounding the serpentine structure enables the cancellation of the magnetic field generated by the current flowing through the metal traces.

[0045] The insulating layer 23 may include two or more sublayers, such as a first sublayer in direct contact with the upper surface 24 of the group III nitride barrier layer 13 and a second sublayer located on the first sublayer. The first sublayer may include an oxide, such as silicon oxide, and the first sublayer may include a nitride, such as silicon nitride.

[0046] In some embodiments, the source pad 19 is electrically connected to the source finger 16 via a conductive redistribution structure including at least one conductive via 26 extending through the second electrical insulating layer 48, and the drain pad 21 is electrically coupled to the drain finger 18 via at least one conductive via 27 extending through the second electrical insulating layer 48. The second electrical insulating layer 48 may extend over the entire first main surface 24, and a first electrical insulating layer 23 is located on the portion of the second electrical insulating layer adjacent to the source pad 19 and the drain pad 21.

[0047] Reference Figure 1BIn a cross-sectional view, in some embodiments, a group III nitride body 11 is formed on a support substrate 40, the support substrate 40 having a first main surface 41 capable of supporting the growth of at least one epitaxial group III nitride layer. The support substrate 40 may be formed of a heterogeneous substrate, which is formed of a material other than group III nitrides. The support substrate 40 may be formed of a single-crystal silicon wafer or a single-crystal silicon layer and may have… <111> or <110> Orientation. Alternatively, the support substrate 40 may be formed of silicon carbide or sapphire. A buffer layer 42 may be formed between the support substrate 40 and the group III nitride body 11, and thus extend between the growth surface 41 of the support substrate 40 and the group III nitride channel layer 12. The support substrate 40 has a second main surface 43 opposite to the growth surface 41 and provides a rear-side second main surface for the group III nitride device 10.

[0048] In some embodiments not shown, the buffer structure 42 may further include a back-side barrier layer. A group III nitride channel layer 12 is formed on the back-side barrier layer and forms a heterojunction with it, and a group III nitride barrier layer 13 is formed on the group III nitride channel layer 12. The back-side barrier layer has a different band gap than the channel layer 12, and if the group III channel layer 12 includes GaN, it may include, for example, AlGaN. The composition of the AlGaN in the back-side barrier layer may differ from the composition of the AlGaN used in the barrier layer 13.

[0049] A typical transition or buffer structure for a buffer layer 42 suitable for a silicon substrate 40 includes an AlN initiation layer on the silicon substrate 40, which may have a thickness of several hundred nanometers, followed by Al x Ga （1-x） The N-layer sequence, with each layer again several hundred nanometers thick, reduces the Al content from approximately 50-75% to 10-25% before growing the group III nitride channel layer 12 (e.g., a GaN layer) or the AlGaN backside barrier (if present). Alternatively, a superlattice buffer can be used. Again, an AlN initiation layer is used on a silicon substrate. Depending on the superlattice chosen, AlN and Al... x Ga （1-x） N-paired sequences, where AlN layers and Al x Ga （1-x） The thickness of N ranges from 2 to 25 nm. Depending on the desired breakdown voltage, the superlattice can include between 20 and 100 pairs. Alternatively, the Al described above can be used in combination with the superlattice mentioned above. x Ga （1-x） N-layer sequence.

[0050] In the embodiment illustrated in FIG1, all contact pads 19, 20, 21 and gate resistor 22, which serve as external contact areas for electrically connecting the group III nitride transistor device 10 to other devices or redistribution boards, are formed on the same side, i.e., on the front side 44 of the group III nitride transistor device 10. The front side 44 is positioned above the group III nitride body 11. The rear side of the group III nitride transistor device 10 is provided by the rear side 43 of the support substrate 40 and is opposite to the front side 44.

[0051] In some embodiments, a front-side metallization 47 on the front side 44 of the group III nitride transistor device 10 provides a source pad 19, a gate pad 20, a drain pad 21, a gate resistor 22, and a conductivity redistribution structure from the source finger 16 to the source pad 19, from the gate finger 17 through the gate via 25 and the gate resistor 22 to the gate pad 20, and from the drain finger 18 to the drain pad 21. The gate resistor 22 can be considered integrated into the front-side metallization 47. The gate resistor 22 is also at least partially located above the active region 15 of the group III nitride device 10 that contributes to the load switching. The active region of the group III nitride transistor device 10 is located below the transistor cell and below the source finger 16, the gate finger 17, and the drain finger 18. Therefore, at least a portion of the gate resistor is located above and overlaps with at least a portion of one or more transistor cells, and is located above and overlaps with at least a portion of a source finger 16, a gate finger 17, and a drain finger 18 forming the transistor cell. The gate resistor 22 is electrically insulated from the underlying source finger 16 and drain finger 18 by a first electrical insulating layer 23 and a second electrical insulating layer 48 (if present).

[0052] Figure 1 illustrates an example of a front-side metallization structure 47, which includes an additional gate resistor 22 between the gate fingers 17 and the gate pad 20, and also includes separate redistribution structures from the source fingers 16 and the drain fingers 18 to their respective pads 19, 21. However, the front-side metallization structure 47 and the redistribution structures provided by it are not limited to this arrangement and may have other structures.

[0053] Figure 2 includes Figure 2A and Figure 2B ,in Figure 2A A schematic top view of the front metallization structure 47 of a group III nitride transistor device 10 according to an embodiment is illustrated, and Figure 2BThe illustration shows a cross-sectional view of the front metallization structure 47 of a group III nitride transistor device 10 according to an embodiment. The front metallization structure 47 has three conductive layers. The bottommost first conductive layer 50 is in direct contact with the first main surface 24 of the group III nitride body 11 and with the group III nitride barrier layer 13, and is configured to form source fingers 16, gate fingers 17, and drain fingers 18. An electrically insulating layer 54 is located on the first main surface 24 to cover the source fingers 16, gate fingers 17, and drain fingers 18. The second conductive layer 51 includes an elongated source segment 52 and an elongated drain segment 53, one of the elongated source segments 52 being aligned with and located thereon of each of the source fingers 16, and one of the elongated drain segments 53 being aligned with and located thereon of each of the drain fingers 18. The electrical insulating layer 54 has an opening 55, into which a source segment 52 and a drain segment 53 extend to electrically connect the individual source segment 52 to its corresponding lower source finger 16 and to electrically connect the individual drain segment 53 to its corresponding lower drain finger 18.

[0054] An additional electrical insulating layer 59 is located on the second metallization layer 51, and a third conductive layer 56 is located on the additional insulating layer 59. The third conductive layer 56 includes at least one source bus 57 and at least one drain bus 58. The source bus 57 extends over and substantially perpendicular to the source and drain sections 52 and 53. The source bus 57 is electrically connected to the source section 52 via a conductive via 60 extending through the electrical insulating layer 59. The source bus 57 is electrically insulated from the underlying drain section 53 via the electrical insulating layer 59. The conductive via 60 is located in a row below the source bus 57. The drain bus 58 extends over and substantially perpendicular to the source and drain sections 52 and 53 and parallel to the source bus 57. The drain bus is electrically connected to the underlying drain section 53 via a conductive via 61 extending through the electrical insulating layer 59. The drain bus 58 is electrically insulated from the source section 52 below it by an electrical insulating layer 59. A via 61 is located in a row below the drain bus 58.

[0055] include Figures 3A to 3C Figure 3 illustrates a method for manufacturing a group III nitride transistor device, and can be used to manufacture the group III nitride transistor device 10 illustrated in Figure 1. Figure 3A A top view showing a portion of the first main surface 24 of the group III nitride body 11. At least one transistor cell, including source fingers 16, gate fingers 17, and drain fingers 18, is located on the first main surface 24.

[0056] In an arrangement of two or more transistor cells in which gate fingers 17 are located on opposite sides of a common source finger 16, these gate fingers 17 can be electrically connected to each other via a gate connection portion 62, which can be... Figure 3A As seen in the top view, the gate connection portion 62 extends substantially perpendicular to the length of the gate finger 17 and is spaced apart from the distal end of the source finger 18. The gate finger 17 extends beyond the gate connection portion 62 and beyond the distal ends of the source finger 16 and the drain finger 18 to reach the gate channel 63, which extends substantially perpendicular to the length of the gate finger 17 and electrically connects the gate fingers 17 to each other.

[0057] Reference Figure 3B A second electrically insulating layer 48 is located on the first main surface 24 of the group III nitride layer 13. A first electrically insulating layer 23 is formed on the second electrically insulating layer 48 and has a lateral area smaller than that of the lower second electrically insulating layer 48. The lateral area of ​​the first electrically insulating layer 23 corresponds to the total area required by the gate resistor 22. The first electrically insulating layer 23 covers at least the end portions of the gate fingers 17, the gate channel 63, and the end portions of the source fingers 16 and the drain fingers 18. In order to form an electrical connection between the gate channel 63 located in the lowermost conductive layer 50 of the front metallization 47 and the gate resistor 22 to be formed on the opposite upper surface of the insulating layer 23, a via 64 is formed to expose a portion of the gate channel 63 through the first electrically insulating layer 23 and the second electrically insulating layer 48. In some embodiments, an additional electrically insulating layer may be formed on the sidewall of the via 64. For example, a conductive material such as copper is deposited at least on the sidewall of the via 64, and may even fill the via 64 to form a conductive via 25 extending through the thickness of the first electrical insulating layer 23 and the second electrical insulating layer 48.

[0058] Reference Figure 3C The gate resistor 22 can be formed by depositing a metal layer onto the electrically insulating layer 23 and configuring the metal layer to form a tortuous metal trace including a plurality of series-connected end openings. One end of the metal trace is electrically connected to the conductive via 25 and the other end of the metal trace is electrically connected to the gate pad 20. Alternatively, the metal trace of the gate resistor 22 can be selectively deposited onto the electrically insulating layer.

[0059] Gate pad 20, source pad 19, and drain pad 21 may also be fabricated from the conductive layer used to form gate resistor 22. Alternatively, source pad 19, gate pad 20, and drain pad 21 may be fabricated in a conductive layer different from the planar trace of gate resistor 22. Alternatively, the conductive layer used to form gate resistor 22 may form a lower sublayer of gate pad 20, source pad 19, and drain pad 21, and the thickness of these pads 19, 20, and 21 may be increased by depositing a second sublayer onto the first sublayer.

[0060] Source pad 19 can provide a source bus 57 electrically connected in parallel to source fingers 16. Drain pad 21 can provide a drain bus 58 electrically connected in parallel to drain fingers 18. Gate resistor 22 is formed in the front metallization 47 of group III nitride transistor 10 and is at least partially located above the active region 15 of group III nitride transistor device 10. Gate resistor 22 and gate pad 20 are formed on electrical insulating layer 23, while source pad 19 and drain pad 21 are located on lower second electrical insulating layer 48 and are laterally adjacent and spaced apart from electrical insulating layer 23. In the embodiment illustrated in Figures 1 and 3, gate resistor 22 and gate pad 20 are located in a plane different from the plane of source pad 19 and drain pad 21 because electrical insulating layer 23 is only located on a portion of the first main surface 24.

[0061] In some embodiments of the group III nitride transistor device 10, the source pad 19, gate pad 20, drain pad 21, and gate resistor 22 are located on the same side of the device 10. In embodiments of the group III nitride transistor illustrated and described with reference to Figures 1 to 3, the source pad 19, gate pad 20, drain pad 21, and gate resistor 22 are located on the front side 44 and integrated into the front metallization 47. In other embodiments, the source pad 19 and drain pad 21 are located on opposite sides of the group III nitride device 10. In one embodiment, the drain pad 21 is located on the front side 44 of the device 10, and the source pad 19, gate pad 20, and gate resistor 22 are located on the rear side 43 of the device 10. In an alternative embodiment, the drain pad 21 is located on the rear side 43 of the device 10, and the source pad 19, gate pad 20, and gate resistor 22 are located on the front side 44 of the device 10. Gate pad 20 and gate resistor 22 may alternatively be located on the same side as drain pad 21.

[0062] include Figure 4A and Figure 4B Figure 4 illustrates an example of a group III nitride transistor device 10' according to another embodiment. Figure 4A A schematic cross-sectional view of a group III nitride transistor device 10' is illustrated. Figure 4BA schematic perspective view of a group III nitride transistor device 10' is shown. The group III nitride transistor device 10' differs from the group III nitride transistor devices illustrated in Figures 1 through 3 in that the source pad 19, gate pad 20, and gate resistor 22 are located on opposite rear surfaces 43 of the support substrate 40, and the drain pad 21 is located on opposite front surfaces 44. The drain pad 21 can be integrated into the front metallization 47. The source pad 19, gate pad 20, and gate resistor 22 are integrated into the rear metallization. The gate resistor 22 located on the rear surface 43 can have a similar structure to that illustrated in Figure 1.

[0063] Drain pad 21 may extend over substantially all of the first primary surfaces 24 of the group III nitride body 11. Source pad 19 located on the second primary surface 43 of the silicon substrate is electrically connected to source fingers 16 located on the opposite first primary surface 24 of the group III nitride body 11 via at least one conductive via 70 extending through the thickness of the silicon substrate 40, through the group III nitride-based buffer layer 42, and also through the group III nitride body 11 to the first primary surface 24 of the group III nitride body 11. Source pad 19 may be electrically connected to source fingers 16 or connected to the source bus of source fingers 16 via one or more conductive vias 70. The gate pad 20 is positioned adjacent to the source pad 19 on the second main surface 43 of the support substrate 40, and is electrically connected to the gate fingers 17 on the opposite first side 24 of the device 10' via at least one conductive via 71 extending from the second main surface 43 through the silicon substrate 40, through the buffer layer 42, and through the group III nitride body 11 to the first main surface 24. For example, the gate via 71 may be disposed below and in contact with the gate channel 63, and electrically connect the gate channel 63 and thus the gate fingers 17 on the front side 24 of the group III nitride body 11 to the gate resistor 22 and the gate pad 20 disposed on the opposite surface 43 of the group III nitride device 10.

[0064] The Group III nitride transistor device 10' illustrated in Figure 4 has a quasi-vertical arrangement because the source pad 19 and drain pad 21 are arranged on opposite surfaces 24, 43 of the device 10'. In some embodiments, such as those illustrated in Figure 4, the drain pad 21 is mounted to the redistribution plate 72, for example, by solder. This arrangement can be referred to as drain-down. This arrangement can be used to provide an improved thermal path for heat dissipation. In some embodiments, the drain pad 21 may include a plurality of bumps 73, which may be connected, for example, by solder to pads 74 located on the upper surface 75 of the redistribution plate 72. The bumps 73 may include solder. Alternatively, the source pad 19 and gate pad 20 may be mounted on the redistribution plate 72 in a source-down arrangement.

[0065] In the embodiment illustrated in FIG4, the gate resistor 22 is located on a planar electrically insulating layer 23, which is located on the planar rear surface 43 of the support substrate 40. The gate resistor 22 has the form of a planar trace located on the planar electrically insulating layer 23, and may have the form described with reference to FIG1. ​​The gate resistor 22 is electrically connected at one end to the gate channel 63 on the front side 24 through a conductive via 71 extending through the thickness of the support substrate 40 and the group III nitride body 11. The gate resistor 22 is electrically connected at its opposite ends to the gate pad 20. For example, the opposite ends of the gate resistor 22 may be integral with the gate pad 20. However, the gate resistor 22 is not limited to this arrangement and may have other forms.

[0066] include Figures 5A to 5D Figure 5 illustrates a method for fabricating a gate resistor 22 located in a recess 82 formed in a second main surface 43 of a support substrate 40. The recess 82 can also be described as a trench. In this stage, a buffer layer 42 and a Group III nitride body 11 comprising a Group III nitride channel layer 12 and a Group III nitride barrier layer 13 have been epitaxially grown on a growth surface 41 of the support substrate 40, and source fingers 16, drain fingers 18, gate fingers 17, and a gate channel 63 have been formed on a first main surface 24 of the Group III nitride barrier layer 13.

[0067] Reference Figure 5A A first through-hole 81 is formed, extending from the second main surface 43 of the support substrate 40 through the thickness of the support substrate 40 and through the thickness of the group III nitride body 11. The through-hole 81 may be located below and expose a portion of the gate channel 63 positioned on the first main surface 24 of the group III nitride body 11. One or more second through-holes 80 are also formed for forming connections to the source fingers 16. For example, one or more second through-holes 80 may be located above the source bus positioned on the first main surface 24 of the group III nitride body 11. Additionally, a recess 82 is formed in the second main surface 43 of the support substrate 40 and has a lateral shape suitable for forming a gate resistor. For example, the recess 82 may have a serpentine shape, including multiple bends corresponding to the shape of the gate resistor shown in FIG. 1. One end of the recess 82 extends into the through-hole 81 for the gate. The recess 82 and the through-holes 80, 81 may be formed by methods such as etching, laser ablation, etc. The recess 82 may have a larger dimension than required by the gate resistor in order to provide the desired gate resistance, so as to allow the volume occupied by the recess 82 to be provided by electrical insulation between the conductive material of the gate resistor and the support substrate 40.

[0068] Reference Figure 5B An electrically insulating layer 83 is then formed, which pads through the through-holes 80 and 81 and also pads the recess 82. The electrically insulating layer 83 may initially further cover the second main surface 43 and is subsequently removed from the planar second main surface 43, for example, by chemical mechanical polishing, such that it only lies on the sidewalls of the through-holes 80 and 81 and on the sidewalls and bottom of the recess 82. The electrically insulating layer 83 surrounds the gaps in the through-holes 80 and 81 and surrounds the recesses in the recess 82.

[0069] Reference Figure 5C Conductive material, such as copper, is then inserted into vias 80 and 81 and into recess 82. Vias 80 and 81 can be filled to form conductive vias 70 and 71, and recess 82 can also be filled. Subsequently, any conductive material on the second main surface 43 can be removed, for example, by chemical mechanical polishing, so that the gate resistor 22 is formed from the conductive material retained in the recess 82 and has a serpentine shape.

[0070] Reference Figure 5D Source pad 19 is deposited on the second main surface 43 such that it contacts the conductive material in the conductive via 70, and gate pad 20 is deposited on the second main surface 43 such that it contacts the first distal end of the conductive material formed in the recess 82 providing the gate resistor 22. The conductive material in the opposite second distal end of the recess 82 is integrated with the conductive material in the gate via 71, and thus electrically connects the gate resistor 22 to the gate via 71 and the gate channel 63 and gate fingers 17 on the opposite first main surface 24 of the group III nitride body 11.

[0071] Figure 6The illustration shows a Group III nitride transistor device 10” according to an embodiment, wherein a gate pad 20 and a drain pad 21 are formed in a front-side metallization 47, and a source pad 19 is located on an opposing second side 33 of a support substrate 40 in a rear-side metallization. The device 10” can be mounted to a redistribution board 72, for example, by attaching the source pad 19 to a die pad 74 located on a first main surface 75 of the redistribution board 72 using solder. Source fingers 16 located on the first main surface 24 of the Group III nitride body 11 are connected to the source pad 19 located on the lower surface 43 of the support substrate 40 via one or more conductive vias 70 extending from the first main surface 24 formed by the Group III nitride barrier layer 13 to the opposing lower surface 43 of the support substrate 40. For example, one or more vias 70 may extend between a source bus located on the first main surface 24 and the second main surface 43. Drain fingers 18 located on the first main surface 24 can be electrically connected together via a drain bus, which is located on the first main surface and extends above and is electrically insulated from the middle finger of the source fingers 16 and gate fingers 17. The gate fingers 17 located on the first main surface 24 are connected together, for example, via a drain bus. Figure 6 The gate channel and gate resistor 22, which are not visible in the cross-sectional view, are electrically connected to the gate pad 20, which is also located on the first main surface. The gate resistor is also located on the first main surface 24.

[0072] Figure 7A top view of a group III nitride device 10"' according to an embodiment is illustrated. The group III nitride device 10"' includes two gate pads 20, 20' electrically coupled to a gate channel 63 via separate, respective gate resistors 22, 22'. The gate pads 20, 20' are arranged in adjacent corners of a first main surface 24. The two gate resistors 22, 22' are at least partially arranged above the active region 15 of the group III nitride device 10"'. Each of the gate resistors 22, 22' has the form of a planar trace formed on an electrically insulating layer 23. The planar trace may include copper and may have a tortuous shape. The group III nitride device 10"' can be configured as a bidirectional switch or a transistor device. An elongated gate channel 63 connected to a gate finger 17 extends along the middle of the first main surface 24 and an elongated source bus 57, the source bus 57 providing source pads, extending parallel to the gate channel 63 adjacent to the opposite side of the gate channel 63. An elongated drain bus 58 providing drain pad 21 is arranged adjacent to each of the source buses 57 and extends parallel to the source buses 57. A bump is located on each of the gate pads 20, 20'; and multiple bumps are located on each of the source buses 57 and drain buses 58. The bumps may include, for example, solder, such as soft solder or diffused solder, or copper. If desired, the resistance of the two gate resistors 22, 22' can be adjusted individually and independently of each other by, for example, changing the dimensions of the planar traces.

[0073] In summary, a gate contact structure including a gate pad 20 and an additional gate resistor 22 is provided, the additional gate resistor 22 having an additional resistance R. G,int And it is spatially removed from the active portion of the device. For example, gate resistor 22 can be deployed above the active cell region and located on either of the two opposing main surfaces of the die.

[0074] In this way, the inherent design constraints of space competition with the HEMT device and gate resistor 22 are alleviated. A larger portion of the active region 15 with its 2-DEG can be occupied by the HEMT structure. This can be used to provide a reduced chip R DS,on While maintaining the same die size, or for implementing a given R DS,on The chip shrinks.

[0075] While this disclosure is not intended to be limited thereto, the following numbered examples illustrate one or more aspects of this disclosure. Examples 1. A group III nitride transistor device, comprising: The group III nitride host includes an active region contributing to the load switch, a group III nitride channel layer, and a group III nitride barrier layer disposed on the group III nitride channel layer and forming a heterojunction therebetween. Source fingers, gate fingers, and drain fingers are arranged on a group III nitride barrier layer; Source pads electrically coupled to source fingers, gate pads coupled to gate fingers, and drain pads coupled to drain fingers; A gate resistor, which is electrically coupled between the gate pad and the gate fingers of a transistor device. The gate resistor is located at least partially on the active region of the transistor device.

[0076] 2. A group III nitride transistor device according to Example 1, wherein gate fingers are arranged laterally between source fingers and drain fingers, and the gate fingers, source fingers and drain fingers extend substantially parallel to each other.

[0077] 3. The group III nitride transistor device according to Example 1 or Example 2 further includes an additional gate pad and an additional gate resistor electrically coupled between the additional gate pad and the gate finger, wherein the additional gate resistor is at least partially located on the active region of the transistor device.

[0078] 4. A group III nitride transistor device according to any one of Examples 1 to 3, wherein a plurality of source fingers, a plurality of gate fingers and a plurality of drain fingers are provided, and the gate fingers are electrically connected to each other through gate channels, wherein gate resistors are electrically coupled between the gate channels and gate pads.

[0079] 5. A group III nitride transistor device according to any one of Examples 1 to 4, wherein the gate resistor comprises a planar metal trace.

[0080] 6. A group III nitride transistor device according to Example 5, wherein the metal trace includes at least one bend, the bend comprising: two substantially parallel elongated metal traces having first ends; and a bend connecting the first ends of the two substantially parallel metal traces.

[0081] 7. The group III nitride transistor device according to Example 6 further includes an intermediate connection trace extending from a second end of one of two substantially parallel elongated traces, the second end being opposite to the first end, wherein the intermediate connection trace is substantially parallel to one of the two substantially parallel elongated traces and a bend-connected metal trace extending to a gate via.

[0082] 8. A group III nitride transistor device according to any one of Examples 1 to 7, wherein a gate resistor is disposed above and spaced apart from at least a portion of the source fingers, gate fingers and drain fingers.

[0083] 9. A group III nitride transistor device according to Example 8, wherein an electrically insulating layer is disposed on at least a portion of the source fingers, gate fingers and drain fingers and on a group III nitride barrier layer, and a gate resistor is disposed on the electrically insulating layer.

[0084] 10. A group III nitride transistor device according to any one of Examples 7 to 9, wherein a gate via extends through an electrically insulating layer and extends between a gate channel and a metal trace of a gate resistor.

[0085] 11. A group III nitride transistor device according to Example 9 or Example 10, wherein the gate pad is located on an electrically insulating layer.

[0086] 12. A group III nitride transistor device according to any one of Examples 1 to 11, wherein the source pad, gate pad, and drain pad are positioned laterally adjacent to each other on a group III nitride barrier layer.

[0087] 13. A group III nitride transistor device according to any one of Examples 1 to 12, further comprising a support substrate, the support substrate including a first main surface capable of supporting epitaxial growth of at least one group III nitride layer and a second main surface opposite to the first main surface, wherein a group III nitride channel layer is disposed on the first main surface of the support substrate, and a gate resistor is disposed on and electrically insulated therefrom on the second main surface of the support substrate.

[0088] 14. A group III nitride transistor device according to Example 13, wherein the support substrate comprises a material other than group III nitride.

[0089] 15. A group III nitride transistor device according to any one of Examples 1 to 14, wherein the metal traces form part of a metallization structure on a second main surface of a group III nitride barrier layer or a supporting substrate.

[0090] 16. A group III nitride transistor device according to any one of Examples 13 to 15, wherein a gate resistor is formed in a recess in a second main surface of a supporting substrate.

[0091] 17. A group III nitride transistor device according to Example 16, wherein the groove has a tortuous shape.

[0092] 18. A group III nitride transistor device according to Example 16 or Example 17, wherein the recess is padded with an electrically insulating pad layer, and the metal trace is located on the electrically insulating pad layer in the recess and forms a gate resistor.

[0093] 19. A group III nitride transistor device according to Example 18, wherein the gate resistor is electrically insulated from the second main surface of the support substrate by an additional electrically insulating layer disposed on the second main surface of the support substrate, and the gate resistor has the form of a planar metal trace located on the additional electrically insulating layer.

[0094] 20. A group III nitride transistor device according to any one of Examples 13 to 19, wherein a gate resistor is coupled to a gate finger through at least one conductive via, the at least one conductive via extending from a second main surface of a supporting substrate through the supporting substrate, through the group III nitride body, to a gate channel located on a group III nitride barrier layer.

[0095] 21. A group III nitride transistor device according to any one of Examples 1 to 20, wherein the source pad and the gate pad are located on a second main surface of the supporting substrate, and the drain pad is located on a group III nitride barrier layer.

[0096] 22. The group III nitride transistor device according to Example 21 further includes one or more conductive vias extending between a source pad on a second main surface of a support substrate and a source bus on a group III nitride barrier layer.

[0097] 23. A group III nitride transistor device according to any one of Examples 1 to 7, wherein the drain pad and the gate pad are located on a group III nitride barrier layer, and the source pad is located on a second main surface of the supporting substrate.

[0098] 24. The group III nitride transistor device according to Example 23 further includes one or more conductive vias extending between a source pad on a second main surface of a support substrate and a source bus on a group III nitride barrier layer.

[0099] 25. A group III nitride transistor device according to any one of Examples 1 to 24, wherein the group III nitride layer further includes a group III nitride buffer structure disposed on a first main surface of a support substrate, and a group III nitride channel layer is disposed on the group III nitride buffer structure.

[0100] 26. A group III nitride transistor device according to any one of Examples 1 to 25, wherein the group III nitride transistor device is a HEMT.

[0101] 27. A group III nitride transistor device according to any one of Examples 1 to 26, wherein the electrically insulating layer is formed of an oxide or a nitride.

[0102] 28. A group III nitride transistor device according to any one of Examples 1 to 27, wherein the electrically insulating layer is formed of silicon dioxide.

[0103] 29. A group III nitride transistor device according to any one of Examples 1 to 28, wherein the supporting substrate is formed of a single-crystal silicon substrate.

[0104] 30. A group III nitride transistor device according to Example 29, wherein the first main surface of the single-crystal silicon substrate has <111> Orientation.

[0105] For ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to cover orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the description, the same terms refer to the same element.

[0106] As used herein, the terms "having," "comprising," "including," "including," etc., are open-ended terms that indicate the presence of a stated element or feature but do not exclude additional elements or features. The quantifiers "a," "an," and the pronoun "the" are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is understood that features of the various embodiments described herein may be combined with each other unless specifically indicated otherwise.

[0107] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A group III nitride transistor device, comprising: The group III nitride body (11) includes an active region (15) contributing to the load switch, a group III nitride channel layer (12), and a group III nitride barrier layer (13) disposed on the group III nitride channel layer (12) and forming a heterojunction (14) therebetween. Source fingers (16), gate fingers (17) and drain fingers (18) are arranged on a group III nitride barrier layer (13); Source pad (19) electrically coupled to source finger (16), gate pad (20) coupled to gate finger (17), and drain pad (21) coupled to drain finger (18). A gate resistor (22) is electrically coupled between the gate pad (20) and the gate finger (17) of the transistor device (10, 10', 10'', 10'''). The gate resistor (22) is located at least partially on the active region (15) of the transistor device (10, 10', 10'', 10''').

2. The group III nitride transistor device according to claim 1, wherein a plurality of source fingers (16), a plurality of gate fingers (17) and a plurality of drain fingers (18) are provided, and the gate fingers (17) are electrically connected to each other through a gate channel (63), wherein a gate resistor (22) is electrically coupled between the gate channel (63) and the gate pad (20).

3. The group III nitride transistor device according to claim 1 or 2, wherein the gate resistor (22) comprises a planar metal trace.

4. The group III nitride transistor device according to claim 3, wherein the metal trace includes at least one bend, the bend comprising two substantially parallel elongated metal traces (28; 28') having a first end and a bend-connecting metal trace (29) connecting the first ends of the two substantially parallel metal traces (28, 28').

5. The group III nitride transistor device of claim 4, further comprising an intermediate connection trace (30; 31) extending from a second end of one of the two substantially parallel elongated traces (28), the second end being opposite to the first end, wherein the intermediate connection trace (30; 31) is substantially parallel to one of the two substantially parallel elongated traces (28) and the bend-connected metal trace (29) of the bend extends to the gate via (25).

6. The group III nitride transistor device according to any one of claims 1 to 5, wherein the gate resistor (22) is disposed over at least a portion of the source finger (16), the gate finger (17) and the drain finger (18) and spaced apart from at least a portion of the source finger (16), the gate finger (17) and the drain finger (18).

7. The group III nitride transistor device according to claim 6, wherein the electrical insulating layer (23) is disposed on at least a portion of the source finger (16), the gate finger (17) and the drain finger (18) and on the group III nitride barrier layer (13), and the gate resistor (22) is disposed on the electrical insulating layer (23).

8. The group III nitride transistor device according to any one of claims 5 to 7, wherein the gate via (25) extends through the electrically insulating layer (23) and extends between the gate channel (63) and the metal trace of the gate resistor (22).

9. The group III nitride transistor device according to claim 7 or claim 8, wherein the gate pad (20) is located on the electrically insulating layer (23).

10. The group III nitride transistor device according to any one of claims 1 to 9, wherein the source pad (19), the gate pad (20) and the drain pad (21) are positioned laterally adjacent to each other on the group III nitride barrier layer (13).

11. The group III nitride transistor device according to any one of claims 1 to 5, further comprising a support substrate (40) including a first main surface (41) capable of supporting epitaxial growth of at least one group III nitride layer and a second main surface (43) opposite to the first main surface (41), wherein a group III nitride channel layer (12) is disposed on the first main surface (41) of the support substrate (40), and a gate resistor (22) is disposed on and electrically insulated from the second main surface (43) of the support substrate (40).

12. The group III nitride transistor device according to claim 11, wherein the gate resistor (22) is formed in a groove (82) in a second main surface (43) of a support substrate (40).

13. The group III nitride transistor device according to claim 12, wherein the groove (82) has a tortuous shape.

14. The group III nitride transistor device according to claim 12 or claim 13, wherein the recess (82) is padded with an electrically insulating pad layer (83), and a metal layer is located on the electrically insulating pad layer (83) in the recess (82) and forms a gate resistor (22).

15. The group III nitride transistor device according to claim 11, wherein the gate resistor (22) is electrically insulated from the second main surface (43) of the support substrate (40) by a planar electrically insulating layer (23) disposed on the second main surface (43) of the support substrate (40), and the gate resistor (22) has the form of a planar metal trace located on the planar electrically insulating layer (23).

16. The group III nitride transistor device according to any one of claims 11 to 15, wherein the gate resistor (22) is coupled to the gate finger (17) through at least one conductive via (71), the at least one conductive via (71) extending from the second main surface (43) of the support substrate (40) through the support substrate (40), through the group III nitride body (11) to the gate channel (63) located on the group III nitride barrier layer (13).

17. The group III nitride transistor device according to any one of claims 1 to 16, wherein the source pad (19) and the gate pad (20) are located on the second main surface (43) of the support substrate (40), and the drain pad (21) is located on the group III nitride barrier layer (13).

18. The group III nitride transistor device of claim 17 further includes one or more conductive vias (70) extending between a source pad (19) on a second main surface (43) of a support substrate (40) and a source bus (57) on a group III nitride barrier layer (13).

19. The group III nitride transistor device according to any one of claims 1 to 5, wherein the drain pad (21) and the gate pad (20) are located on the group III nitride barrier layer (13), and the source pad (19) is located on the second main surface (43) of the support substrate (40).

20. The group III nitride transistor device of claim 19 further includes one or more conductive vias (70) extending between a source pad (19) on a second main surface (43) of a support substrate (40) and a source bus (57) on a group III nitride barrier layer (13).

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