High-efficiency GaN-based HEMT chip and manufacturing method
CN122995188APending Publication Date: 2026-10-27淄博美林电子有限公司
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Patent Information
- Application Number
- CN202610912491.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-24
- Publication Date
- 2026-10-27
AI Technical Summary
Technical Problem
[0003]当前常规平面结构的 GaN 基 HEMT 芯片,其源极(S)、漏极(D)的电极 Pad 均直接布置在芯片的有源导电区域上方,该设计存在三大核心缺陷:其一,源漏极 Pad 占用了芯片大量的有效导电面积,压缩了器件有源区的可用空间,直接限制了器件电流密度与功率密度的提升;其二,源漏极 Pad 的面积受限于有源区尺寸,无法根据封装键合需求灵活拓展,增大了封装键合的工艺难度,也影响了器件长期工作的可靠性;其三,源漏极与对应Pad 之间的电流传输路径长,接触电阻大,导致器件导电效率低、导通损耗高,高频工作特性受到显著制约
Benefits of technology
本发明将漏极 Pad 与源极 Pad 完全布置于芯片有源导电区域的外侧,彻底解决了传统结构中 Pad 占用有效导电面积的问题,最大化利用了芯片的有源区空间,可显著提升器件的电流密度与功率密度。
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Abstract
The application discloses a kind of efficient GaN base HEMT chip, including semiconductor substrate, buffer layer, channel layer, barrier layer, dielectric layer, source and drain are equipped with in dielectric layer two sides, the drain corresponding formation has drain gate, the source corresponding formation has source gate, the drain gate and source gate are all located in the active conductive channel area of chip;First metallization via hole that is opened in the drain gate has been passed through dielectric passivation layer, second metallization via hole that is opened in the source gate has been passed through dielectric passivation layer;Chip surface is provided with drain pad and source pad, the drain pad is directly electrically connected with drain gate by first metallization via hole, the source pad is directly electrically connected with source gate by second metallization via hole;On the premise of not occupying chip active conductive area completely, realize the flexible extension of source drain Pad area, while shortening current transmission path, reduce contact resistance, significantly improve the conductive efficiency, power density and working reliability of device.
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