A p-gan hemt device with a stacked dielectric and a method of fabricating the same

Abstract

The application discloses a kind of p-GaN HEMT devices with laminated medium and preparation method thereof, belong to semiconductor device technical field.The device of the application is sequentially arranged on AlGaN barrier layer, interlayer, p-GaN cap layer, Si3N4 / AlN laminated dielectric layer and gate metal layer, through interlayer as etching stop layer, device is prepared by precise gradient dry etching process.The application can realize etching automatic termination, completely avoid etching damage of traditional process to barrier layer, reduce interface state density;Laminated medium structure effectively improves the anti-radiation performance of device, inhibits the performance degradation of device caused by high-energy particle radiation;At the same time, through lattice matching optimization and asymmetric gate structure, the device current collapse problem is completely solved.The application process is simple, controllability is strong, and the electrical stability of the device is excellent, high temperature and high pressure reliability, suitable for the large-scale application of radiation environment, high-frequency communication and other scenes.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a p-GaN HEMT device with a multilayer dielectric and its fabrication method. Background Technology

[0002] HEMTs (High Electron Mobility Transistors) leverage the modulation and doping characteristics of semiconductor heterojunctions to form a high-density, high-mobility two-dimensional electron gas (2DEG) at the interface between the channel layer and the barrier layer. This results in excellent high-frequency, high-voltage, and high-speed operating performance, making them core power devices in fields such as communications, radar, and aerospace. A typical GaN HEMT device mainly consists of a substrate, a buffer layer, a GaN channel layer, and an AlGaN barrier layer. The gate, source, and drain are fabricated above the barrier layer. The device's switching characteristics are achieved by controlling the depletion and conduction of the 2DEG through the gate voltage.

[0003] Currently, commercial GaN HEMT devices generally suffer from two major problems: current collapse and etching process damage. Furthermore, their insufficient radiation resistance severely limits their application in extreme radiation environments. To suppress current collapse, the mainstream industry approach is to fabricate a p-GaN cap layer on the AlGaN barrier layer. This utilizes the depletion effect of the p-type semiconductor to eliminate the "virtual gate" effect on the device surface and stabilize the 2DEG concentration. However, traditional p-GaN gate fabrication employs a process of overall deposition followed by dry etching for patterning. The etching amount in dry etching is difficult to control precisely, easily leading to over-etching, which directly damages the underlying AlGaN barrier layer, disrupts the heterojunction interface structure, and causes 2DEG concentration decay and increased interface state density, significantly reducing the device's electrical performance and reliability. Simultaneously, conventional single-layer passivation dielectric structures have weak radiation resistance. High-energy particle radiation easily generates defects inside the device and activates carrier traps, causing leakage, threshold drift, and output power decay. This fails to meet the requirements of extreme applications such as aerospace and nuclear industries. Moreover, traditional fabrication processes are complex and lack controllability, hindering large-scale mass production. Summary of the Invention

[0004] Technical problem solved: To address the above-mentioned technical problems, the present invention provides a p-GaN HEMT device with a multilayer dielectric and its fabrication method, which can effectively solve the technical defects of existing p-GaN HEMT devices, such as easy damage to the barrier layer during etching, significant current collapse effect, poor radiation resistance, and low process controllability.

[0005] Technical solution: In a first aspect, the present invention provides a p-GaN HEMT device with a stacked dielectric layer, comprising a substrate, a buffer layer, a GaN channel layer and an AlGaN barrier layer arranged sequentially from bottom to top. An insertion layer, a p-GaN cap layer, a first stacked dielectric layer, a second stacked dielectric layer and a gate metal layer are stacked sequentially on top of the AlGaN barrier layer. A source and a drain are disposed on opposite sides of the AlGaN barrier layer, and both the source and drain penetrate the stacked dielectric layer to form ohmic contacts with the insertion layer and the AlGaN barrier layer.

[0006] Preferably, the insertion layer is an InGaN or AlInN compound semiconductor layer with a thickness of 10-20 nm. The insertion layer is lattice-matched with the AlGaN barrier layer and the p-GaN cap layer, and is used as a dry etching barrier layer to avoid damage to the barrier layer.

[0007] Furthermore, the thickness of the insertion layer is 10–20 nm.

[0008] Preferably, the p-GaN cap layer has a thickness of 30–60 nm, and the horizontal distance between the p-GaN cap layer and the source electrode is smaller than the horizontal distance between the p-GaN cap layer and the drain electrode. By optimizing the electric field distribution of the device through the asymmetric structure, current collapse is further suppressed.

[0009] Preferably, the first stacked dielectric layer is a Si3N4 dielectric layer with a thickness of 50-60 nm; the second stacked dielectric layer is an AlN dielectric layer with a thickness of 60-70 nm, and the first stacked dielectric layer and the second stacked dielectric layer are stacked sequentially on the surface of the p-GaN cap layer from top to bottom.

[0010] Preferably, the gate metal layer is a tungsten metal layer with a thickness of 40-50 nm, forming a highly stable Schottky contact with the p-GaN cap layer.

[0011] Preferably, the overall surface of the device is provided with a passivation layer, which is a SiO2, Sc2O3 or Al2O3 dielectric layer with a thickness of 8-10 nm, used to passivate surface defects of the device and suppress electron trapping effect.

[0012] In a second aspect, the present invention provides a method for fabricating a p-GaN HEMT device with a multilayer dielectric as described in the first aspect, comprising the following steps: (1) Substrate pretreatment: A buffer layer, a GaN channel layer and an AlGaN barrier layer are epitaxially grown sequentially on the substrate surface to complete the fabrication of the device substrate structure; (2) Deposition of stacked functional layers: A compound semiconductor insertion layer with a thickness of 10-20 nm is epitaxially grown on the surface of the AlGaN barrier layer using MOCVD vapor deposition. Then, a first stacked dielectric layer of Si3N4 with a thickness of 50-60 nm and a second stacked dielectric layer of AlN with a thickness of 60-70 nm are sequentially deposited on the surface of the insertion layer. (3) Gate region etching: The gate preset region is first etched using a dry etching process. The etching gas ratio is BCl3:Cl2:Ar=1:1:1.2~1.6, the etching power is 30W, and the etching process is automatically stopped at the surface of the insertion layer to remove the two stacked dielectric layers of the gate region and expose the insertion layer gate preparation area. (4) p-GaN gate fabrication: A p-GaN cap layer is deposited on the exposed insertion layer surface by a secondary epitaxial process, and then a tungsten metal layer is deposited on the p-GaN cap layer surface by electron beam evaporation. After patterning, a gate metal layer is formed. (5) Source and drain region dielectric etching: The source and drain preset regions are etched a second time. The etching gas ratio is BCl3:Cl2:Ar=1:1:1.2~1.6, the etching power is 30W, the first stacked dielectric layer and the second stacked dielectric layer of the source and drain regions are removed, and the etching ends at the insertion layer. (6) Etching of the insertion layer in the source and drain region: The third etching is carried out by a modified dry etching process. The etching gas ratio is BCl3:Cl2:H=1:1:1.1~1.3, the etching power is 10W, and the insertion layer in the source and drain region is completely removed, exposing the AlGaN barrier layer below. (7) Source and drain fabrication: A multilayer metal system is deposited on the surface of the exposed AlGaN barrier layer by electron beam evaporation, and the source and drain are formed by ohmic alloy annealing. At the same time, the field plate structure and external pins are formed. (8) Overall passivation treatment: Low pressure chemical vapor deposition (LPCVD) is used to deposit a passivation layer on the overall surface of the device, the wafer is planarized, and the leads are brought out through the window to complete the device fabrication.

[0013] Beneficial effects: 1) Completely avoids barrier layer etching damage and has strong process stability: The present invention sets a compound semiconductor insertion layer between the barrier layer and the gate structure, which is used as a barrier layer for dry etching. The etching is automatically terminated through a matching etching process, which completely avoids the problem of over-etching damage to the AlGaN barrier layer in traditional processes, effectively reduces the heterojunction interface state density, stabilizes the 2DEG concentration, and greatly improves the electrical consistency of the device. 2) Effectively suppress current collapse effect: The insertion layer can achieve perfect lattice matching between the barrier layer and the p-GaN cap layer, optimize the interface flatness, and reduce interface defects; combined with the asymmetric p-GaN cap layer structure, it can effectively deplete excess electrons in the channel and eliminate the surface "virtual gate" effect. At the same time, the surface passivation layer can suppress electron trapping. Multiple mechanisms work together to solve the device current collapse problem. 3) Excellent radiation resistance and suitable for extreme scenarios: The Si3N4 / AlN double-layer stacked dielectric structure can effectively block the incidence of high-energy particles, shorten the movement path of particles inside the device, suppress the generation of radiation-induced defects, alleviate the problems of device threshold drift and increased leakage current caused by radiation, and greatly improve the working stability of the device in the radiation environment. 4) Simple process, suitable for mass production: Through precise control of etching by the insertion layer, there is no need for complicated etching accuracy calibration process, which reduces the processing difficulty; the gate secondary epitaxial process has high forming quality, and the device gate control capability and high-temperature and high-pressure operation reliability are significantly improved, which has high industrial promotion value. Attached Figure Description

[0014] Figures 1-2 This is a schematic diagram of the cross-sectional structure of the device after the deposition of the stacked dielectric and the insertion layer according to the present invention; Figures 3-4 This is a schematic diagram of the process structure for etching the source / drain region dielectric and the insertion layer in this invention; Figure 5 This is a schematic diagram of the structure of the p-GaN gate after fabrication according to the present invention; Figure 6 This is a schematic cross-sectional view of the complete p-GaN HEMT device of the present invention; Figure 7 The transfer characteristic curves of the p-GaN HEMT device of this invention are shown below. Figure 8 The output characteristic curve of the p-GaN HEMT device of this invention is shown. Figure 9 This is the breakdown characteristic curve of the p-GaN HEMT device of the present invention; Figure 10 This is a comparison of the breakdown characteristic curves of the example sample and the ordinary device sample after irradiation experiments; The numbers in the figure are: 11, substrate; 12, AlGaN barrier layer; 13, p-GaN cap layer; 14, first stacked dielectric layer; 15, second stacked dielectric layer; 16, gate metal layer; 20, insertion layer; 21, source; 22, drain; 23, passivation layer. Detailed Implementation

[0015] The present invention will be described in detail below with reference to specific embodiments: Example 1

[0016] like Figure 6 As shown, a p-GaN HEMT device with a stacked dielectric layer has a substrate 11 composed of a substrate, a buffer layer, a GaN channel layer, and an AlGaN barrier layer 12 stacked from bottom to top. The upper surface of the AlGaN barrier layer 12 is sequentially provided with a 15nm thick InGaN insertion layer 20, a 45nm thick p-GaN cap layer 13, a 55nm thick Si3N4 first stacked dielectric layer 14, a 65nm thick AlN second stacked dielectric layer 15, and a 45nm thick tungsten gate metal layer 16.

[0017] The tungsten metal layer of the gate metal layer 16 has a high work function and good thermal stability, and can form a high-quality Schottky contact with the cap layer 13. The source 21 and drain 22 are respectively disposed on both sides of the gate. The horizontal distance between the p-GaN cap layer 13 and the source 21 is smaller than the horizontal distance between the p-GaN cap layer 13 and the drain 22. The asymmetric structure can optimize the electric field distribution of the device and suppress high voltage leakage.

[0018] A 10 nm thick Al2O3 passivation layer 23 is deposited on the overall surface of the device, which can effectively passivate surface defects, block the interaction between the external environment and the functional layer of the device, further stabilize the electrical performance of the device and improve its radiation resistance. The InGaN insertion layer 20 has the dual functions of lattice matching and etching barrier, which not only ensures the growth quality of the p-GaN cap layer 13, but also precisely terminates dry etching and protects the AlGaN barrier layer 12 from damage. Example 2

[0019] The fabrication method of the p-GaN HEMT device with stacked dielectrics described in Example 1, as follows: Figures 1-6 As shown, it includes the following steps: (1) Substrate pretreatment: A buffer layer, a GaN channel layer and an AlGaN barrier layer 12 are epitaxially grown sequentially on the substrate surface to complete the fabrication of the device substrate 11 structure.

[0020] (2) Deposition of stacked functional layers: A 15 nm thick InGaN insertion layer 20 was epitaxially grown on the surface of the AlGaN barrier layer using MOCVD vapor deposition. The insertion layer 20 can achieve lattice matching with the subsequent p-GaN layer, which can improve the electron mobility between p-GaN and the barrier layer 12. In addition, it can form a smooth interface with GaN, reduce the interface state density, and suppress the current collapse effect. Subsequently, a 55 nm Si3N4 first stacked dielectric layer and a 65 nm AlN second stacked dielectric layer were sequentially deposited on the surface of the insertion layer. The two stacked dielectric layers can effectively alleviate the radiation effect caused by high-energy particles incident on the device, improve the device's radiation resistance, and suppress the device's current collapse.

[0021] (3) Gate region etching: The gate preset region is etched by dry etching process. The etching gas ratio is BCl3:Cl2:Ar=1:1:1.4, the etching power is 30W, and the etching process is automatically stopped at the surface of the insertion layer to remove the two stacked dielectric layers of the gate region and expose the insertion layer gate preparation area.

[0022] (4) p-GaN gate fabrication: A p-GaN cap layer is deposited on the exposed insertion layer 20 using a secondary epitaxial process, directly covering the AlGaN surface in the active region. This effectively passivates the AlGaN surface states and, as a conductive p-type layer, provides a low-impedance release path for the charge, quickly conducting the charge away and avoiding the formation of a "virtual gate". Subsequently, a tungsten metal layer is deposited on the surface of the p-GaN cap layer 13 using electron beam evaporation, and after patterning, a gate metal layer 16 is formed. (5) Source and drain region dielectric etching: The source 21 and drain 22 preset regions are etched for the second time. The etching gas ratio is BCl3:Cl2:Ar=1:1:1.4, the etching power is 30W, the first stacked dielectric layer 14 and the second stacked dielectric layer 15 of the source and drain regions are removed, and the etching ends at the insertion layer 20. (6) Etching of the insertion layer in the source and drain region: The third etching is carried out by the modified dry etching process. The etching gas ratio is BCl3:Cl2:H=1:1:1.2, the etching power is 10W, and the insertion layer 20 in the source and drain region is completely removed, exposing the AlGaN barrier layer 12 below. (7) Source and drain fabrication: A multilayer metal system is deposited on the surface of the bare AlGaN barrier layer by electron beam evaporation, and the source 21 and drain 22 are formed by ohmic alloy annealing process. At the same time, the field plate structure and external pins are formed. (8) Overall passivation treatment: Low pressure chemical vapor deposition (LPCVD) is used to deposit a passivation layer 23 on the overall surface of the device, the wafer is planarized, and the leads are brought out through the window to complete the device fabrication.

[0023] Performance testing: The device prepared in Example 2 was subjected to performance testing, mainly testing the basic electrical characteristics of the device, and testing the changes in threshold voltage and gate leakage current under thermal and electrical stress.

[0024] (1) Test the basic electrical characteristics of the device using a 4200 semiconductor analyzer and plot the results. Figure 7 The transfer characteristic curve of the device is shown. The test results show that the device fabricated by this process has a threshold voltage of 2.21V, which can effectively prevent false activation. Figure 8 The output characteristic curve of the device is shown, and the on-resistance of the device is 25mΩ; Figure 9The breakdown characteristic curve of the device is shown. The test results show that the leakage current of the device at 200V is only 19nA, which is much lower than that of ordinary devices.

[0025] (2) Test the changes in the basic electrical characteristics of the device after extreme experiments using a 4200 semiconductor analyzer and plot the results. Figure 10 By comparing the breakdown characteristic curves of the example sample (the sample prepared in Example 2) and the ordinary device sample (the control sample) after the irradiation experiment, it can be found that the leakage current rise of this example is smaller at 200V after the irradiation experiment.

[0026] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A p-GaN HEMT device with a multilayer dielectric, characterized in that: The device comprises, from bottom to top, a substrate, a buffer layer, a GaN channel layer, and an AlGaN barrier layer. Above the AlGaN barrier layer, an insertion layer, a p-GaN cap layer, a first stacked dielectric layer, a second stacked dielectric layer, and a gate metal layer are stacked in sequence. Source and drain electrodes are respectively disposed on both sides of the AlGaN barrier layer. The source and drain electrodes penetrate the stacked dielectric layer and form ohmic contacts with the insertion layer and the AlGaN barrier layer.

2. The p-GaN HEMT device with a multilayer dielectric according to claim 1, characterized in that: The insertion layer is an InGaN or AlInN compound semiconductor layer with a thickness of 10–20 nm.

3. A p-GaN HEMT device with a multilayer dielectric according to claim 2, characterized in that: The thickness of the insertion layer is 10–20 nm.

4. A p-GaN HEMT device with a multilayer dielectric according to claim 1, characterized in that: The p-GaN cap layer has a thickness of 30–60 nm, and the horizontal distance between the p-GaN cap layer and the source electrode is smaller than the horizontal distance between the p-GaN cap layer and the drain electrode.

5. A p-GaN HEMT device with a multilayer dielectric according to claim 1, characterized in that: The first stacked dielectric layer is a Si3N4 dielectric layer with a thickness of 50-60 nm; the second stacked dielectric layer is an AlN dielectric layer with a thickness of 60-70 nm. The first stacked dielectric layer and the second stacked dielectric layer are stacked sequentially from top to bottom on the surface of the p-GaN cap layer.

6. A p-GaN HEMT device with a multilayer dielectric according to claim 1, characterized in that: The gate metal layer is a tungsten metal layer with a thickness of 40-50 nm.

7. A p-GaN HEMT device with a multilayer dielectric according to claim 1, characterized in that: The device has a passivation layer on its overall surface. The passivation layer is a SiO2, Sc2O3 or Al2O3 dielectric layer with a thickness of 8-10 nm.

8. A method for fabricating a p-GaN HEMT device with a multilayer dielectric as described in any one of claims 1-7, characterized in that, Includes the following steps: (1) Substrate pretreatment: A buffer layer, a GaN channel layer and an AlGaN barrier layer are epitaxially grown sequentially on the substrate surface to complete the fabrication of the device substrate structure; (2) Deposition of stacked functional layers: A compound semiconductor insertion layer with a thickness of 10-20 nm is epitaxially grown on the surface of the AlGaN barrier layer using MOCVD vapor deposition. Then, a first stacked dielectric layer of Si3N4 with a thickness of 50-60 nm and a second stacked dielectric layer of AlN with a thickness of 60-70 nm are sequentially deposited on the surface of the insertion layer. (3) Gate region etching: The gate preset region is first etched using a dry etching process. The etching gas ratio is BCl3:Cl2:Ar=1:1:1.2~1.6, the etching power is 30W, and the etching process is automatically stopped at the surface of the insertion layer to remove the two stacked dielectric layers of the gate region and expose the insertion layer gate preparation area. (4) p-GaN gate fabrication: A p-GaN cap layer is deposited on the exposed insertion layer surface by a secondary epitaxial process, and then a tungsten metal layer is deposited on the p-GaN cap layer surface by electron beam evaporation. After patterning, a gate metal layer is formed. (5) Source and drain region dielectric etching: The source and drain preset regions are etched a second time. The etching gas ratio is BCl3:Cl2:Ar=1:1:1.2~1.6, the etching power is 30W, the first stacked dielectric layer and the second stacked dielectric layer of the source and drain regions are removed, and the etching ends at the insertion layer. (6) Etching of the insertion layer in the source and drain region: The third etching is carried out by a modified dry etching process. The etching gas ratio is BCl3:Cl2:H=1:1:1.1~1.3, the etching power is 10W, and the insertion layer in the source and drain region is completely removed, exposing the AlGaN barrier layer below. (7) Source and drain fabrication: A multilayer metal system is deposited on the surface of the bare AlGaN barrier layer by electron beam evaporation, and the source and drain are formed by ohmic alloy annealing. At the same time, the field plate structure and external pins are formed. (8) Overall passivation treatment: Low pressure chemical vapor deposition (LPCVD) is used to deposit a passivation layer on the overall surface of the device, the wafer is planarized, and the leads are brought out through the window to complete the device fabrication.

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