Staircase super junction enhanced HEMT device with buried layer and method of manufacturing the same
Patent Information
- Application Number
- CN202611075276.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-20
- Publication Date
- 2026-10-27
AI Technical Summary
但传统超结结构制备工艺复杂，且难以与增强型栅极结构实现兼容，不仅无法有效降低导通损耗，还制约了器件的开关速度与集成度，未能从根本上解决传统HEMT的性能短板
[0031]（1）实现稳定可靠的增强型工作模式： 本发明采用单一金属材料作为栅极，结合P+型GaN增强型栅极（P-GaN帽层）与P+型电流阻挡层（重掺阻挡层）的协同设计，利用其中多数载流子的正电性，将GaN/AlGaN异质结导带抬高至费米能级之上，使i-GaN沟道层与i-AlGaN势垒层共同形成的二维电子气（2DEG）沟道仅在栅源电压大于零时才能恢复，由此成功实现了增强型器件特性，有效解决了传统增强型HEMT阈值电压不稳定的问题。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, specifically to a stepped superjunction enhanced HEMT device with a buried layer and its fabrication method. Background Technology
[0002] In recent years, with the rapid iteration of new energy vehicles, smart grids, high-frequency communications, and other fields, the performance requirements for high voltage, high frequency, low loss, and high reliability of power electronic devices have become increasingly urgent. Improving withstand voltage and reducing conduction losses have become the core demands driving the upgrading of power electronics technology.
[0003] High electron mobility transistors (HEMTs) have shown broad application prospects in high-voltage power conversion scenarios due to their inherent advantages such as high electron mobility, low on-resistance, and fast switching speed. Compared with traditional silicon-based power MOSFETs, HEMT devices based on wide-bandgap semiconductor materials can operate stably at higher temperatures, voltages, and frequencies, effectively reducing conduction losses and improving withstand voltage, making them the preferred devices in the field of high-voltage power conversion.
[0004] However, existing HEMT devices still have the following shortcomings:
[0005] First, the breakdown voltage capability is limited. Traditional HEMT devices are limited by inherent defects in the gate structure design and the uneven electric field distribution between the drain and source, making it difficult to further improve the breakdown voltage capability. In high-voltage applications, breakdown is prone to occur, which seriously affects the reliability of the device.
[0006] Secondly, the electrical performance of enhancement-mode devices is unstable. Traditional enhancement-mode HEMT devices generally suffer from unstable threshold voltage and high conduction losses, which greatly limits their large-scale application in medium and high voltage power conversion.
[0007] Third, the introduction of superjunction structures brings new problems. To improve breakdown voltage, superjunction structures have been introduced into HEMT designs, achieving a uniform distribution of the internal electric field through alternating P-type and N-type semiconductor layers. However, the fabrication process of traditional superjunction structures is complex and difficult to be compatible with enhancement-mode gate structures. This not only fails to effectively reduce conduction losses but also restricts the switching speed and integration density of devices, failing to fundamentally solve the performance shortcomings of traditional HEMTs.
[0008] Therefore, it is urgent to solve the problems existing in traditional HEMT devices. Summary of the Invention
[0009] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a stepped superjunction enhanced HEMT device with a buried layer. It adopts a stepped superjunction and introduces a buried layer to improve the electric field modulation in the drift region, increase the breakdown voltage, optimize the current path, and effectively meet the performance requirements of high withstand voltage and low on-resistance.
[0010] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: a stepped superjunction enhancement-mode HEMT device with a buried layer, comprising, from bottom to top, a drain, a buffer layer, a drift region, a lightly doped barrier layer, a buried layer, an i-GaN channel layer, an i-AlGaN barrier layer, a P-GaN cap layer, and a gate; wherein...
[0011] Three P-GaN pillars with decreasing lateral length and doping concentration are arranged at intervals from top to bottom on both the left and right sides of the drift region.
[0012] A lightly doped barrier layer is stacked, and a heavily doped barrier layer is set on both the left and right sides of the buried layer;
[0013] The i-GaN channel layer and the i-AIGaN barrier layer together form a two-dimensional electron gas channel, and the source is set on the left and right sides of the two-dimensional electron gas channel.
[0014] Each source is separated from the stacked P-GaN cap layer and gate by a SiN passivation layer.
[0015] Furthermore, a Schottky contact is used between the P-GaN cap layer and the gate.
[0016] Furthermore, the doping concentration of the P-GaN cap layer is 3×10⁻⁶. 17 cm -3 .
[0017] Furthermore, the drift region is lightly doped with n-type doping, with a doping concentration of 1×10⁻⁶. 16 cm -3
[0018] Furthermore, the heavily doped barrier layer is p-doped with a doping concentration of 1×10⁻⁶. 17 cm -3 ~3×10 18 cm -3 between.
[0019] Furthermore, the lightly doped barrier layer is lightly doped with P, and its doping concentration is 1×10⁻⁶. 15 cm -3 .
[0020] Furthermore, the buried layer is lightly doped with nitrogen (N), with a doping concentration of 5 × 10⁻⁶. 15 cm -3 .
[0021] Furthermore, the doping concentration of the three P-GaN pillars on each side decreases from 4 × 10⁻⁶ from top to bottom. 16 cm -3 Decrease sequentially to 1×10 16 cm -3 .
[0022] Furthermore, the buffer layer is N-fold doped with a concentration of 1×10⁻⁶. 19 cm -3 .
[0023] This invention also relates to a method for fabricating a stepped superjunction enhanced HEMT device with a buried layer, comprising:
[0024] S1, Buffer layer and drain preparation: Take a flat substrate, deposit an N-fold doped layer under the substrate using MOCVD process and anneal it to obtain a buffer layer, and deposit the drain under the buffer layer.
[0025] S2, Drift Region and Superjunction Formation: Remove the substrate, grow the drift region on the exposed buffer layer using MOCVD, etch a stepped groove using ICP and grow a stepped three-section P-GaN pillar, and simultaneously deposit a lightly doped barrier layer and a buried layer, leaving space between the left and right sides of the lightly doped barrier layer and the corresponding side of the drift region.
[0026] S3, Preparation of heavy barrier layer and channel: Heavy-doped barrier layers are deposited on the left and right sides of the drift region; GaN channel layer and i-AlGaN barrier layer are grown sequentially on the buried layer to form a two-dimensional electron gas channel;
[0027] S4, Cap and Gate Fabrication: A P-GaN cap and a single metal gate are sequentially deposited on the i-AlGaN barrier layer;
[0028] S5, Metal Deposition: Source electrodes are deposited on both sides of the channel, followed by annealing;
[0029] S6, Passivation layer formation: A passivation layer is deposited between each source and the stacked P-GaN cap layer and gate.
[0030] By adopting the above technical solution, the present invention has the following beneficial effects:
[0031] (1) Achieving a stable and reliable enhancement mode: This invention uses a single metal material as the gate and combines the synergistic design of P+ type GaN enhancement gate (P-GaN cap layer) and P+ type current blocking layer (heavily doped blocking layer). By utilizing the positive charge of the majority carriers, the conduction band of the GaN / AlGaN heterojunction is raised above the Fermi level, so that the two-dimensional electron gas (2DEG) channel formed by the i-GaN channel layer and the i-AlGaN barrier layer can only be recovered when the gate-source voltage is greater than zero. Thus, the enhancement mode device characteristics are successfully realized, and the problem of unstable threshold voltage of traditional enhancement mode HEMT is effectively solved.
[0032] (2) Improved breakdown voltage capability: Three P-GaN pillars with decreasing lateral length and doping concentration are arranged at intervals from top to bottom on both sides of the drift region. Together with the N-type drift region, they form a stepped discrete superjunction structure. This three-segment design allows the doping concentration and lateral length of the superjunction to gradually change with position, achieving more precise charge matching and electric field control. Combined with the further modulation effect of the buried layer on the electric field, the uniformity of the electric field distribution inside the device is effectively improved. Simulation optimization results show that the breakdown voltage of this device is significantly improved compared with traditional HEMT devices; compared with ordinary stepless superjunction GaN HEMT, the breakdown voltage of this device is improved by about 63%.
[0033] (3) Effectively reduce conduction loss and enhance current driving capability: Thanks to the optimization effect of the vertical electric field of the stepped superjunction formed by the three P-GaN pillars with decreasing lateral length and doping concentration in the drift region, the synergistic effect of the buried layer stacked on the lightly doped barrier layer on electric field modulation, and the structural advantages of the heavily doped barrier layer, the device channel of the present invention has efficient tunneling conditions, which effectively reduces the on-resistance while improving the withstand voltage capability; the saturation current is about 13% higher than that of ordinary stepless superjunction GaN HEMT, achieving a good balance between high withstand voltage and low conduction loss.
[0034] (4) Enhanced gate control and superior overall performance: The two-dimensional electron gas channel formed by the i-GaN channel layer and the i-AlGaN barrier layer in this invention has sources on both sides. Each source is isolated from the stacked P-GaN cap layer and the gate by a SiN passivation layer. This structure effectively reduces gate leakage current and enhances the gate's control over the channel. Combined with the synergistic effect of the above structures, the device exhibits a better Ron-BV tradeoff, resulting in a significantly improved overall power quality factor. Compared with traditional HEMT devices and ordinary stepless superjunction GaN-based HEMT devices, it has lower on-resistance, higher saturation drive current, and significantly improved breakdown voltage. This invention provides an important reference for designing high-performance, high-voltage, high-frequency, and low-loss GaN power devices, and is suitable for high-end power electronics applications such as electric vehicles, photovoltaic inverters, and 5G base stations. Attached Figure Description
[0035] Figure 1 This is a structural diagram of a traditional P⁺-GaN CBL enhancement-mode vertical GaN / AlGaN HEMT device;
[0036] Figure 2 This is a structural diagram of the stepped superjunction enhanced HEMT device with a buried layer according to the present invention;
[0037] Figure 3 This is a comparison of the transfer characteristic curves of the stepped superjunction enhanced HEMT device with buried layer of the present invention and a conventional device.
[0038] Figure 4 This is a comparison of the output characteristic curves of the stepped superjunction enhanced HEMT device with buried layer of the present invention and a conventional device.
[0039] Figure 5 This is a comparison of the breakdown characteristic curves of the stepped superjunction enhanced HEMT device with buried layer of the present invention and a conventional device.
[0040] In the figure, 1 is the drain; 2 is the buffer layer; 3 is P-pillar 1; 4 is P-pillar 2; 5 is P-pillar 3; 6 is the heavily doped barrier layer; 7 is the source; 8 is the SiN passivation layer; 9 is the gate; 10 is the P-GaN cap layer; 11 is the i-AlGaN barrier layer; 12 is the i-GaN channel layer; 13 is the buried layer; 14 is the lightly doped barrier layer; and 15 is the drift region. Detailed Implementation
[0041] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0042] like Figure 2As shown, a stepped superjunction enhancement-mode HEMT device with a buried layer 13 includes, from bottom to top, a drain 1, a buffer layer 2, a drift region 15, a lightly doped barrier layer 14, a buried layer 13, an i-GaN channel layer 12, an i-AlGaN barrier layer 11, a P-GaN cap layer 10, and a gate 9; wherein,
[0043] Within the drift region 15, three P-GaN pillars with decreasing lateral length and doping concentration are arranged on the left and right sides from top to bottom, namely P pillar one, P pillar two and P pillar three from top to bottom.
[0044] A lightly doped barrier layer 14 and a buried layer 13 are stacked together, and heavyly doped barrier layers 6 are set on both sides of them.
[0045] The i-GaN channel layer 12 and the i-AIGaN barrier layer 11 together form a two-dimensional electron gas channel, and the source electrode 7 is set on the left and right sides of the two-dimensional electron gas channel.
[0046] Each source 7 is separated from the stacked P-GaN cap layer 10 and gate 9 by a SiN passivation layer 8.
[0047] In this embodiment:
[0048] A Schottky contact is used between the P-GaN cap layer 10 and the gate 9;
[0049] The i-GaN channel layer uses undoped intrinsic gallium nitride, which is 4 μm long and 60 nm thick. The i-AIGaN barrier layer 11 uses undoped intrinsic aluminum gallium nitride, which is 4 μm long and 15-30 nm thick. The polarization effect of the two forms a two-dimensional electron gas channel.
[0050] The GaN cap layer has a doping concentration of 3 × 10⁻⁶. 17 cm -3 ;
[0051] Drift region 15 is lightly doped n-type with a doping concentration of 1×10⁻⁶. 16 cm -3 The heavily doped barrier layer 6 is p-doped with a doping concentration of 1×10⁶. 17 cm -3 ~3×10 18 cm -3 Between these, current is forced to flow vertically from the drift region 15 of the device;
[0052] The lightly doped barrier layer 14 is lightly doped with P, and its doping concentration is 1×10⁻⁶. 15 cm -3 ;
[0053] Buried layer 13 is lightly doped with N, and its doping concentration is 5 × 10⁻⁶. 15 cm -3 ;
[0054] The doping concentration of the three P-GaN pillars on each side decreases from 4 × 10⁻⁶ to 4 × 10⁻⁶ from top to bottom. 16 cm -3 Decrease sequentially to 1×10 16 cm -3 Buffer layer 2 is N-doped with a concentration of 1×10⁻⁶. 19 cm -3 ;
[0055] The molar percentage of Al in the i-AIGaN barrier layer is 0.15-0.3.
[0056] There is a horizontal spacing of 0.5-1nm between the source 7 and the gate 9, which is the horizontal distance of the SiN passivation layer 8.
[0057] It should be noted that the above parameters are just examples and can be set to others as needed.
[0058] The fabrication method of the stepped superjunction enhanced HEMT device with buried layer 13 involved in the above embodiments specifically includes:
[0059] S1, Buffer Layer 2 and Drain 1 Fabrication: Take a flat substrate and deposit N-doped material (1×10⁻⁶) under the substrate using MOCVD process. 19 cm -3 After annealing, a buffer layer 2 is obtained, and a drain electrode 1 is deposited under the buffer layer 2 to form a substrate;
[0060] S2, Drift Region 15 and Superjunction Formation: The substrate was removed, and n-type lightly doped (1×10⁻⁶) cells were grown on the exposed buffer layer 2 using MOCVD. 16 cm -3 In the drift region 15, ICP etching of stepped grooves and growth of three-segment P-GaN pillars in a stepped pattern are performed, while simultaneously depositing lightly doped P (1×10⁻⁶). 15 cm -3 The lightly doped barrier layer 14 and the lightly doped N (5×10) 15 cm -3 The buried layer 13, the lightly mixed barrier layer 14, and the space between the left and right sides of the buried layer 13 and the corresponding sides of the drift zone 15 are left.
[0061] S3, Heavy barrier layer and channel fabrication: P-heavy doping (1×10⁻⁶) is deposited on both sides of drift region 15. 17 ~3×10 18 cm -3 A heavily doped barrier layer 6 is formed; a GaN channel layer and an i-AlGaN barrier layer 11 are sequentially grown on the buried layer 13 to form a two-dimensional electron gas channel.
[0062] S4, Cap and Gate 9 fabrication: P-GaN cap 10 and single metal gate 9 (with Schottky contact of P-GaN cap 10) are sequentially deposited on i-AIGaN barrier layer 11.
[0063] S5, Metal deposition: Source electrode 7 (0.5~1nm spacing with gate 9) is deposited on both sides of the channel, followed by annealing;
[0064] S6, Passivation layer formation: A 30nm thick SiN passivation layer 8 is deposited between each source 7 and the stacked P-GaN cap layer 10 and gate 9.
[0065] In this embodiment of the stepped superjunction enhancement-mode HEMT device with a buried layer, a stepped three-segment P-GaN pillar and a buried doped layer are introduced within the drift region 15, creating a gradient-changing bulk electric field modulation condition within the drift region 15. To ensure controllable breakdown characteristics and achieve enhancement-mode operation, a heavily doped barrier layer 6 is set below the channel to form a bulk barrier region, and the channel potential is controlled by the upper P-type gate 9, forming a gate-controlled barrier modulation structure. In the off state, no forward voltage is applied to the gate 9, the two-dimensional electron gas of the heterojunction is depleted, the barrier height of the heavily doped barrier layer 6 is high, and the charge carriers have difficulty crossing the barrier to form a conduction current, thus significantly suppressing the device leakage current. In the on state, a forward voltage is applied to the gate 9 to raise the channel potential and lower the bulk barrier height. Electrons obtain sufficient migration energy within the drift region 15 to successfully cross the barrier, and with the electric field soothing effect of the buried layer 13, large-area conduction is achieved, thereby completing the device's turn-on operation.
[0066] The advantages of this embodiment will be introduced below based on comparative experimental data.
[0067] It should be noted that the HEMT device in this embodiment (i.e. Figure 2 (as shown) and traditional HEMT devices (i.e. Figure 1 The difference (as shown) is that a stepped P-GaN pillar is added, along with a lightly doped barrier layer 14 and a buried layer 13.
[0068] Figure 3 This is a structural diagram of the HEMT device in this embodiment (i.e.) Figure 2 (as shown) and traditional HEMT devices (such as Figure 1 A comparison graph of the transfer characteristic curves (shown). From Figure 3As can be seen, the stepped superjunction enhancement-mode HEMT device with buried layer 13 in this embodiment exhibits good enhancement-mode characteristics compared to conventional devices. The drain current is close to zero when Vgs=0V, and the threshold voltage is in the range of 1.3V~1.6V, demonstrating high resistance to false turn-on. The threshold voltage of this embodiment is slightly higher, and the subthreshold curve is steeper, indicating that the gate 9 has stronger control over the channel. In the linear rise region, the rise rate of this embodiment is similar to that of the conventional device. However, in the high gate voltage saturation region, the saturated drain current of this embodiment is significantly higher, reaching approximately 21.8mA, which is about 2.5mA higher than the conventional structure, representing a 12.9% improvement. This fully verifies the effectiveness of the buried layer 13 and the stepped superjunction structure in enhancing channel control and current drive capability, without negatively impacting the turn-on characteristics.
[0069] Figure 4 This is a structural diagram of the HEMT device in this embodiment (i.e.) Figure 2 (as shown) and traditional HEMT devices (i.e. Figure 1 The output characteristic curve comparison chart (shown) shows that... Figure 4 As can be seen, the stepped superjunction enhanced HEMT device with buried layer 13 in this embodiment almost overlaps with the conventional device in the linear region, indicating that the present invention does not sacrifice conduction performance in pursuit of high withstand voltage. The current in the saturation region of this embodiment is higher, about 2.5 mA higher than the conventional structure, which is an improvement of 12.9%, indicating stronger channel control capability.
[0070] Figure 5 This is a structural diagram of the HEMT device in this embodiment (i.e.) Figure 2 (as shown) and traditional HEMT devices (such as Figure 1 The breakdown curve comparison chart (shown) shows that... Figure 5 As can be seen, the stepped superjunction enhanced HEMT device with buried layer 13 in this embodiment maintains an extremely low leakage current before breakdown, just like the conventional device. The main difference lies in the withstand voltage capability. The breakdown voltage of the conventional structure is 1750V, while the breakdown voltage of this invention is 2850V, which is 63% higher.
[0071] In summary, this embodiment constructs a stepped superjunction enhancement-mode HEMT device with a buried layer. A single-material metal is used as the gate (9), combining a P+ type GaN enhancement gate with a P+ type current blocking layer. Utilizing the positive charge of the majority carriers, the conduction band of the GaN / AlGaN heterojunction is raised above the Fermi level. The two-dimensional electron gas (2DEG) channel of the heterojunction can only be restored when the gate-source voltage is greater than 0, successfully achieving enhancement-mode device characteristics. The p / n / p type discrete superjunction enhancement-mode superjunction structure, formed by three segments of P-type GaN stair-step alternating P-type semiconductor pillars and N-type GaN drift regions, combined with the electric field modulation effect of the buried layer (13), effectively improves the uniformity of the internal electric field distribution, enabling the device channel to have efficient tunneling conditions and enhancing the overall device performance. Compared to traditional HEMT superjunction devices, this GaN-based enhanced vertical buried layer HEMT with segmented superjunction has higher breakdown voltage, lower on-resistance, and stronger current drive capability, resulting in higher efficiency, better power density, and better operational stability in the field of high-voltage power conversion.
[0072] The stepped superjunction enhancement-mode HEMT device with a buried layer in this embodiment has lower on-resistance, higher saturation drive current, and significantly improved breakdown voltage. At the same time, thanks to the optimization effect of the stepped superjunction on the vertical electric field, the synergistic effect of the thick GaN buried layer on electric field modulation, and the structural advantages of P-type GaN, the device has stronger gate control capability and a better Ron-BV trade-off, which greatly improves the breakdown voltage and current drive capability of the device, and achieves a good balance between high breakdown voltage and low conduction loss.
[0073] Simulation optimization results show that, compared with traditional HEMTs, this device has a significantly improved breakdown voltage, which is increased by about 63%, and a saturation current, which is increased by about 13%, while maintaining a low on-resistance. The overall power quality factor is significantly improved, which can provide an important reference for designing high-performance, high-voltage, high-frequency, and low-loss GaN power devices, and is suitable for high-end power electronic applications such as electric vehicles, photovoltaic inverters, and 5G base stations.
[0074] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A stepped superjunction enhanced HEMT device with a buried layer (13), characterized in that, The structure comprises, from bottom to top, a drain (1), a buffer layer (2), a drift region (15), a lightly doped barrier layer (14), a buried layer (13), an i-GaN channel layer (12), an i-AlGaN barrier layer (11), a P-GaN cap layer (10), and a gate (9); wherein, Three P-GaN pillars with decreasing lateral length and doping concentration are arranged on the left and right sides of the drift region (15) from top to bottom; Heavy-doped barrier layers (6) are provided on the left and right sides of the stacked light-doped barrier layer (14) and the buried layer (13). The i-GaN channel layer (12) and the i-AIGaN barrier layer (11) together form a two-dimensional electron gas channel, and the source electrode (7) is set on the left and right sides of the two-dimensional electron gas channel. Each source (7) is separated from the stacked P-GaN cap layer (10) and gate (9) by a SiN passivation layer (8).
2. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, A Schottky contact is used between the P-GaN cap layer (10) and the gate (9).
3. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The doping concentration of the P-GaN cap layer (10) is 3×10⁻⁶. 17 cm -3 .
4. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The drift region (15) is lightly doped n-type with a doping concentration of 1×10⁻⁶. 16 cm -3 .
5. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The heavily doped barrier layer (6) is p-doped with a doping concentration of 1×10⁻⁶. 17 cm -3 ~3×10 18 cm -3 between.
6. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The lightly doped barrier layer (14) is lightly doped with P and has a doping concentration of 1×10⁻⁶. 15 cm -3 .
7. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The buried layer (13) is lightly doped with N, and its doping concentration is 5 × 10⁻⁶. 15 cm -3 .
8. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The doping concentration of the three P-GaN pillars on each side decreases from 4 × 10⁻⁶ to 4 × 10⁻⁶ from top to bottom. 16 cm -3 Decrease sequentially to 1×10 16 cm -3 .
9. The stepped superjunction enhanced HEMT device with a buried layer (13) according to claim 1, characterized in that, The buffer layer (2) is N-fold doped with a concentration of 1×10⁻⁶. 19 cm -3 .
10. A method for fabricating a stepped superjunction enhanced HEMT device with a buried layer (13) as described in any one of claims 1-9, characterized in that, include: S1, Buffer layer (2) and drain (1) preparation: Take a flat substrate, deposit an N-fold doped layer under the substrate using MOCVD process and anneal it to obtain a buffer layer (2), and deposit a drain (1) under the buffer layer (2). S2, Drift Region (15) and Superjunction Formation: Remove the substrate, grow the drift region (15) on the exposed buffer layer (2) using MOCVD, etch a stepped groove with ICP and grow a stepped three-segment P-GaN pillar, and simultaneously deposit a lightly doped barrier layer (14) and a buried layer (13). There is space between the left and right sides of the lightly doped barrier layer (14) and the buried layer (13) and the corresponding side of the drift region (15). S3, preparation of heavy barrier layer and channel: deposit heavy barrier layer (6) on the left and right sides of drift region (15); grow GaN channel layer and i-AIGaN barrier layer (11) on buried layer (13) in sequence to form two-dimensional electron gas channel; S4, Cap and Gate (9) fabrication: P-GaN cap (10) and single metal gate (9) are sequentially deposited on i-AIGaN barrier layer (11). S5, Metal deposition: Source electrodes (7) are deposited on both sides of the channel, followed by annealing; S6, passivation layer formation: SiN passivation layer (8) is deposited between each source (7) and the stacked P-GaN cap layer (10) and gate (9).