A GaN HEMT device with a stepped gate structure and a method of manufacturing the same

Abstract

The application discloses a GaN HEMT device with a stepped gate structure and a preparation method thereof. The device comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer which are stacked in sequence; a gate structure arranged on the barrier layer, comprising a first sub-gate and a second sub-gate arranged at intervals, and a groove region between the first sub-gate and the second sub-gate; the first sub-gate and the second sub-gate each comprise a P-type gallium nitride layer arranged on the barrier layer; the thickness of the barrier layer below the groove region is less than the thickness of the barrier layer below the first sub-gate and the second sub-gate; and a gallium oxynitride film conformally covers the surfaces of the first sub-gate, the second sub-gate and the groove region, and a continuous transition interface is formed between the gallium oxynitride film and the P-type gallium nitride layer. The application is beneficial to optimizing the electric field distribution in the gate region, improving the voltage resistance of the device, and enhancing the stability and dynamic performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, specifically to a GaN HEMT device with a stepped gate structure and its fabrication method. Background Technology

[0002] With the increasing demands for efficiency and power density in power electronic systems, high electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunctions have attracted significant attention due to their high-frequency and low-loss characteristics. P-GaN gate structures are widely used to achieve enhancement-mode (E-mode) operation. However, existing P-GaN HEMT devices still face several challenges: on the one hand, traditional P-GaN gate devices generally have low threshold voltages and are prone to drift, affecting system safety and drive circuit design; on the other hand, while MIS P-GaN structures used to improve threshold voltage can introduce a dielectric layer, this leads to weakened gate control capability, increased subthreshold swing, and deteriorated dynamic performance, while simply increasing the P-GaN layer thickness easily causes lattice mismatch and reliability issues. Furthermore, conventional gate structures exhibit severe electric field concentration at the drain-side corner, limiting the device's breakdown voltage and high-voltage application capability. Therefore, there is an urgent need for a GaN HEMT device structure that can simultaneously achieve high threshold voltage, high stability, and high breakdown voltage without sacrificing gate control capability and epitaxial quality. Summary of the Invention

[0003] The purpose of this invention is to provide a GaN HEMT device with a stepped gate structure and its fabrication method. This invention helps to optimize the electric field distribution in the gate region, improve the device's breakdown voltage, and enhance its stability and dynamic performance.

[0004] The technical solution of the present invention: A GaN HEMT device with a stepped gate structure, comprising: A substrate, and a nucleation layer, a buffer layer, a channel layer and a barrier layer sequentially stacked on the substrate; A gate structure is disposed on the barrier layer. The gate structure includes a first sub-gate and a second sub-gate disposed at intervals, and a groove region located between the first sub-gate and the second sub-gate. The first sub-gate and the second sub-gate both include a P-type gallium nitride layer disposed on the barrier layer. The thickness of the barrier layer below the groove region is less than the thickness of the barrier layer (5) below the first sub-gate and the second sub-gate. A gallium oxynitride thin film conformally covers the surfaces of the first sub-gate, the second sub-gate, and the surface of the groove region, and the gallium oxynitride thin film has a continuous transition interface with the p-type gallium nitride layer.

[0005] In the aforementioned GaN HEMT device with a stepped gate structure, the gallium oxynitride thin film is formed by in-situ oxidation through annealing in an oxygen-containing atmosphere.

[0006] In the aforementioned GaN HEMT device with a stepped gate structure, the thickness of the barrier layer below the groove region is 1~10nm; The thickness of the P-type gallium nitride layer (6) is 50~100nm.

[0007] In the aforementioned GaN HEMT device with a stepped gate structure, the gallium oxynitride thin film covers the top surface and sidewalls of the first sub-gate and the second sub-gate, as well as the bottom surface of the recessed region; The gallium oxynitride thin film also covers the surface of the barrier layer exposed in the groove region.

[0008] In the aforementioned GaN HEMT device with a stepped gate structure, the thickness of the gallium oxynitride thin film (9) is 1~20nm.

[0009] The aforementioned GaN HEMT device with a stepped gate structure further includes: The source metal and drain metal are respectively disposed above the barrier layer and located on both sides of the gate structure; A gate metal is disposed on the side surface of the gallium oxynitride thin film opposite to the barrier layer.

[0010] In the aforementioned GaN HEMT device with a stepped gate structure, the source metal and the drain metal are made of at least one of titanium, aluminum, nickel, gold, titanium nitride, or platinum. The material of the gate metal includes at least one of nickel, gold, or titanium nitride. The barrier layer is made of aluminum gallium nitride, wherein the aluminum content is 0.18 to 0.24%.

[0011] A method for fabricating a GaN HEMT device with a stepped gate structure, comprising: A nucleation layer, a buffer layer, a channel layer, a barrier layer, and a p-type gallium nitride layer are sequentially formed on the substrate. The p-type gallium nitride layer and the barrier layer are etched to form a stepped gate structure including a first sub-gate, a second sub-gate, and a recessed region between them, wherein the thickness of the barrier layer below the recessed region is less than the thickness of the barrier layer below the first sub-gate and the second sub-gate. Source metal and drain metal are formed on the barrier layer, and ohmic contact annealing is performed under a protective atmosphere; Annealing is performed in an oxygen-containing atmosphere to oxidize the surfaces of the P-type gallium nitride layer and the exposed barrier layer in situ, forming a conformally conformal gallium nitride thin film covering the stepped gate structure. A gate metal is formed on the gallium oxynitride thin film.

[0012] The fabrication method of the above-mentioned GaN HEMT device with a stepped gate structure, wherein the formation of the gate structure includes: The P-type gallium nitride layer outside the gate region is etched to form a first sub-gate and a second sub-gate spaced apart. Etching a portion of the P-type gallium nitride layer and a portion of the barrier layer between the first sub-gate and the second sub-gate forms the groove region; The formation of the gallium oxynitride thin film includes: Annealing is performed in a nitrogen-oxygen-containing active atmosphere to transform the surfaces of the first sub-gate and the second sub-gate, as well as the bottom surface and sidewalls of the groove region, into the gallium oxynitride thin film in situ.

[0013] The aforementioned method for fabricating a GaN HEMT device with a stepped gate structure includes the following annealing conditions in a nitrogen-oxygen-containing reactive atmosphere: The annealing temperature is 200~500℃; Annealing time is 1~30min.

[0014] Compared with existing technologies, this invention achieves a unified set of multiple technical effects through the synergistic combination of a stepped gate structure and an in-situ oxidized gallium oxynitride (GaN) film. Specifically, the barrier layer thickness below the groove region is reduced, and combined with the P-type GaN layers retained on both sides, a stepped morphology with a low center and high sides is formed. This structure can effectively modulate the electric field distribution below the gate and shield the electric field concentration effect of the drain bias on the gate edge, thereby significantly improving the breakdown voltage of the device and preventing premature breakdown. At the same time, the GaN film formed by in-situ oxidation on the surface of the stepped structure through oxygen-containing atmosphere annealing not only conformally covers the top surface, sidewalls, and bottom surface of the P-type GaN layer, effectively passivating etching damage and reducing interface state density, but also has a higher Schottky barrier height compared to the MIS structure of traditional deposited dielectric layers. While ensuring excellent gate control capability and low subthreshold swing, it significantly improves the threshold voltage of the device and suppresses gate leakage current. Furthermore, the combination of the right-side P-type gallium nitride gate and the recessed gate further shields the drain bias voltage from affecting the left-side gate, enhancing the long-term stability of the threshold voltage. The entire fabrication process eliminates the need for complex external dielectric layer deposition steps, avoiding lattice mismatch issues caused by increasing the P-GaN thickness. This simplifies the process flow while enabling the device to possess high threshold voltage, high breakdown voltage, low on-resistance, and excellent dynamic switching performance. Attached Figure Description

[0015] Figure 1 This is a schematic cross-sectional view of the extended foundation layered structure according to an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of the double-strip P-GaN cap structure according to an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the stepped gate structure after etching according to an embodiment of the present invention; Figure 4 This is a schematic cross-sectional view of the source / drain metal structure after its formation, according to an embodiment of the present invention. Figure 5 This is a schematic cross-sectional view of the structure after the in-situ oxidation of GaON thin film is formed according to an embodiment of the present invention; Figure 6 This is a schematic cross-sectional view of the complete GaN HEMT device structure according to an embodiment of the present invention.

[0016] Among them, 1-substrate, 2-nucleation layer, 3-buffer layer, 4-channel layer, 5-barrier layer, 6-P-type gallium nitride layer, 7-source metal, 8-drain metal, 9-gallium oxynitride thin film, 10-gate metal. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this should not be construed as limiting the present invention.

[0018] Example 1: This example provides a GaN HEMT device with a stepped gate structure, such as... Figure 6 As shown, the device includes a substrate 1, and a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5 sequentially stacked on the substrate 1. In this embodiment, the substrate 1 can be a semiconductor material such as silicon, silicon carbide, sapphire, gallium nitride, QST, SOI, or diamond. The nucleation layer 2, buffer layer 3, channel layer 4, and barrier layer 5 together constitute the epitaxial functional layers of the device. A high-concentration two-dimensional electron gas conductive channel is formed between the channel layer 4 and the barrier layer 5 due to spontaneous polarization and piezoelectric polarization effects. The channel layer 4 is made of GaN, and the heterojunction interface formed by it and the AlGaN barrier layer 5 has sufficient conduction band discontinuity, which is beneficial for enhancing the quantum confinement effect of the two-dimensional electron gas, thereby obtaining higher carrier surface density and mobility. It should be understood that although a specific stacking order is shown in the figure, in other embodiments, the material system and doping type of each epitaxial layer can be adjusted according to the actual device requirements, as long as a heterojunction conductive channel can be formed. For example, the material of buffer layer 3 can be iron- or carbon-doped gallium nitride, AlN / GaN alternating superlattice, or AlxGa1-xN with aluminum composition gradient, so as to effectively alleviate the lattice mismatch and thermal expansion coefficient difference between substrate 1 and subsequent epitaxial layers.

[0019] The device also includes a gate structure disposed on a barrier layer 5, the gate structure comprising a first sub-gate and a second sub-gate spaced apart, and a recessed region located between the first sub-gate and the second sub-gate; both the first and second sub-gates contain a P-type gallium nitride layer 6 disposed on the barrier layer 5, the thickness of the barrier layer 5 below the recessed region being less than the thickness of the barrier layer 5 below the first and second sub-gates; specifically, this stepped topography, low in the middle and high on both sides, is an active modulation of the electric field distribution below the gate. The thinning of the barrier layer 5 below the recessed region allows the gate metal in this region to be closer to the channel, enhancing the local gate control capability. Simultaneously, due to the presence of the recess, the high electric field on the drain side is effectively dispersed and shielded, avoiding excessive concentration of the electric field at the gate edge, thereby significantly improving the device's breakdown voltage. The P-type gallium nitride layers 6 retained on both sides ensure that the device can effectively deplete channel carriers at zero gate voltage, achieving normally-off characteristics. This structural design achieves synergistic optimization of breakdown voltage capability and threshold voltage stability without sacrificing on-resistance.

[0020] Furthermore, the device also includes a gallium oxynitride (GaN) film 9, conformally covering the surfaces of the first sub-gate, the second sub-gate, and the surface of the groove region, with a continuous transition interface between the GaN film 9 and the P-type GaN layer 6. The GaN film 9 is formed through in-situ oxidation via oxygen-containing atmosphere annealing. Specifically, "in-situ oxidation formation" refers to using a thermal annealing process in an oxygen-containing atmosphere to allow the lattice atoms on the surfaces of the P-type GaN layer 6 and the exposed barrier layer 5 to react directly with oxygen, transforming them in-situ into GaN material, rather than depositing an external dielectric layer on the surface through processes such as ALD or CVD. This in-situ transformation mechanism creates an atomically matched transition interface between the GaN film 9 and the underlying semiconductor, effectively eliminating interface dangling bonds and defect states common in traditional deposition processes, and providing excellent passivation and repair for surface damage caused by etching. Meanwhile, the conformal coverage ensures that the thin film not only covers the top surface, but also closely fits the sidewalls and bottom surface of the groove area, thus isolating the gate metal from the semiconductor in all directions. While increasing the Schottky barrier height and reducing gate leakage, it maintains excellent gate control capability and subthreshold swing, overcoming the gate control weakening problem caused by the introduction of dielectric layer in traditional MIS structures.

[0021] As a preferred option, combined with Figure 2 and Figure 4As shown, the stepped morphology formed by the first sub-gate, the second sub-gate, and the groove physically manifests as two independent strip-shaped P-type gallium nitride layer 6 structures. A recessed groove region is formed between them after some material is removed through etching. The first sub-gate, located on the source side, primarily handles the main control function of channel turn-on and turn-off, while the second sub-gate, located on the drain side, acts as an electric field shield, effectively preventing the electric field from penetrating the main control gate region from the high drain potential, thus significantly improving the stability of the threshold voltage under high-voltage conditions. The device also includes source metal 7 and drain metal 8, located on opposite sides of the gate structure and positioned above the barrier layer 5. This electrode topology ensures precise spatial alignment between the lateral transport path of charge carriers within the channel and the electric field modulation region of the stepped gate, maximizing the electrical benefits of the structural design.

[0022] In a preferred embodiment, the thickness of the barrier layer 5 below the groove region is 1~10 nm. If the residual thickness of the barrier layer 5 below the groove is too large (e.g., more than 10 nm), the gate metal will be far from the two-dimensional electron gas channel, weakening the gate control capability and potentially leading to a low threshold voltage or even failure to achieve enhancement-mode operation. Conversely, if the residual thickness is too small (e.g., less than 1 nm), although the threshold voltage can be increased, it is very easy to induce gate tunneling leakage, and during subsequent in-situ oxidation, lattice damage can easily cause a surge in interface state density, damaging the dynamic resistance and long-term reliability of the device. Therefore, controlling the thickness of the barrier layer in the groove region within the range of 1~10 nm can maintain excellent gate dielectric integrity while ensuring sufficient Schottky barrier height.

[0023] Furthermore, the thickness of the p-type gallium nitride layer 6 is 50-100 nm. On the one hand, the p-type gallium nitride layer 6 must have sufficient thickness to provide an adequate total amount of acceptor impurities, thereby completely depleting the two-dimensional electron gas in the channel at zero gate voltage and ensuring that the device is in a reliable normally-off state. On the other hand, an excessively thick p-type gallium nitride layer will not only exacerbate the lattice mismatch stress with the underlying AlGaN material and induce crystal defects such as dislocations, but also increase the gate capacitance, which is detrimental to high-frequency switching applications. Within the preferred range of 50-100 nm in this invention, the p-type gallium nitride layer 6 can provide a stable threshold voltage (typically greater than 1.5V) while maintaining good epitaxial quality and low parasitic capacitance. For example, in a specific preferred example, the thickness of the p-type gallium nitride layer 6 is set to 70 nm, and the residual thickness of the barrier layer 5 below the trench is set to 5 nm. At this time, the device exhibits a threshold voltage of approximately 2.0V and extremely low gate leakage current. It should be noted that the above numerical range is only a preferred embodiment based on the current material system and process conditions. Those skilled in the art can make adaptive adjustments to the above dimensions according to the actual doping concentration or application scenario requirements.

[0024] Preferably, the gallium oxynitride thin film 9 covers the top surface and sidewalls of the first and second sub-gates, as well as the bottom surface of the recessed region. Figure 5 As shown, this coverage is a conformal growth along the complex three-dimensional contour of the stepped gate structure. Since the gallium oxynitride thin film 9 is formed by in-situ oxidation through annealing in an oxygen-containing atmosphere, its growth process is limited by the diffusion depth of oxygen atoms into the nitride lattice. Therefore, it can precisely conform to the top contour of the p-type gallium nitride layer 6 and extend downwards to closely fit its vertical or inclined sidewalls, while forming a continuous transition layer at the bottom of the groove region. During the etching process to form the stepped gate structure, the sidewalls of the p-type gallium nitride layer 6 are inevitably bombarded by plasma, resulting in lattice damage and a large number of dangling bonds. If these defect states are not effectively passivated, they will become the main channels for gate leakage current and cause unstable drift of the threshold voltage. This invention directly transforms the sidewall surface material into high-quality gallium oxynitride through in-situ oxidation, repairing etching damage and eliminating interface state traps, thereby significantly reducing gate leakage current and improving the dynamic reliability of the device. Furthermore, the gallium oxynitride thin film 9 also covers the surface of the barrier layer 5 exposed in the groove region. This means that within the groove region, the gallium oxynitride thin film 9 lies directly on top of the thinned barrier layer 5, serving as the sole dielectric barrier between the gate metal and the channel. This full-coverage structure ensures that the gate metal will not directly contact the exposed semiconductor surface regardless of changes in the gate voltage, avoiding metal-induced bandgap states and Fermi level pinning effects, thus laying the structural foundation for obtaining a high and stable threshold voltage.

[0025] Based on the aforementioned three-dimensional conformal overlay structure, the thickness of the gallium oxynitride (GaN) film 9 is controlled within the range of 1–20 nm. If the GaN film 9 is too thin (e.g., less than 1 nm), it is difficult to form a dense and continuous insulating layer. This not only fails to adequately passivate defect states on the sidewalls and interfaces but also makes it highly susceptible to carrier tunneling under high electric fields, leading to a sharp increase in gate leakage current and even device breakdown failure. Conversely, if the GaN film 9 is too thick (e.g., exceeding 20 nm), although the insulation performance is guaranteed, the increase in the equivalent oxide thickness (EOT) significantly weakens the gate's ability to control the two-dimensional electron gas in the channel, resulting in decreased transconductance, increased subthreshold swing, and increased switching delay. Therefore, limiting the thickness to the 1–20 nm range ensures sufficient Schottky barrier height to suppress leakage current while maintaining excellent gate control sensitivity. In a preferred specific example, the thickness of the GaN film 9 is approximately 3–8 nm.

[0026] Example 2: Based on Example 1, this example further improves the electrical connection integrity of the device and specifically defines the electrode topology and material system. Specifically, the device also includes source metal 7 and drain metal 8, which are respectively disposed above the barrier layer 5 and located on both sides of the gate structure; gate metal 10 is disposed on the surface of the gallium oxynitride thin film 9 away from the barrier layer 5, and gate metal 10 also includes a field plate structure extending to the drain side. This stacked position relationship constructs the basic current transport and gate control loop of the device. Among them, source metal 7 and drain metal 8 are in direct contact with the upper surface of the barrier layer 5, aiming to form a low-resistance ohmic contact channel as a port for carriers to flow into and out of the two-dimensional electron gas channel. Specifically, the source metal 7 and drain metal 8 can adopt a multilayer composite structure of titanium / aluminum / nickel / gold (Ti / Al / Ni / Au), with each layer having a thickness of 30 / 80 / 50 / 50 nm, and undergo rapid thermal annealing at 800°C for 30 s to allow the titanium and aluminum layers to undergo a solid-state reaction with the surface of the barrier layer 5, forming an ohmic contact interface with extremely low specific contact resistivity. The gate metal 10 is isolated from the underlying semiconductor layer by a gallium oxynitride thin film 9, using the thin film formed by in-situ oxidation in the aforementioned embodiment as an interface modification layer to form a gate control structure with a high barrier height. It should be understood that although the figure shows a symmetrical arrangement of the source metal 7 and drain metal 8 on the left and right sides of the gate structure, in other embodiments, depending on the chip layout design or packaging requirements, the source and drain electrodes can also adopt an asymmetrical arrangement or a multi-finger interdigitated structure, as long as they are electrically located on opposite sides of the gate control region to define an effective channel length.

[0027] In a preferred embodiment, the source metal 7 and drain metal 8 are made of at least one of titanium, aluminum, nickel, gold, titanium nitride, or platinum. Specifically, the core of the source / drain electrode material system design lies in achieving a balance between extremely low specific contact resistivity and excellent high-temperature stability. For example, in a specific preferred example, the source metal 7 and drain metal 8 employ a multilayer composite structure of titanium / aluminum / nickel / gold, wherein the titanium and aluminum layers undergo a solid-state reaction with the nitride on the surface of the barrier layer 5 during high-temperature annealing, forming a low-barrier ohmic contact interface; while the outer nickel / gold or titanium nitride / platinum combination mainly acts as a diffusion barrier layer and an anti-oxidation protective layer, preventing the internal metal from oxidizing or agglomerating and failing during subsequent processes or long-term operation. Those skilled in the art should understand that the above material combinations are not exhaustive; any refractory metal or its alloy system capable of forming a stable, low-resistivity ohmic contact with the AlGaN / GaN heterojunction can be used as an alternative to this invention.

[0028] For the gate metal 10, the material includes at least one of nickel, gold, or titanium nitride. This selection is primarily based on considerations of controlling the height of the Schottky barrier. Since the present invention introduces an in-situ oxidized gallium oxynitride thin film 9 under the gate, the gate metal 10 no longer directly contacts the semiconductor surface, thus reducing the direct impact of its work function on the threshold voltage. However, a chemically stable and easily patternable metal material is still required. For example, the nickel / gold combination is widely used due to its mature evaporation and stripping process compatibility and good conductivity; while in some applications with more stringent high-temperature reliability requirements, titanium nitride is a better choice due to its excellent heat resistance and anti-electromigration ability. The selection of these materials is all aimed at ensuring the complete transmission of the gate signal while avoiding device degradation caused by the diffusion of metal atoms into the dielectric layer.

[0029] Furthermore, the barrier layer 5 is made of aluminum gallium nitride (AlGaN), with an aluminum content ranging from 0.18 to 0.24. The aluminum composition in the AlGaN barrier layer directly determines the polarization electric field strength at the heterojunction interface, thus affecting the density of the two-dimensional electron gas within the channel. If the aluminum composition is below 0.18, insufficient polarization-induced charge leads to a significant increase in the device's on-resistance, limiting its current handling capability in power applications. Conversely, if the aluminum composition is above 0.24, although the carrier concentration increases, the lattice mismatch stress between AlGaN and the underlying GaN channel layer increases sharply, easily inducing crystal defects such as dislocations and cracks. These defects not only become leakage channels reducing the breakdown voltage but also act as charge trap centers, causing dynamic on-resistance degradation and threshold voltage drift. Therefore, controlling the aluminum composition within the range of 0.18 to 0.24 ensures sufficiently low on-resistance while maintaining the high-quality crystal characteristics of the epitaxial layer, thereby supporting the overall high performance and high reliability of the device.

[0030] Example 3: As Figures 1 to 6 As shown, this embodiment provides a method for fabricating a GaN HEMT device with a stepped gate structure. This method integrates structure forming and interface modification through a specific process timing. Specifically, the fabrication method includes the following steps: In step S100, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, and a p-type gallium nitride layer 6 are sequentially formed on substrate 1. This step constructs the epitaxial functional stack of the device. For example, the above semiconductor layers can be grown layer by layer on substrate 1 such as silicon, silicon carbide, or sapphire using processes such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE). A two-dimensional electron gas conductive channel is formed between the channel layer 4 and the barrier layer 5 due to the polarization effect, while the top p-type gallium nitride layer 6 provides the necessary depletion region material basis for the subsequent formation of the enhancement gate structure. In this embodiment, the total thickness of the AlGaN barrier layer 5 is 15 nm, and the thickness of the p-type gallium nitride layer 6 is 70 nm, to provide sufficient material margin for subsequent step etching and in-situ oxidation processes. It should be understood that although this embodiment uses a specific layer stacking order as an example, in other embodiments, the material composition, doping type or growth process of each layer can be adjusted according to the device performance requirements, as long as a heterojunction epitaxial wafer with gate control capability can be formed.

[0031] In step S200, the P-type gallium nitride layer 6 and the barrier layer 5 are etched to form a stepped gate structure including a first sub-gate, a second sub-gate, and a recessed region between them. The thickness of the barrier layer 5 below the recessed region is less than the thickness of the barrier layer 5 below the first and second sub-gates. In this step, the gate window can first be defined by photolithography, and the P-type gallium nitride layer 6 outside the gate region can be removed by dry etching to form a spaced-apart sub-gate structure. Then, a second etching is performed on the region between the sub-gates, cutting down into the barrier layer 5 to a certain depth but not completely penetrating it, thus forming a stepped morphology that is low in the middle and high on both sides. This geometric structure allows the gate metal in the recessed region to be closer to the channel to enhance local gate control capability. Simultaneously, the P-type gallium nitride layer 6 and the thicker barrier layer 5 retained on both sides act as electric field shields, effectively dispersing the high electric field peak on the drain side and preventing premature device breakdown. The accuracy of the etching depth directly determines the magnitude and uniformity of the threshold voltage; therefore, the etching rate and endpoint detection must be strictly controlled.

[0032] In step S300, source metal 7 and drain metal 8 are formed on the barrier layer 5. A metal stack is deposited using electron beam evaporation or sputtering, combined with a lift-off or etching process to form the desired electrode pattern. The source metal 7 and drain metal 8 are in direct contact with the barrier layer 5 and undergo high-temperature annealing to form ohmic contacts, serving as ports for carriers to enter and exit the channel. After forming the source and drain metals, rapid thermal annealing is performed under a nitrogen or argon protective atmosphere at a temperature of 700-850°C for 20-60 seconds to form low-resistance ohmic contacts between the source and drain metals and the barrier layer. Subsequent oxygen-containing annealing is then performed. Since a stable ohmic contact interface has already been formed between the source and drain metals, and the oxygen-containing annealing temperature is relatively low (200-500°C), this low-temperature oxidation process does not significantly affect the characteristics of the formed ohmic contacts.

[0033] In step S400, annealing is performed in an oxygen-containing atmosphere to oxidize the surfaces of the P-type gallium nitride layer 6 and the exposed barrier layer 5 in situ, forming a conformal gallium oxynitride thin film 9 covering the stepped gate structure. The gallium oxynitride thin film 9 formed by the above-mentioned in-situ oxidation process forms an atomically matched transition interface with the underlying P-type gallium nitride layer 6 and barrier layer 5 through chemical bonding, effectively eliminating dangling bonds and defect states caused by lattice mismatch or interface contamination in traditional deposition processes. Specifically, this is the core innovative step of the preparation method of this invention. Its essence is to utilize thermal activation to induce a solid-state reaction between oxygen atoms and the freshly exposed semiconductor surface after etching, directly transforming the surface lattice into gallium oxynitride material, rather than depositing an external insulating medium on the surface. For example, the wafer after stepped etching is placed in a rapid thermal annealing furnace or tube furnace, oxygen or an oxygen-containing mixed gas is introduced, and it is held at a predetermined temperature for a period of time. During this process, oxygen atoms diffuse uniformly along the top surface, sidewalls, and the surface of the barrier layer 5 at the bottom of the groove of the p-type gallium nitride layer 6, undergoing in-situ transformation. This naturally conforms to the three-dimensional contour of the stepped structure, achieving perfect conformal coverage. This in-situ oxidation mechanism has significant self-alignment advantages, accurately covering all exposed surfaces without additional photolithography alignment. More importantly, since the oxide layer is transformed from the substrate material itself, it forms an atomically matched transition interface with the underlying semiconductor, effectively eliminating the interface dangling bonds and contamination problems common in traditional deposition processes. This provides in-situ repair and passivation for lattice damage caused by previous etching, thereby significantly reducing the interface state density and gate leakage current.

[0034] In step S500, gate metal 10 is formed on the gallium oxynitride thin film 9. Gate metal 10 is also fabricated on the in-situ generated gallium oxynitride thin film 9 using electron beam evaporation or sputtering. For example, gate metal 10 can be deposited by electron beam evaporation, using a nickel / gold (Ni / Au) multilayer structure with thicknesses of 50 / 100 nm, where the nickel layer provides stable Schottky contact characteristics and the gold layer serves as an anti-oxidation protective layer. This thin film is used as an interface modification layer to increase the Schottky barrier height, further suppressing gate leakage while maintaining excellent gate control sensitivity. Thus, through the close integration of the above five main steps, a stepped-gate GaN HEMT device with high threshold voltage, high breakdown voltage, and excellent interface characteristics is fabricated.

[0035] Preferably, the process of etching the P-type gallium nitride layer 6 and the barrier layer 5 to form a stepped gate structure including a first sub-gate, a second sub-gate, and a recessed region between them can employ a step-by-step etching strategy to achieve precise topology control. For example, firstly, the P-type gallium nitride layer 6 outside the gate region is etched to form the spaced first and second sub-gates; subsequently, a portion of the P-type gallium nitride layer 6 and a portion of the barrier layer 5 between the first and second sub-gates are etched to form the recessed region. The advantage of this step-by-step processing logic is that the first etching step defines the overall width and position of the sub-gate, providing a self-aligned mask reference for subsequent recess etching, effectively avoiding gate asymmetry problems caused by multiple photolithography alignment errors. Simultaneously, during the etching of the recessed region, the P-type gallium nitride layers 6 already formed on both sides act as natural protective walls, significantly improving the verticality and flatness of the recessed sidewalls and reducing the electric field concentration effect caused by sidewall tilting or excessive roughness. It should be understood that although this embodiment takes step-by-step etching as an example, in other embodiments, if an advanced etching equipment with extremely high selectivity and depth control is used, a single photolithography combined with a multi-step etching process can be used to simultaneously form the sub-gate and the groove structure. As long as the final geometric morphology meets the stepped features and the thickness of each region meets the design requirements, it falls within the protection scope of this invention.

[0036] After etching the stepped structure, the parameter control of the in-situ oxidation process is crucial to the quality of the gallium oxynitride thin film 9. Specifically, annealing is performed in a nitrogen-oxygen-containing active atmosphere (e.g., N2O, NO, NH3 / O2) to in-situ transform the surfaces of the first and second sub-gates, as well as the bottom and sidewalls of the groove region, into a gallium oxynitride thin film 9. This transformation process is not a simple vapor deposition but rather a thermally activated solid-phase reaction mechanism. As a preferred embodiment, the annealing process conditions in a nitrogen-oxygen-containing active atmosphere include: an annealing temperature of 200–500°C and an annealing time of 1–30 min. When the annealing temperature is below 200°C, the thermal kinetic energy of oxygen atoms is insufficient to overcome the surface barrier and diffuse effectively into the lattice, causing the oxidation reaction to remain only at the outermost layer. This fails to adequately repair the deep lattice damage caused by etching, leaving a large number of dangling bonds and defect states at the interface, resulting in a large gate leakage current and unstable threshold voltage. Conversely, when the annealing temperature exceeds 500℃, excessive heat may trigger lattice decomposition in GaN or AlGaN materials, or cause deactivation or even hydrogen passivation failure of the magnesium (Mg) acceptors in the p-type gallium nitride layer 6, severely weakening the depletion capability of the p-type layer. Simultaneously, high temperatures may also promote excessive diffusion of oxygen atoms towards the channel, altering the polarization charge distribution at the heterojunction interface and leading to a significant decrease in the mobility of the two-dimensional electron gas. Similarly, the annealing time must be strictly controlled. Too short a time results in insufficient oxide layer density and thickness, while too long a time may lead to excessively thick gallium oxynitride film 9, increasing the equivalent oxide thickness (EOT), weakening the gate's control over the channel, causing transconductance degradation and slower switching speeds.

[0037] In a specific preferred example, the thermal annealing process is set to hold at 300°C in a pure oxygen atmosphere for 5 minutes. Under this condition, oxygen atoms can gain sufficient energy to undergo appropriate coordination exchange with gallium atoms on the surface of the p-type gallium nitride layer 6 and the barrier layer 5, forming a gallium oxynitride thin film 9 with a thickness of approximately 3-5 nm, stable stoichiometry, and a steep interface. Test results show that the device prepared using this preferred process has a threshold voltage of over 2.0V, a gate leakage current of less than 10 nA / mm, and exhibits excellent long-term stability under high-temperature and high-pressure stress testing, verifying the effectiveness of the above process window in achieving high-performance devices. It should be noted that the above temperature and time ranges are preferred ranges for conventional rapid thermal annealing (RTA) or tube furnace annealing processes. In actual production, depending on the heating method, heating rate, oxygen partial pressure, and characteristics of the equipment cavity, those skilled in the art can make adaptive adjustments within the above ranges to obtain the optimal combination of interface modification and electrical performance.

[0038] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A GaN HEMT device with a stepped gate structure, characterized in that, include: A substrate (1), and a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (5) sequentially stacked on the substrate (1); A gate structure is disposed on the barrier layer (5). The gate structure includes a first sub-gate and a second sub-gate disposed at intervals, and a groove region located between the first sub-gate and the second sub-gate. The first sub-gate and the second sub-gate both include a P-type gallium nitride layer (6) disposed on the barrier layer (5). The thickness of the barrier layer (5) below the groove region is less than the thickness of the barrier layer (5) below the first sub-gate and the second sub-gate. And a gallium oxynitride thin film (9) conformally covers the surfaces of the first sub-gate, the second sub-gate, and the surface of the groove region, and the gallium oxynitride thin film (9) and the P-type gallium nitride layer (6) have a continuous transition interface.

2. The GaN HEMT device with a stepped gate structure according to claim 1, characterized in that, The gallium oxynitride thin film (9) is formed by in-situ oxidation through annealing in an oxygen-containing atmosphere.

3. The GaN HEMT device with a stepped gate structure according to claim 1, characterized in that, The thickness of the barrier layer (5) below the groove region is 1~10nm; The thickness of the P-type gallium nitride layer (6) is 50~100nm.

4. The GaN HEMT device with a stepped gate structure according to claim 1, characterized in that, The gallium oxynitride thin film (9) covers the top surface and sidewall of the first sub-gate and the second sub-gate, respectively, as well as the bottom surface of the groove region; The gallium oxynitride thin film (9) also covers the surface of the barrier layer (5) exposed in the groove region.

5. The GaN HEMT device with a stepped gate structure according to claim 4, characterized in that, The thickness of the gallium oxynitride thin film (9) is 1~20nm.

6. The GaN HEMT device with a stepped gate structure according to claim 1, characterized in that, Also includes: The source metal (7) and drain metal (8) are respectively disposed above the barrier layer (5) and located on both sides of the gate structure; A gate metal (10) is disposed on the side surface of the gallium oxynitride thin film (9) away from the barrier layer (5).

7. The GaN HEMT device with a stepped gate structure according to claim 6, characterized in that, The source metal (7) and the drain metal (8) are made of at least one of titanium, aluminum, nickel, gold, titanium nitride or platinum; The material of the gate metal (10) includes at least one of nickel, gold, or titanium nitride; The barrier layer (5) is made of aluminum gallium nitride, wherein the aluminum content is 0.18 to 0.24%.

8. A method for fabricating a GaN HEMT device with a stepped gate structure, characterized in that, include: A nucleation layer (2), a buffer layer (3), a channel layer (4), a barrier layer (5), and a p-type gallium nitride layer (6) are sequentially formed on a substrate (1); The P-type gallium nitride layer (6) and the barrier layer (5) are etched to form a stepped gate structure including a first sub-gate, a second sub-gate and a recessed region between them, wherein the thickness of the barrier layer (5) below the recessed region is less than the thickness of the barrier layer (5) below the first sub-gate and the second sub-gate. Source metal (7) and drain metal (8) are formed on the barrier layer (5) and ohmic contact annealing is performed under a protective atmosphere; Annealing is performed in an oxygen-containing atmosphere to oxidize the surfaces of the P-type gallium nitride layer (6) and the exposed barrier layer (5) in situ, forming a conformally conformal gallium nitride thin film (9) covering the stepped gate structure. A gate metal (10) is formed on the gallium oxynitride thin film (9).

9. The method for fabricating a GaN HEMT device with a stepped gate structure according to claim 8, characterized in that, The formation of the gate structure includes: The P-type gallium nitride layer (6) outside the gate region is etched to form a first sub-gate and a second sub-gate spaced apart; Etching a portion of the P-type gallium nitride layer (6) and a portion of the barrier layer (5) between the first sub-gate and the second sub-gate forms the groove region; The formation of the gallium oxynitride thin film (9) includes: Annealing is performed in a nitrogen-oxygen active atmosphere to convert the surfaces of the first sub-gate and the second sub-gate, as well as the bottom and sidewalls of the groove region, into the gallium oxynitride thin film in situ (9).

10. The method for fabricating a GaN HEMT device with a stepped gate structure according to claim 9, characterized in that, The process conditions for annealing in a nitrogen- and oxygen-containing active atmosphere include: The annealing temperature is 200~500℃; Annealing time is 1~30min.

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