An enhanced gallium nitride power device and a method of fabricating the same

Abstract

The application provides an enhanced gallium nitride power device and a preparation method thereof, and relates to the technical field of semiconductors. The device is provided with a first two-dimensional electron gas channel, a second two-dimensional electron gas channel and two-dimensional hole gas through a secondary epitaxial structure and a four-terminal structure, so that a multi-channel parallel current-carrying structure is obtained. The selective etching of the surface barrier layer in the gate region realizes the normally-off control of the second two-dimensional electron gas channel; meanwhile, the independent top control electrode is arranged on the surface of the hole induction layer to individually regulate the two-dimensional hole gas. Through the cooperative control of the main gate and the top control electrode, the device realizes the multi-channel cooperative conduction while maintaining the enhanced off-state characteristic, effectively reduces the on-state resistance and improves the large-current working capacity. The device is suitable for gallium nitride power electronic applications with high efficiency and low loss.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to an enhanced gallium nitride power device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN)-based power devices have been widely used in power electronics, communication power supplies, and new energy vehicles due to their high critical breakdown electric field, high electron mobility, and excellent high-frequency characteristics. However, as application scenarios increasingly demand higher system efficiency, power density, and heat dissipation performance, further reducing the on-resistance of GaN power devices has become one of the key issues that urgently need to be addressed in this field.

[0003] Existing GaN power devices typically utilize a two-dimensional electron gas (2DEG) formed by an AlGaN / GaN heterojunction as the primary current-carrying channel, reducing on-resistance by increasing polarization intensity or channel electron concentration. However, this approach still faces several limitations in practical applications. On one hand, the current-carrying capacity of a single 2DEG channel is limited, and it is easily constrained by speed saturation, thermal effects, and reliability issues under high-current operating conditions. On the other hand, to achieve enhancement-mode operation, existing technologies generally introduce p-type GaN gate structures, concave gate structures, or composite gate structures to deplete the 2DEG. However, these structures often introduce additional gate-controlled impedance, parasitic capacitance, or process complexity, leading to increased on-resistance losses while maintaining enhancement-mode characteristics. To address this, some research has attempted to introduce additional 2DEG through multi-heterojunction stacks or multi-channel structures to achieve parallel conduction. However, such approaches are usually limited by inter-channel interference, parasitic conduction in the off-state, and device control complexity, making it difficult to simultaneously meet the requirements of low on-resistance and stable enhancement-mode operation. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a multi-channel GaN power device structure based on surface epitaxy. After completing the source, drain, and gate three-terminal structures, a multi-layer heterostructure is sequentially epitaxially formed on the device surface, thereby constructing multiple parallel current-carrying channels in the vertical direction of the device. Simultaneously, this invention places an independent top control electrode on the uppermost layer of the device to individually regulate the two-dimensional hole gas formed by the GaN / AlN heterojunction, ensuring it is either depleted or suppressed in the off-state and controlled to participate in current carrying under on-state conditions. Through this structural design, this invention achieves multi-channel parallel conduction while maintaining enhancement-mode operating characteristics, effectively reducing the device's equivalent on-resistance and avoiding the parasitic conduction and control coupling problems commonly found in existing multi-channel GaN devices, resulting in superior low-loss performance and application adaptability.

[0005] The present invention addresses the limitations of single-channel conduction capability in existing GaN power devices, the difficulty in further reducing on-resistance under enhancement-mode operating conditions, and the susceptibility of multi-channel structures to parasitic conduction and control coupling. It proposes an enhancement-mode gallium nitride power device and its fabrication method. This structure, while maintaining enhancement-mode operating characteristics, achieves effective control of multiple current-carrying channels, thereby significantly reducing the device's equivalent on-resistance and improving its overall performance in high-efficiency, low-loss power electronics applications.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An enhanced gallium nitride power device includes a substrate layer, a buffer layer on the substrate layer, a channel layer on the buffer layer, a heterojunction barrier layer on the channel layer, and a p-type cap layer on the heterojunction barrier layer.

[0008] The channel layer and the heterojunction barrier layer form the first two-dimensional electron gas channel under polarization.

[0009] The enhanced gallium nitride power device has a four-port structure and also includes a source, a drain, a main gate, and a top control electrode. The main gate is disposed on the p-type cap layer, and the source and drain are separately disposed on the upper surface of the heterojunction barrier layer and form an ohmic contact with the first two-dimensional electron gas channel.

[0010] The enhanced gallium nitride power device also includes a secondary epitaxial structure, which is epitaxially grown on the heterojunction barrier layer and the main gate, and includes, from bottom to top, a surface barrier layer, a second barrier layer, a surface channel layer and a hole-inducing layer; the surface barrier layer located on the upper surface region of the main gate is partially removed;

[0011] The top control electrode is disposed on the surface of the hole-inducing layer and is electrically isolated from the main gate and led out independently; wherein, the second barrier layer and the surface channel layer above it form a second two-dimensional electron gas channel under polarization, and the surface channel layer and the hole-inducing layer above it form a two-dimensional hole gas under polarization.

[0012] The enhanced gallium nitride power device forms three parallel current-carrying channels in the vertical direction: a first two-dimensional electron gas channel, a second two-dimensional electron gas channel, and a two-dimensional hole gas channel.

[0013] In the device off state, the main gate performs depletion control on the first two-dimensional electron gas channel, the second two-dimensional electron gas channel is in a depleted state, and the two-dimensional hole gas is suppressed under the action of the top control electrode, so that the device as a whole exhibits enhanced turn-off characteristics.

[0014] When the device is in the on state, a forward bias is applied to the main gate, and the first two-dimensional electron gas channel first forms a conduction channel. As the bias voltage or operating current increases, the second two-dimensional electron gas channel gradually participates in current carrying. At the same time, the participation of the two-dimensional hole gas is adjusted by the top control electrode, so that the three current-carrying channels work in parallel, thereby effectively reducing the equivalent on-resistance of the device.

[0015] Furthermore, the surface barrier layer in the secondary epitaxial structure is a group III nitride barrier material layer, preferably AlGaN, and in some embodiments it may also be GaN or an equivalent barrier material. The thickness of the surface barrier layer ranges from about 5 nm to 10 nm.

[0016] Furthermore, the second barrier layer in the secondary epitaxial structure is made of the same or similar material as the surface barrier layer. The second barrier layer is a group III nitride barrier material layer, preferably AlGaN, and in some embodiments it may also be GaN or an equivalent material. The thickness of the second barrier layer ranges from about 10 nm to 15 nm.

[0017] Furthermore, the surface channel layer in the secondary epitaxial structure is a GaN layer, used as a carrier transport channel, with a thickness ranging from approximately 100 nm to 400 nm.

[0018] Furthermore, the hole-inducing layer in the secondary epitaxial structure is a group III nitride layer with strong polarization characteristics. The material can be selected from AlN, AlGaN or GaN, preferably AlN, and the thickness of the hole-inducing layer ranges from about 100 nm to 400 nm.

[0019] Furthermore, the top control electrode is a metal electrode, and its material can be a metal stack structure such as Ni / Au or Ti / Au, with the total thickness of the metal stack ranging from approximately 50 nm to 500 nm.

[0020] Furthermore, the top control electrode forms an electric field coupling relationship with the hole-inducing layer through a metal / semiconductor structure or a metal / dielectric / semiconductor structure.

[0021] This invention also provides a method for fabricating an enhanced gallium nitride power device, specifically including the following steps:

[0022] First, the original epitaxial structure is prepared; a buffer layer is epitaxially grown on the substrate layer, a channel layer is epitaxially grown on the buffer layer, a heterojunction barrier layer is epitaxially grown on the channel layer, and a p-type cap layer is epitaxially grown on the heterojunction barrier layer.

[0023] Then, the mesa and electrode structures of the device are fabricated. First, the mesa region is patterned by photolithography on the device surface, and the mesa structure is formed by etching to define the active and isolation regions of the device. Then, in the gate region corresponding to the main gate, the p-type cap layer disposed on the heterojunction barrier layer is selectively etched to remove the p-type material outside the gate region and expose the underlying heterojunction barrier layer. The source and drain regions are defined on the surface of the heterojunction barrier layer, and an ohmic contact structure is formed. The main gate is fabricated on the upper surface of the p-type cap layer.

[0024] Finally, a secondary surface epitaxy is performed on the device surface. First, a surface barrier layer is epitaxially grown on the device surface. Then, selective etching is performed on the surface barrier layer on the main gate surface to remove or thin it. Then, a second barrier layer is epitaxially grown on the entire device surface to cover the surface barrier layer and its etched area. A surface channel layer is epitaxially grown on the second barrier layer, and a hole-inducing layer is further epitaxially grown on the surface channel layer. A top control electrode is fabricated on the surface of the hole-inducing layer.

[0025] The beneficial effects of this invention are as follows:

[0026] Multi-channel parallel conduction significantly reduces on-resistance: This invention introduces a secondary epitaxial layer after completing the original three-terminal GaN device structure, sequentially constructing a first two-dimensional electron gas channel, a second two-dimensional electron gas channel, and a two-dimensional hole gas channel in the vertical direction of the device. This allows multiple current-carrying channels to participate in current transmission in parallel during conduction. Compared to existing device structures that rely solely on a single two-dimensional electron gas channel, this invention effectively increases the current-carrying cross-sectional area at the device structure level, significantly reducing the equivalent on-resistance of the device, thereby reducing conduction losses.

[0027] Maintaining enhanced turn-off characteristics and avoiding parasitic conduction: This invention uses the main gate to deplete the first two-dimensional electron gas channel, and combines the surface secondary epitaxial structure and the top control electrode to constrain the potential of the second two-dimensional electron gas channel and the two-dimensional hole gas, so that each current-carrying channel is in a depleted or weakly conductive state under zero gate bias conditions, thereby ensuring that the device as a whole exhibits an enhanced operating mode and effectively avoiding the parasitic conduction problem in the turn-off state that is common in multi-channel structures.

[0028] Independent control of two-dimensional hole gas enhances device operational flexibility: This invention features an independently led-out top control electrode on the uppermost layer of the device, enabling individual electric field control of the two-dimensional hole gas. This suppresses the two-dimensional hole gas in the off state and allows it to participate in parallel current carrying under controlled conditions when the device is on or operating at high current. This independent control method avoids control coupling between the two-dimensional hole gas and the two-dimensional electron gas, improving the device's controllability and operational stability.

[0029] Balancing low loss and high reliability, suitable for high-current applications: Under high-current operating conditions, the two-dimensional hole gas participates in conduction as a parallel current-carrying channel, which helps to share the current density in the two-dimensional electron gas channel, alleviate the current congestion and local heating problems in a single channel, thereby improving the reliability and long-term stability of the device in high-power, high-current applications. Attached Figure Description

[0030] Figure 1 This is a schematic cross-sectional view of an enhanced gallium nitride power device structure according to an embodiment of the present invention.

[0031] Figure 2 This is a schematic diagram of the epitaxial layer structure of an enhanced gallium nitride power device structure in one embodiment of the present invention.

[0032] Figure 3 This is a schematic diagram of the process flow and implementation method of an enhanced gallium nitride power device according to an embodiment of the present invention.

[0033] Explanation of reference numerals in the attached figures: 1. Surface barrier layer; 2. Second barrier layer; 3. Surface channel layer; 4. Hole-inducing layer; 5. Heterojunction barrier layer; 6. Channel layer; 7. Buffer layer; 8. Substrate layer; 9. P-type cap layer; 10. Source; 11. Drain; 12. Main gate; 13. Top control electrode; 14. First two-dimensional electron gas channel; 15. Second two-dimensional electron gas channel; 16. Two-dimensional hole gas. Detailed Implementation

[0034] The specific implementation methods of the present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following implementation methods.

[0035] See Formation of an epitaxial structure for an enhanced gallium nitride power device. Figure 1 , Figure 2 In this embodiment, the device is fabricated based on a group III nitride material system, and its original epitaxial structure forms the following layers from bottom to top:

[0036] First, a buffer layer 7 is epitaxially grown on the substrate layer 8. The buffer layer 7 is used to improve lattice mismatch and suppress leakage current. Subsequently, a channel layer 6 is epitaxially grown on the buffer layer 7, a heterojunction barrier layer 5 is epitaxially grown on the channel layer 6, and a p-type cap layer 9 is epitaxially grown on the heterojunction barrier layer 5. The channel layer 6 and the heterojunction barrier layer 5 form a first two-dimensional electron gas channel 14 under polarization.

[0037] After completing the original GaN device epitaxial structure, a secondary epitaxial growth is performed on the device surface to construct a multi-heterojunction stacked current-carrying structure. The secondary epitaxial structure, from bottom to top, includes a surface barrier layer 1, a second barrier layer 2, a surface channel layer 3, and a hole-inducing layer 4. The second barrier layer 2 and the surface channel layer 3 above it form a second two-dimensional electron gas channel 15 under polarization, and the surface channel layer 3 and the hole-inducing layer 4 above it form a two-dimensional hole gas 16 under polarization.

[0038] Through the above epitaxial structure design, three parallel current-carrying channels are formed in the vertical direction of the device: a first two-dimensional electron gas channel 14, a second two-dimensional electron gas channel 15, and a two-dimensional hole gas channel 16.

[0039] Furthermore, the surface barrier layer 1 in the secondary epitaxial structure is a group III nitride barrier material layer, preferably AlGaN, and in some embodiments it may also be GaN or an equivalent barrier material. The thickness of the surface barrier layer 1 ranges from about 5 nm to 10 nm.

[0040] Furthermore, the second barrier layer 2 in the secondary epitaxial structure is made of the same or similar material as the surface barrier layer 1. The second barrier layer 2 is a group III nitride barrier material layer, preferably AlGaN, and in some embodiments it can also be GaN or an equivalent material. The thickness of the second barrier layer 2 ranges from about 10 nm to 15 nm.

[0041] Furthermore, the surface channel layer 3 in the secondary epitaxial structure is a GaN layer, used as a carrier transport channel, with a thickness ranging from approximately 100 nm to 400 nm.

[0042] Furthermore, the hole-inducing layer 4 in the secondary epitaxial structure is a group III nitride layer with strong polarization characteristics. The material can be selected from AlN, AlGaN or GaN, preferably AlN, and the thickness of the hole-inducing layer 4 ranges from about 100 nm to 400 nm.

[0043] See device electrode structure. Figure 1 After the epitaxial structure growth is completed, the source electrode 10, drain electrode 11, main gate electrode 12 and top control electrode 13 are sequentially fabricated.

[0044] In this configuration, the source electrode 10 and the drain electrode 11 are separately disposed on the upper surface of the heterojunction barrier layer 5 and form an ohmic contact with the first two-dimensional electron gas channel 14.

[0045] The main gate 12 is disposed on the upper surface of the p-type cap layer 9 and is used to control the first two-dimensional electron gas channel 14 located below it and the second two-dimensional electron gas channel 15 located above it. The surface barrier layer 1 in the region corresponding to the main gate 12 is partially removed by etching, allowing the second barrier layer 2 in that region to directly contact the surface of the main gate 12, thereby changing the equivalent barrier structure of the gate region. By controlling the bias of the main gate 12, the first two-dimensional electron gas channel 14 and the second two-dimensional electron gas channel 15 can be in a depletion state under zero gate bias conditions, thereby achieving the enhancement-mode operation of the device.

[0046] The top control electrode 13 is disposed on the surface of the hole-inducing layer 4 and is electrically isolated from the main gate 12 and independently led out, for individual control of the two-dimensional hole gas 16. The top control electrode 13 can form an electric field coupling relationship with the underlying epitaxial layer through a metal / semiconductor structure or a metal / dielectric / semiconductor structure, so that the two-dimensional hole gas 16 is in a depleted or suppressed state in the off state, and participates in parallel current carrying under controlled conditions when the device is on or under high current operation.

[0047] By applying bias voltages to the main gate 12 and the top control electrode 13 respectively, the first two-dimensional electron gas channel 14, the second two-dimensional electron gas channel 15 and the two-dimensional hole gas 16 can be independently controlled, thereby ensuring the enhancement-mode turn-off characteristics while enabling multiple current-carrying channels to work together in the on state, so as to reduce the equivalent on resistance of the device.

[0048] Furthermore, the top control electrode 13 is a metal electrode, and its material can be a metal stack structure such as Ni / Au or Ti / Au, with the total thickness of the metal stack ranging from about 50 nm to 500 nm.

[0049] A method for fabricating an enhanced gallium nitride power device is described in [reference needed]. Figure 3 After the initial epitaxial structure growth is completed, the device's mesa and electrode structures are fabricated. Specifically, the device surface is first patterned using photolithography to create the mesa region, and then etched to form the mesa structure, defining the active and isolation regions of the device. Subsequently, in the gate region corresponding to the main gate, the p-type cap layer 9 disposed on the heterojunction barrier layer 5 is selectively etched to remove the p-type material outside the gate region and expose the underlying heterojunction barrier layer 5.

[0050] After etching the p-type cap layer 9, the source 10 and drain 11 regions are defined on the surface of the heterojunction barrier layer 5, and ohmic contact structures are formed in the corresponding regions. Subsequently, the main gate 12 is fabricated in the gate region (i.e., the upper surface of the p-type cap layer 9) and positioned above the heterojunction barrier layer 5 to perform gate-controlled modulation of the first two-dimensional electron gas channel 14 formed by the channel layer 6 and the heterojunction barrier layer 5.

[0051] After completing the main gate 12 structure, a secondary surface epitaxy is performed on the device surface. During this secondary epitaxy, a surface barrier layer 1 is first grown on the device surface. Then, selective etching is performed on the surface barrier layer 1 within the gate region corresponding to the main gate 12 (i.e., the upper surface of the main gate 12), removing or thinning the surface barrier layer 1 in this region, thereby changing the equivalent barrier structure at the gate region. The barrier structure in this region changes from a stack of surface barrier layer 1 and second barrier layer 2 to an equivalent barrier structure dominated by the second barrier layer 2, thereby reducing the equivalent barrier thickness at the gate region, enhancing gate control electric field coupling, and enabling the second two-dimensional electron gas channel 15 to be in a depleted or weakly conductive state under zero gate bias conditions, achieving normally off operation.

[0052] After etching the gate region of the surface barrier layer 1, a second barrier layer 2 is epitaxially grown on the entire device surface, covering the surface barrier layer 1 and its etched area. Subsequently, a surface channel layer 3 is epitaxially grown on the second barrier layer 2, and a hole-inducing layer 4 is further epitaxially grown on the surface channel layer 3, thereby completing the secondary epitaxial stacked structure for forming the second two-dimensional electron gas channel 15 and the two-dimensional hole gas 16.

[0053] After completing all epitaxial layer structures, a top control electrode 13 is fabricated on the surface of the hole-inducing layer 4, so that it forms an electric field coupling relationship with the heterojunction of the surface channel layer 3 / hole-inducing layer 4 below, and the top control electrode 13 is independently led out for individual control of the two-dimensional hole gas 16.

[0054] The enhanced four-port gallium nitride power device of the present invention introduces a multilayer heterostructure in the vertical direction of the device to construct multiple parallel current-carrying channels, and combines independent bias control of the main gate and the top control electrode to achieve synergistic optimization between enhanced turn-off characteristics and low on-resistance. Its working principle is as follows.

[0055] In the original epitaxial structure of the device, the channel layer and the heterojunction barrier layer form the first two-dimensional electron gas channel under polarization. By introducing a p-type cap layer above this channel and setting the main gate, the main gate can effectively deplete the first two-dimensional electron gas channel under zero gate bias conditions, putting it in the off state, thereby ensuring that the device has enhancement-mode operating characteristics.

[0056] After completing the original three-terminal device structure, a surface barrier layer, a second barrier layer, a surface channel layer, and a hole-inducing layer are sequentially formed on the device surface through secondary surface epitaxy. At the interface between the second barrier layer and the surface channel layer, a second two-dimensional electron gas channel is formed under polarization; at the interface between the surface channel layer and the hole-inducing layer, a two-dimensional hole gas is formed under reverse polarization. Thus, a multi-channel current-carrying system with two two-dimensional electron gas channels and one two-dimensional hole gas channel coexisting is formed inside the device.

[0057] For the second two-dimensional electron gas channel, selective etching is performed on the surface barrier layer in the gate region corresponding to the main gate to reduce the equivalent barrier thickness in the gate region, thereby enhancing the gate electric field's ability to control the surface channel layer. This allows the second two-dimensional electron gas channel to be in a depleted or weakly conductive state under zero gate bias conditions, preventing it from forming a parasitic conduction channel in the off state.

[0058] The top control electrode is disposed on the surface of the hole-inducing layer and is electrically isolated from the main gate and led out independently. By applying a bias voltage to the top control electrode, a vertical electric field can be established above the heterojunction formed by the surface channel layer and the hole-inducing layer, so that the two-dimensional hole gas is in a depleted or suppressed state in the off state; under device conduction or high current operation conditions, the two-dimensional hole gas can be controlled to participate in current carrying by adjusting the bias of the top control electrode.

[0059] In the device off state, the main gate performs depletion control on the first two-dimensional electron gas channel, and the second two-dimensional electron gas channel is in a depleted state due to the equivalent barrier structure. The two-dimensional hole gas is suppressed under the action of the top control electrode, so that the device as a whole exhibits enhancement-type turn-off characteristics.

[0060] When the device is in the on state, a forward bias is applied to the main gate, and the first two-dimensional electron gas channel forms a conduction channel. As the bias voltage or operating current increases, the second two-dimensional electron gas channel gradually participates in current carrying. At the same time, the participation of the two-dimensional hole gas is adjusted by the top control electrode, so that multiple current-carrying channels work in parallel, thereby effectively reducing the equivalent on-resistance of the device and improving the device's conduction capability and operating stability under high current conditions.

[0061] Based on the above working principle, this invention achieves multi-channel coordinated conduction and independent control of two-dimensional hole gas while ensuring enhanced turn-off characteristics, taking into account both low conduction loss and device reliability, and is suitable for high-efficiency gallium nitride power device applications.

[0062] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. An enhanced gallium nitride power device, characterized in that, include: Substrate layer (8), buffer layer (7) on substrate layer (8), channel layer (6) on buffer layer (7), heterojunction barrier layer (5) on channel layer (6), p-type cap layer (9) on heterojunction barrier layer (5). The channel layer (6) and the heterojunction barrier layer (5) form the first two-dimensional electron gas channel (14) under polarization. The enhanced gallium nitride power device is a four-port structure, and also includes a source (10), a drain (11), a main gate (12) and a top control electrode (13). The main gate (12) is disposed on the p-type cap layer (9), and the source (10) and drain (11) are separately disposed on the upper surface of the heterojunction barrier layer (5) and form an ohmic contact with the first two-dimensional electron gas channel (14). The enhanced gallium nitride power device also includes a secondary epitaxial structure, which is epitaxially grown on the heterojunction barrier layer (5) and the main gate (12), and includes, from bottom to top, a surface barrier layer (1), a second barrier layer (2), a surface channel layer (3) and a hole-inducing layer (4); the surface barrier layer (1) located on the upper surface region of the main gate (12) is removed or partially removed; The top control electrode (13) is disposed on the surface of the hole-inducing layer (4) and electrically isolated from the main gate (12) and independently led out; wherein, the second barrier layer (2) and its upper surface channel layer (3) form a second two-dimensional electron gas channel (15) under polarization, and the surface channel layer (3) and its upper hole-inducing layer (4) form a two-dimensional hole gas (16) under polarization.

2. The enhanced gallium nitride power device according to claim 1, characterized in that, The enhanced gallium nitride power device forms three parallel current-carrying channels in the vertical direction: a first two-dimensional electron gas channel (14), a second two-dimensional electron gas channel (15), and a two-dimensional hole gas channel (16).

3. The enhanced gallium nitride power device according to claim 1, characterized in that, In the device off state, the main gate (12) implements depletion control on the first two-dimensional electron gas channel (14), the second two-dimensional electron gas channel (15) is in a depletion state, and the two-dimensional hole gas (16) is suppressed under the action of the top control electrode, so that the device as a whole exhibits enhanced turn-off characteristics. When the device is in the on state, the main gate (12) is forward biased, and the first two-dimensional electron gas channel (14) first forms a conduction channel; as the bias voltage or operating current increases, the second two-dimensional electron gas channel (15) gradually participates in current carrying, and at the same time, the participation of two-dimensional hole gas is adjusted by the top control electrode (13) so that the three current carrying channels work in parallel, thereby effectively reducing the equivalent on resistance of the device.

4. The enhanced gallium nitride power device according to claim 1, characterized in that, The surface barrier layer (1) is a group III nitride barrier material layer with a thickness ranging from 5 nm to 10 nm; the second barrier layer (2) is a group III nitride barrier material layer with a thickness ranging from 10 nm to 15 nm.

5. The enhanced gallium nitride power device according to claim 1, characterized in that, The surface trench layer (3) is a GaN layer with a thickness ranging from 100 nm to 400 nm.

6. The enhanced gallium nitride power device according to claim 1, characterized in that, The hole-inducing layer (4) is a group III nitride layer with strong polarization characteristics, and its thickness ranges from 100 nm to 400 nm.

7. The enhanced gallium nitride power device according to claim 1, characterized in that, The top control electrode (13) is a metal electrode with a Ni / Au or Ti / Au metal stack structure, and the total thickness of the metal stack ranges from 50 nm to 500 nm.

8. The enhanced gallium nitride power device according to claim 1, characterized in that: The top control electrode (13) forms an electric field coupling relationship with the hole-inducing layer (4) through a metal / semiconductor structure or a metal / dielectric / semiconductor structure.

9. A method for fabricating an enhanced gallium nitride power device as described in any one of claims 1-8, characterized in that, Specifically, the following steps are included: First, the original epitaxial structure is prepared; a buffer layer (7) is epitaxially grown on the substrate layer (8), a channel layer (6) is epitaxially grown on the buffer layer (7), a heterojunction barrier layer (5) is epitaxially grown on the channel layer (6), and a p-type cap layer (9) is epitaxially grown on the heterojunction barrier layer (5). Then, the device's mesa and electrode structures are fabricated. First, the device surface is photolithographically patterned and the mesa region is patterned. The mesa structure is formed by etching to define the active and isolation regions of the device. Then, in the gate region corresponding to the main gate, the p-type cap layer (9) disposed on the heterojunction barrier layer (5) is selectively etched to remove the p-type material outside the gate region and expose the heterojunction barrier layer (5) below. The source (10) and drain (11) regions are defined on the surface of the heterojunction barrier layer (5), and an ohmic contact structure is formed. The main gate (12) is fabricated on the upper surface of the p-type cap layer (9). Next, a secondary surface epitaxy is performed on the device surface; first, a surface barrier layer (1) is epitaxially grown on the device surface; then, selective etching is performed on the surface barrier layer (1) on the upper surface of the main gate (12) to remove or thin the surface barrier layer (1) on the upper surface of the main gate (12); then, a second barrier layer (2) is epitaxially grown on the entire device surface to cover the surface barrier layer (1) and its etched area; a surface channel layer (3) is epitaxially grown on the second barrier layer (2), and a hole-inducing layer (4) is further epitaxially grown on the surface channel layer (3); Finally, a top control electrode (13) is prepared on the surface of the hole-inducing layer (4).

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