Electrostatic discharge protection device structure and microprocessing chip

Abstract

The application provides an electrostatic discharge protection device structure and a micro processing chip. The electrostatic discharge protection device structure comprises a substrate of a first conductive type, a gate structure arranged on the substrate, and a source region and a drain region arranged on two sides of the gate structure respectively; the drain region comprises a first doped region of a second conductive type and a plurality of second doped regions of the first conductive type arranged in the first doped region of the second conductive type, and the plurality of second doped regions of the first conductive type are arranged at intervals along the extension direction of the gate structure. The application can improve the current discharge capacity of the electrostatic discharge protection device, and further improve the overall electrostatic discharge protection capacity of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a structure and microprocessor chip for electrostatic discharge protection device. Background Technology

[0002] As semiconductor process technology continues to iterate, chip size is decreasing, and devices are becoming increasingly sensitive to electrostatic discharge (ESD) events.

[0003] To ensure that ESD protection devices function effectively, their operating voltage range typically needs to match the design window of the protected device. For high-voltage ESD protection devices, strong current discharge capability and high robustness are usually required; the lower the on-resistance, the stronger the current discharge capability of the device.

[0004] However, with the development of technology and the demand for high-voltage processes, while improving the withstand voltage of devices, the current discharge capability of devices is often affected to a certain extent, making it difficult to balance withstand voltage performance and ESD protection performance.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] Based on this, the embodiments of this application provide an electrostatic discharge protection device structure and a microprocessor chip, which can improve the current discharge capability of the electrostatic discharge protection device, thereby improving the overall electrostatic discharge protection capability of the device.

[0007] According to some embodiments, this application provides an electrostatic discharge protection device structure, including: Substrate of the first conductivity type; A gate structure disposed on the substrate; and The source and drain regions are respectively disposed on both sides of the gate structure; The drain region includes a first doped region of a second conductivity type and a plurality of second doped regions of a first conductivity type disposed within the first doped region of the second conductivity type, the plurality of second doped regions of the first conductivity type being arranged at intervals along the extension direction of the gate structure.

[0008] In some embodiments, the second doped region of the first conductivity type is embedded in the first doped region of the second conductivity type in the thickness direction of the substrate.

[0009] In some embodiments, the surface of the second doped region of the first conductivity type is flush with the surface of the first doped region of the second conductivity type.

[0010] In some embodiments, the gate structure includes a polysilicon gate layer, the polysilicon gate layer being a continuous, integral structure in the extension direction of the gate structure.

[0011] In some embodiments, the source region includes a third doped region of a second conductivity type, and the third doped region of the second conductivity type is a continuous region in the extension direction of the gate structure.

[0012] In some embodiments, the electrostatic discharge protection device structure further includes a body contact region disposed on the side of the source region away from the gate structure, the body contact region including a fourth doped region of a first conductivity type.

[0013] In some embodiments, a shallow groove isolation structure is provided between the source region and the body contact region.

[0014] In some embodiments, the source region is connected to the gate structure and connected to a reference ground.

[0015] In some embodiments, the electrostatic discharge protection device structure includes a gate-grounded metal-oxide-semiconductor field-effect transistor structure.

[0016] According to some embodiments, this application also provides a microprocessor chip, which includes the electrostatic discharge protection device structure provided in the foregoing embodiments.

[0017] The embodiments of this application may have, or at least have, the following advantages: The electrostatic discharge (ESD) protection device structure provided in this application embodiment includes multiple second doped regions of the first conductivity type within a first doped region of the second conductivity type in the drain region, and these multiple second doped regions of the first conductivity type are spaced apart along the extension direction of the gate structure. By improving the drain region doping structure, the release path of non-equilibrium carriers can be increased, allowing current to be discharged in multiple directions during ESD, thereby improving the device's ESD discharge capability. Furthermore, the improvement in the drain region doping structure helps reduce the device's on-resistance, thus improving the device's failure current; simultaneously, under the same discharge current, reducing the device's on-resistance helps generate more electron-hole pairs, thereby improving the device's sustaining voltage and ultimately enhancing the overall ESD protection capability of the device.

[0018] Other advantages, objectives, and features of this application will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from practice of this application. The objectives and other advantages of this application can be realized and obtained through the following description. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0020] Figure 1 This is a three-dimensional structural schematic diagram of the electrostatic discharge protection device structure provided in some embodiments of this application; Figure 2 This is a three-dimensional structural diagram of the electrostatic discharge protection device structure provided in some embodiments of this application, in which the source region and the gate structure are connected and connected to a reference ground.

[0021] Explanation of reference numerals in the attached figures: 100, Substrate; 200, Gate structure; 300, Source region; 400, Drain region; 400a, First doped region of second conductivity type; 400b, Second doped region of first conductivity type; 500, Bulk contact region; 600, Shallow trench isolation structure; 700, silicide barrier structure. Detailed Implementation

[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0024] It should be understood that when an element or layer is referred to as "on" or "connected to," it may be directly located on or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first conductivity type may be referred to as a second conductivity type, and similarly, a second conductivity type may be referred to as a first conductivity type; the first conductivity type and the second conductivity type are different conductivity types, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, or the first conductivity type may be N-type and the second conductivity type may be P-type.

[0025] It should be understood that, in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "located on" will be oriented "below" other elements or features. Thus, the exemplary term "on" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] It is understood that the term "connected" in the following embodiments should be interpreted as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0027] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “composes” and / or “comprises” are used in this specification, the presence of the stated feature, integer, element, and / or part is established, but the presence or addition of one or more other features, integers, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] As semiconductor process technology continues to iterate, chip size is decreasing, and devices are becoming increasingly sensitive to electrostatic discharge (ESD) events.

[0029] To ensure that ESD protection devices function effectively, their operating voltage range typically needs to match the design window of the protected device. For high-voltage ESD protection devices, strong current discharge capability and high robustness are usually required; the lower the on-resistance, the stronger the current discharge capability of the device.

[0030] However, with the development of technology and the demand for high-voltage processes, while improving the withstand voltage of devices, the current discharge capability of devices is often affected to a certain extent, making it difficult to balance withstand voltage performance and ESD protection performance.

[0031] Therefore, this application aims to provide a solution that can address the aforementioned technical problems, improve the current discharge capability of electrostatic discharge protection devices, and thus enhance the overall electrostatic discharge protection capability of the devices. Details will be elaborated in subsequent embodiments.

[0032] According to some embodiments, this application provides an electrostatic discharge protection device structure, including a substrate of a first conductivity type, a gate structure disposed on the substrate, and a source region and a drain region respectively disposed on both sides of the gate structure.

[0033] The drain region includes a first doped region of a second conductivity type and a plurality of second doped regions of a first conductivity type disposed within the first doped region of the second conductivity type. The plurality of second doped regions of the first conductivity type are arranged at intervals along the extension direction of the gate structure.

[0034] The above-mentioned electrostatic discharge protection device structure has multiple second doped regions of the first conductivity type in the drain region, and the multiple second doped regions of the first conductivity type are arranged at intervals along the extension direction of the gate structure.

[0035] By making the above improvements to the drain region doping structure, the release path of non-equilibrium carriers can be increased, allowing the current to be discharged in multiple directions during electrostatic discharge, thereby improving the electrostatic discharge discharge capability of the device.

[0036] Furthermore, the improvement of the drain region doping structure described above helps to reduce the device's on-resistance, which in turn helps to increase the device's failure current. At the same time, under the same discharge current, reducing the device's on-resistance helps to generate more electron-hole pairs, which in turn helps to increase the device's sustaining voltage and thus improve the device's overall electrostatic discharge protection capability.

[0037] The above is the core idea of ​​this application. The following will combine... Figure 1 and Figure 2The technical solutions in the embodiments of this application are clearly and completely described. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] It should be noted that the embodiments of this application do not limit the specific type of electrostatic discharge protection device structure. In some embodiments, the electrostatic discharge protection device structure includes a gate grounded metal-oxide-semiconductor field-effect transistor (GGMOS) structure.

[0039] Furthermore, for example, the GGMOS structure can be a high-voltage GGMOS structure. As an example, the high-voltage GGMOS structure can be suitable for applications with higher operating voltages, such as operating voltages greater than or equal to 12V, but it is not limited thereto, and this application does not impose any limitations on it.

[0040] It should be understood that the subsequent embodiments of this application use the GGNMOS structure as an example for illustration, but the technical solutions of this application can also be applied to other applicable electrostatic discharge protection device structures, and this application does not limit them.

[0041] The electrostatic discharge protection device structure provided in this application embodiment may specifically include a substrate 100 of a first conductivity type, a gate structure 200, a source region 300, and a drain region 400. The gate structure 200 is disposed on the substrate 100, and the source region 300 and the drain region 400 are respectively disposed on both sides of the gate structure 200.

[0042] The drain region 400 includes a first doped region 400a of a second conductivity type and a plurality of second doped regions 400b of the first conductivity type disposed within the first doped region 400a. The plurality of second doped regions 400b of the first conductivity type extend along the extension direction of the gate structure 200 (e.g., ...). Figure 1 The X-direction (as shown) is arranged at intervals.

[0043] It should be noted that, in the embodiments of this application, the doping concentration of the second doped region 400b of the first conductivity type can be adjusted according to actual electrical requirements. For example, the doping concentration of the second doped region 400b of the first conductivity type can be set accordingly based on the device's operating voltage, electrostatic discharge protection performance requirements, and / or other electrical parameters. This application does not limit this.

[0044] For ease of description, the following embodiments in this specification use P-type as the first conductivity type and N-type as the second conductivity type as examples. However, those skilled in the art should understand that, without departing from the inventive concept of this application, the first conductivity type and the second conductivity type can also be N-type and P-type, respectively. Correspondingly, the conductivity type of each doped region can be replaced accordingly, and the same technical effect can be achieved. This application does not limit this.

[0045] Therefore, in this embodiment, as Figure 1 As shown, the electrostatic discharge protection device structure includes a substrate 100, such as a P-type substrate.

[0046] In some embodiments, a second doped region 400b of a first conductivity type (e.g., P-type) is embedded in a first doped region 400a of a second conductivity type (e.g., N-type) in the thickness direction of the substrate 100.

[0047] In the above embodiments, by making the second doped region 400b of the first conductivity type (e.g., P-type) in the thickness direction of the substrate 100 (e.g., ... Figure 1 The doped regions (shown in the Z direction) are embedded into the first doped region 400a of the second conductivity type (e.g., N-type), forming a three-dimensional doped cross structure in the drain region 400 with different conductivity types. This helps to further increase the release paths of non-equilibrium carriers, ensuring that the current can be discharged in multiple directions during electrostatic discharge, effectively improving the electrostatic discharge discharge capability of the device.

[0048] In some embodiments, the surface of the second doped region 400b of the first conductivity type (e.g., P-type) is flush with the surface of the first doped region 400a of the second conductivity type (e.g., N-type) to form a relatively flat drain surface structure.

[0049] In some embodiments, the gate structure 200 includes a polysilicon gate layer, which is a continuous, integrated structure in the extension direction of the gate structure 200.

[0050] In some embodiments, the source region 300 includes a third doped region of a second conductivity type (e.g., N-type), and the third doped region of the second conductivity type (e.g., N-type) is a continuous region in the extension direction of the gate structure 200.

[0051] In some embodiments, the electrostatic discharge protection device structure further includes a body contact region 500 disposed on the side of the source region 300 away from the gate structure 200, the body contact region 500 including a fourth doped region of a first conductivity type (e.g., P-type).

[0052] In some embodiments, a shallow groove isolation structure 600 is provided between the source region 300 and the body contact region 500.

[0053] In some embodiments, the source region 300 is connected to the gate structure 200 and connected to a reference ground.

[0054] Furthermore, as an example, the body contact region 500 can also be connected to the reference ground so that the source region 300, the gate structure 200, and the body contact region 500 are all connected to the reference ground.

[0055] Furthermore, please combine Figure 2 Understand the current discharge path during electrostatic discharge in some embodiments of this application.

[0056] In a traditional GGNMOS structure, the drain region only contains doped regions of the second conductivity type. During electrostatic discharge, the current can only form as shown in the diagram. Figure 2 The current discharge path I1 shown is used for current discharge.

[0057] Please continue reading. Figure 2 It is understood that, compared to the traditional GGNMOS structure, in this embodiment, multiple second doped regions 400b of the first conductivity type are disposed within the first doped region 400a of the second conductivity type, forming a doped cross-three-dimensional structure in the drain region 400. During electrostatic discharge, in addition to the original current discharge path I1, the current can also form a new current discharge path I2 via the first doped region 400a of the second conductivity type, the second doped region 400b of the first conductivity type, and the substrate 100. Since the multiple second doped regions 400b of the first conductivity type are arranged at intervals along the extension direction of the gate structure 200, multiple new current discharge paths I2 can be formed, allowing the current to be released in multiple directions.

[0058] More specifically, for example Figure 2 As shown, the N+ doped region connected to the drain is the region where electrostatic current enters the device. The current first enters the N+ doped region in the drain region 400 from the drain, then flows to the P+ doped region located in the N+ doped region, and further flows to the P-type substrate, thus forming a new current discharge path I2.

[0059] It should be noted that since the second doped region 400b of the first conductivity type is disposed inside the first doped region 400a of the second conductivity type, each second doped region 400b of the first conductivity type can form a corresponding current discharge path with the first doped regions 400a of the second conductivity type on both sides. Figure 2The diagram only shows a few of the newly added current discharge paths I2 to facilitate understanding of the inventive concept of this application. In actual devices, multiple current discharge paths I2 distributed in different locations can be formed to participate in current discharge.

[0060] Therefore, by constructing a doped cross-shaped three-dimensional structure in the drain region 400, this embodiment adds multiple current discharge paths I2 while retaining the original current discharge path I1. This is beneficial for increasing the release paths of non-equilibrium carriers, reducing local current concentration, and improving the current discharge capability of the device.

[0061] In some embodiments, the electrostatic discharge protection device structure may further include a silicide barrier structure 700. The silicide barrier structure 700 is disposed on the substrate 100 and located on the side of the drain region 400 near the gate structure 200, and extends along the extension direction of the gate structure 200.

[0062] By setting the silicide barrier structure 700, metal silicide can be prevented from forming on the side of the drain region 400 near the gate structure 200, thereby preventing local current accumulation during electrostatic discharge and helping to make the electrostatic current more uniformly distributed in the extension direction of the gate structure 200, further improving the overall electrostatic discharge protection capability of the device.

[0063] This application does not limit the specific formation process and structural form of the silicide barrier structure 700. As an example, the silicide barrier structure 700 can be formed using a silicide block (SAB) process.

[0064] According to some embodiments, this application also provides a microprocessor chip. This microprocessor chip includes the electrostatic discharge protection device structure provided in the foregoing embodiments.

[0065] Since the electrostatic discharge protection device structure provided in the foregoing embodiments has been described in detail, its structure and working principle will not be repeated here. Because the microprocessor chip includes the electrostatic discharge protection device structure provided in the foregoing embodiments, the microprocessor chip can also achieve the technical effects that the foregoing electrostatic discharge protection device structure can achieve, and will not be repeated here.

[0066] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0067] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0068] In the description of this specification, references to terms such as "some embodiments," "as an example," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A structure for an electrostatic discharge protection device, characterized in that, include: Substrate of the first conductivity type; Gate structure disposed on the substrate; as well as The source and drain regions are respectively disposed on both sides of the gate structure; The drain region includes a first doped region of a second conductivity type and a plurality of second doped regions of a first conductivity type disposed within the first doped region of the second conductivity type, the plurality of second doped regions of the first conductivity type being arranged at intervals along the extension direction of the gate structure.

2. The electrostatic discharge protection device structure according to claim 1, characterized in that, The second doped region of the first conductivity type is embedded into the first doped region of the second conductivity type in the thickness direction of the substrate.

3. The electrostatic discharge protection device structure according to claim 2, characterized in that, The surface of the second doped region of the first conductivity type is flush with the surface of the first doped region of the second conductivity type.

4. The electrostatic discharge protection device structure according to claim 1, characterized in that, The gate structure includes a polysilicon gate layer, which is a continuous, integrated structure in the extension direction of the gate structure.

5. The electrostatic discharge protection device structure according to claim 1, characterized in that, The source region includes a third doped region of a second conductivity type, and the third doped region of the second conductivity type is a continuous region in the extension direction of the gate structure.

6. The electrostatic discharge protection device structure according to claim 1, characterized in that, The electrostatic discharge protection device structure further includes a body contact region disposed on the side of the source region away from the gate structure, and the body contact region includes a fourth doped region of a first conductivity type.

7. The electrostatic discharge protection device structure according to claim 6, characterized in that, A shallow groove isolation structure is provided between the source region and the body contact region.

8. The electrostatic discharge protection device structure according to claim 1, characterized in that, The source region is connected to the gate structure and connected to a reference ground.

9. The electrostatic discharge protection device structure according to any one of claims 1 to 8, characterized in that, The electrostatic discharge protection device structure includes a gate-grounded metal-oxide-semiconductor field-effect transistor structure.

10. A microprocessor chip, characterized in that, The microprocessor chip includes the electrostatic discharge protection device structure as described in any one of claims 1 to 9.

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