Semiconductor device including a gate electrode and method of manufacturing the semiconductor device

Abstract

A semiconductor device including gate electrodes and a method of manufacturing the same. The semiconductor device can include first source / drain patterns on a substrate, extending in a first direction and spaced apart from each other in a second direction; a first gate electrode between the first source / drain patterns; a first active pattern penetrating the first gate electrode in the second direction and connected with the first source / drain patterns; second source / drain patterns spaced apart from the first source / drain patterns in a third direction; a second gate electrode between the second source / drain patterns and spaced apart from the first gate electrode in the third direction; and a second active pattern connected with the second source / drain patterns and penetrating the second gate electrode in the second direction. First side surfaces of the first gate electrode in the third direction and second side surfaces of the second gate electrode in the third direction can each include facets.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2025-0053894, filed with the Korean Intellectual Property Office on April 24, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The example embodiments relate to a semiconductor device and / or a method of manufacturing the semiconductor device. Background Technology

[0004] As one of the scaling techniques to increase the density of integrated circuit devices, multi-gate transistors have been proposed, which form fin-shaped or nanowire-shaped silicon bodies on a substrate and form gates on the surface of the silicon bodies.

[0005] Meanwhile, as semiconductor devices become more highly integrated, structures that separate adjacent gates may become necessary. As design rules for semiconductor devices become more restrictive, the manufacturing process for creating gate-separated structures may become more complex. Summary of the Invention

[0006] On the one hand, it provides a highly integrated semiconductor device.

[0007] On the other hand, a semiconductor device that can improve reliability is provided.

[0008] On the other hand, it provides a method for manufacturing semiconductor devices that can reduce the difficulty of manufacturing processes.

[0009] The technical tasks achieved by this example embodiment are not limited to the technical tasks described above, and those skilled in the art can infer other technical tasks from the following embodiments.

[0010] According to one aspect, a semiconductor device may include: a plurality of first source / drain patterns on a substrate, the plurality of first source / drain patterns extending in a first direction and spaced apart from each other in a second direction, the first direction intersecting an upper surface of the substrate, and the second direction intersecting the first direction; a first gate electrode located between the plurality of first source / drain patterns; a first active pattern penetrating the first gate electrode in the second direction, the first active pattern being connected to the plurality of first source / drain patterns; a plurality of second source / drain patterns spaced apart from the plurality of first source / drain patterns in a third direction, the third direction intersecting the first direction and the second direction; a second gate electrode spaced apart from the first gate electrode in the third direction, the second gate electrode being located between the plurality of second source / drain patterns in the second direction; and a second active pattern penetrating the second gate electrode in the second direction, the second active pattern being connected to the plurality of second source / drain patterns, wherein both the first side surface of the first gate electrode in the third direction and the second side surface of the second gate electrode in the third direction may include facets.

[0011] According to another aspect, a semiconductor device may include: a first active pattern located above a substrate in a first direction, the first direction intersecting an upper surface of the substrate, the first active pattern extending in a second direction, the second direction intersecting the first direction; a first gate electrode surrounding at least a portion of the first active pattern; a second active pattern located above the substrate in the first direction, the second active pattern being spaced apart from the first active pattern in a third direction, the third direction intersecting the first and second directions; a second gate electrode being spaced apart from the first gate electrode in a third direction and surrounding at least a portion of the second active pattern; and a gate separation structure located between the first gate electrode and the second gate electrode in a third direction, wherein the first active pattern... A gate electrode may include a first lower pattern and a first upper pattern on the first lower pattern. The first lower pattern may surround a first active pattern and may protrude outward from the center of the first active pattern in a third direction. The width of the first upper pattern in the third direction may increase as the first upper pattern moves away from the first lower pattern in a first direction. A second gate electrode may include a second lower pattern and a second upper pattern on the second lower pattern. The second lower pattern may surround a second active pattern and may protrude outward from the center of the second active pattern in a third direction. The width of the second upper pattern in the third direction may increase as the second upper pattern moves away from the second lower pattern in a first direction.

[0012] According to another aspect, a semiconductor device may include: a plurality of first source / drain patterns on a substrate, the plurality of first source / drain patterns extending in a first direction and spaced apart from each other in a second direction, the first direction intersecting an upper surface of the substrate and the second direction intersecting the first direction; a first gate electrode located between the plurality of first source / drain patterns in the second direction; a first gate insulating film surrounding a lower surface and a side surface of the first gate electrode; a first active pattern penetrating the first gate electrode in the second direction, the first active pattern being connected to the plurality of first source / drain patterns; and a plurality of second source / drain patterns in a third direction. The first gate electrode is spaced apart from a plurality of first source / drain patterns and intersects the first and second directions in a third direction; the second gate electrode is spaced apart from the first gate electrode in a third direction and is located between the plurality of second source / drain patterns in a second direction; the second gate insulating film surrounds the lower surface of the second gate electrode and the side surface of the second gate electrode; and the second active pattern penetrates the second gate electrode in a second direction and is connected to the plurality of second source / drain patterns, wherein the first side surface of the first gate electrode in a third direction and the second side surface of the second gate electrode in a third direction can both include facets having a (100) crystal plane.

[0013] According to another aspect, a method of manufacturing a semiconductor device may include: alternately stacking a first sacrificial film and a first active pattern on a substrate in a first direction to provide a plurality of first sacrificial films and a plurality of first active patterns alternately stacked on the substrate, the first direction intersecting an upper surface of the substrate; forming a plurality of first source / drain patterns, the plurality of first source / drain patterns being connected to the plurality of first sacrificial films and the plurality of first active patterns in a second direction, the second direction intersecting the first direction, the plurality of first source / drain patterns being spaced apart from each other in the second direction; forming a first epitaxial pattern surrounding the plurality of first sacrificial films and the plurality of first active patterns between the plurality of first source / drain patterns; forming an interlayer insulating film covering the first epitaxial pattern; forming a first gate electrode trench in the interlayer insulating film by removing the first epitaxial pattern and the plurality of first sacrificial films, and forming a first gate insulating film and a first gate electrode in the first gate electrode trench.

[0014] Specific details of other example embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0015] These and / or other aspects, features, and advantages of the present invention will become more apparent and readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a diagram illustrating a schematic layout of a semiconductor device according to an example embodiment;

[0017] Figure 2 It shows along Figure 1 A diagram of the cross section intercepted by line A-A' in the diagram;

[0018] Figure 3 It shows along Figure 1 A diagram of the cross section intercepted by line B-B' in the diagram;

[0019] Figure 4 It shows Figure 3 An enlarged view of part A in the image;

[0020] Figure 5 It shows along Figure 1 A diagram of the cross section intercepted by line C-C' in the diagram;

[0021] Figures 6 to 9 It is along Figure 1 The cross-sectional view taken by line B-B' in the figure is used to illustrate the semiconductor device according to the example embodiment;

[0022] Figure 10 It is along Figure 1 The cross-sectional view taken by line A-A' in the figure is used to illustrate the semiconductor device according to the example embodiment;

[0023] Figure 11It shows along Figure 1 A cross-sectional view taken by line B-B' in the diagram is used to illustrate a semiconductor device according to an example embodiment;

[0024] Figure 12 It is along Figure 1 The cross-sectional view taken by line B-B' in the figure is used to illustrate the semiconductor device according to the example embodiment;

[0025] Figures 13 to 34 This illustrates a manufacturing process according to an example embodiment. Figure 2 and Figure 3 A diagram illustrating intermediate operations of the method using the semiconductor device; and

[0026] Figures 35 to 45 This illustrates a manufacturing process according to an example embodiment. Figure 9 A diagram illustrating intermediate operations of a method for using a semiconductor device. Detailed Implementation

[0027] In the detailed description of this disclosure, the terms or words used in the specification and claims should not be construed as limited to their ordinary or dictionary meanings. Furthermore, terms or words should be interpreted in a meaning and concept consistent with the technical spirit of this disclosure, based on the principle that the inventor can appropriately define the concepts of terms in order to best interpret embodiments of the inventive concept. The exemplary embodiments described in this specification and the configurations shown in the accompanying drawings are merely embodiments presented in this disclosure and do not necessarily represent all the technical ideas of this disclosure. Accordingly, various equivalents and modifications may exist at the time of filing this disclosure.

[0028] In the following description, unless the context clearly specifies otherwise, singular expressions include plural expressions. It will be understood that when an element (e.g., a first element) is "(operably or communicatively) coupled to" or "connected to" another element (e.g., a second element), the element may be directly coupled to the other element, or there may be an intermediate element (e.g., a third element) between the element and the other element. The terms "have," "may have," "comprise," and "may include," as used herein, indicate the presence of a corresponding feature (e.g., an element such as a number, function, operation, or component) and do not exclude the presence of other features.

[0029] In this disclosure, the terms "first," "second," etc., can be used to describe various components. However, components are not limited by these terms, and these terms can be used to distinguish between individual components. Within the scope of the technical concept of this disclosure, a first component can be named a second component. Similarly, a second component can be named a first component. Furthermore, for clarity, the shape and size of the components may be exaggerated.

[0030] Furthermore, in the following description, terms such as top, top, bottom, side, front, and back are based on the orientation shown in the figures. If the orientation of the object changes, it may be described differently. For clarity, the shapes and dimensions of the elements in the figures may be exaggerated.

[0031] Regarding semiconductor devices according to some example embodiments, the accompanying drawings illustrate fin transistors (FinFETs) including channel regions in the shape of fin patterns, transistors including nanowires or nanosheets, and multi-bridge channel field-effect transistors (MBCFETs). However, this disclosure is not limited thereto.

[0032] According to some example embodiments, the semiconductor device may include a tunneling transistor (tunneling FET), a three-dimensional (3D) transistor, or a vertical transistor (vertical FET). According to some example embodiments, the semiconductor device may obviously include a planar transistor. Furthermore, the technical ideas of this disclosure can be applied to transistors based on two-dimensional (2D) materials (2D material-based FETs) and their heterostructures. Additionally, according to some example embodiments, the semiconductor device may include a bipolar junction transistor, a lateral double-diffused transistor (LDMOS), etc.

[0033] The following describes exemplary embodiments based on the technical concept of this disclosure with reference to the accompanying drawings.

[0034] Figure 1 This is a diagram illustrating a schematic layout of a semiconductor device according to an example embodiment. Figure 2 It shows along Figure 1 The diagram shows the cross section taken by line A-A' in the diagram. Figure 3 It shows along Figure 1 The diagram shows the cross section taken by line B-B' in the diagram. Figure 4 It shows Figure 3 The image is an enlarged view of part A in the image. Figure 5 It shows along Figure 1 The diagram shows the cross section taken by line C-C' in the figure.

[0035] Reference Figures 1 to 5 According to some example embodiments, a semiconductor device may include a substrate 100, a first active pattern AP1, a second active pattern AP2, a first gate electrode 120, a second gate electrode 220, a first source / drain pattern 150, a second source / drain pattern 250, and a gate-separated structure GC.

[0036] According to some example embodiments, substrate 100 may include a first active region AR1, a second active region AR2, and a field region FR. Each of the first active region AR1, the second active region AR2, and the field region FR may extend in a second direction D2. The first active region AR1, the second active region AR2, and the field region FR may be alternately arranged in a third direction D3. For example, the first active region AR1 may be disposed between the field regions FR in the third direction D3. The field region FR may be disposed between the first active region AR1 and the second active region AR2 in the third direction D3. Here, each of the second direction D2 and the third direction D3 may refer to a direction parallel to substrate 100 and intersecting with the first direction D1. The first direction D1 may refer to a direction intersecting with the surface of substrate 100. For example, the first direction D1 may refer to a direction intersecting with the upper surface of substrate 100. The second direction D2 may refer to the direction in which the first active region AR1, the second active region AR2, and the field region FR extend. The third direction D3 can refer to the direction in which the first active region AR1, the field region FR, and the second active region AR2 are alternately set.

[0037] According to some example embodiments, the field region FR may be defined by trenches, but is not limited thereto. Furthermore, those skilled in the art can distinguish which portions are field regions and which portions are active regions. The field region FR may have a shallow trench isolation (STI) structure. However, the example embodiments are not limited thereto. For example, in some embodiments, the field region FR may be defined by deep trenches.

[0038] According to some example embodiments, a device isolation film can be disposed around a first active region AR1 and a second active region AR2 that are spaced apart from each other. Here, the portion of the device isolation film between adjacent first active regions AR1 and second active regions AR2 can serve as a field region FR. For example, the portion where a channel region of a transistor, as an example of a semiconductor device, is formed can serve as an active region, and the portion separating the channel region of the transistor formed in the active region can serve as a field region. Alternatively, the active region can be a portion with fin patterns or nanosheets formed, serving as the channel region of the transistor, and the field region can be a region without fin patterns or nanosheets formed, serving as the channel region.

[0039] According to some example embodiments, substrate 100 may be a semiconductor or a semiconductor-on-insulator. For example, substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide. However, substrate 100 is not limited thereto.

[0040] According to some example embodiments, substrate 100 may include an insulating material. For example, substrate 100 may include at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), and silicon carbonitride oxycarbide (SiOCN).

[0041] Figure 2 , Figure 3 and Figure 5 A substrate 100 is shown disposed below the first fin pattern 101 and the second fin pattern 102, but the exemplary embodiments are not limited thereto. For example, the substrate 100 may not be disposed below the first fin pattern 101 and the second fin pattern 102. In the process of manufacturing a semiconductor device according to some exemplary embodiments, the substrate 100 located below the first fin pattern 101 and the second fin pattern 102 may be removed. In another exemplary embodiment, the first fin pattern 101 and the substrate 100 may not be disposed below the first gate electrode 120 and the first source / drain pattern 150, and the second fin pattern 102 and the substrate 100 may not be disposed below the second gate electrode 220 and the second source / drain pattern 250. In the process of manufacturing a semiconductor device according to some exemplary embodiments, the first fin pattern 101, the second fin pattern 102, and the substrate 100 disposed below the first gate electrode 120, the first source / drain pattern 150, the second gate electrode 220, and the second source / drain pattern 250 may be removed, and an interlayer insulating film may be formed.

[0042] According to some example embodiments, a first fin pattern 101 may be disposed on a first active region AR1 of the substrate 100. A second fin pattern 102 may be disposed on a second active region AR2 of the substrate 100. Each of the first fin pattern 101 and the second fin pattern 102 may protrude from the substrate 100. Each of the first fin pattern 101 and the second fin pattern 102 may extend along a second direction D2. Each of the first fin pattern 101 and the second fin pattern 102 may be formed by etching a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100.

[0043] According to some example embodiments, each of the first fin pattern 101 and the second fin pattern 102 may include silicon (Si). In another example embodiment, each of the first fin pattern 101 and the second fin pattern 102 may include a compound semiconductor. For example, each of the first fin pattern 101 and the second fin pattern 102 may include a group IV-IV compound semiconductor or a group III-V compound semiconductor. For example, a group IV-IV compound semiconductor may be a binary compound, a ternary compound comprising at least two elements selected from carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a group IV element. For example, a group III-V compound semiconductor may be a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb). For example, each of the first fin pattern 101 and the second fin pattern 102 may include a semiconductor material. The first fin pattern 101 and the second fin pattern 102 may include one of the elemental semiconductor materials: silicon or germanium, group IV-IV compound semiconductor, or group III-V compound semiconductor.

[0044] According to some example embodiments, each of the first fin pattern 101 and the second fin pattern 102 may include an insulating material. For example, each of the first fin pattern 101 and the second fin pattern 102 may include at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonate (SiOC), and silicon carbonitride (SiOCN).

[0045] According to some example embodiments, a first active pattern AP1 may be disposed on a first active region AR1 of substrate 100. The first active pattern AP1 may be disposed on a first fin pattern 101. For example, the first active pattern AP1 may be an active pattern comprising nanosheets or nanowires. The first active pattern AP1 may include a plurality of first sheets. The plurality of first sheets may be disposed on substrate 100. The plurality of first sheets may be spaced apart from substrate 100 in a first direction D1. The plurality of first sheets may be spaced apart from each other in the first direction D1. The plurality of first sheets may extend along a second direction D2.

[0046] According to some example embodiments, the first active pattern AP1 may include a first inner AP1_ISS and a first outer AP1_OSS spaced apart on the third direction D3. The first inner AP1_ISS may face the second active pattern AP2 on the third direction D3. The first outer AP1_OSS may be disposed on the third direction D3 on the side opposite to the first inner AP1_ISS.

[0047] According to some example embodiments, a plurality of first active patterns AP1 can be provided. The plurality of first active patterns AP1 can be configured to be spaced apart in the second direction D2. For example, the plurality of first active patterns AP1 can be configured to be spaced apart from each other in the second direction D2 in a first active region AR1 extending along the second direction D2.

[0048] According to some example embodiments, a first active pattern AP1 may be disposed between the first source / drain patterns 150 in the second direction D2. The first active pattern AP1 may be connected to the first source / drain patterns 150 in the second direction D2. The first active pattern AP1 may extend along the second direction D2 and penetrate the first gate electrode 120. The first active pattern AP1 may be surrounded by the first gate electrode 120.

[0049] According to some example embodiments, a second active pattern AP2 may be disposed on a second active region AR2 of substrate 100. The second active pattern AP2 may be disposed on a second fin pattern 102. For example, the second active pattern AP2 may be an active pattern comprising nanosheets or nanowires. The second active pattern AP2 may include a plurality of second sheets. The plurality of second sheets may be disposed on substrate 100. The plurality of second sheets may be spaced apart from substrate 100 in a first direction D1. The plurality of second sheets may be spaced apart from each other in the first direction D1. The plurality of second sheets may extend along a second direction D2.

[0050] According to some example embodiments, the second active pattern AP2 may include a second inner AP2_ISS and a second outer AP2_OSS spaced apart on the third-direction D3. The second inner AP2_ISS may face the first active pattern AP1 on the third-direction D3. The second outer AP2_OSS may be disposed on the third-direction D3 on the side opposite to the second inner AP2_ISS.

[0051] According to some example embodiments, a plurality of second active patterns AP2 can be provided. The plurality of second active patterns AP2 can be configured to be spaced apart in the second direction D2. For example, the plurality of second active patterns AP2 can be configured to be spaced apart in the second direction D2 in a second active region AR2 extending along the second direction D2.

[0052] According to some example embodiments, a second active pattern AP2 may be disposed between the second source / drain patterns 250 in the second direction D2. The second active pattern AP2 may be connected to the second source / drain patterns 250 in the second direction D2. The second active pattern AP2 may extend along the second direction D2 and penetrate the second gate electrode 220. The second active pattern AP2 may be surrounded by the second gate electrode 220.

[0053] For example, the width of the plurality of first pieces of the first active pattern AP1 in the third direction D3 can be increased or decreased proportionally to the width of the first fin pattern 101 disposed at the lower part of the first active pattern AP1 in the third direction D3. The width of the plurality of second pieces of the second active pattern AP2 in the third direction D3 can be increased or decreased proportionally to the width of the second fin pattern 102 disposed at the lower part of the second active pattern AP2 in the third direction D3.

[0054] According to some example embodiments, the first active pattern AP1 and the second active pattern AP2 may be configured to be spaced apart on the third-direction D3. The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other on the third-direction D3, and the gate separation structure GC is located between the first active pattern AP1 and the second active pattern AP2.

[0055] According to some example embodiments, the first active pattern AP1 and the second active pattern AP2 may include, for example, elemental semiconductor materials, such as silicon or germanium. Furthermore, the first active pattern AP1 and the second active pattern AP2 may include compound semiconductors, and may include, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0056] IV-IV compound semiconductors can be binary compounds, ternary compounds, or compounds doped with group IV elements, including at least two of the elements carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0057] III-V compound semiconductors can be, for example, group III elements, and can be a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) with one of group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0058] According to some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may include the same material as the first fin pattern 101 and the second fin pattern 102, and may also include a different material than the first fin pattern 101 and the second fin pattern 102. The first fin pattern 101 and the second fin pattern 102 may be silicon fin patterns containing silicon, and the first active pattern AP1 and the second active pattern AP2 may be silicon wafer patterns containing silicon. Each of the first active pattern AP1 and the second active pattern AP2 may not contain P-type or N-type impurities. The first active pattern AP1 and the second active pattern AP2 may contain only silicon.

[0059] Figure 2 and Figure 3The semiconductor device of this disclosure is illustrated by each of a first active pattern AP1 comprising four first wafers and a second active pattern AP2 comprising four second wafers. However, this disclosure is not limited thereto. It is apparent that the semiconductor device of this disclosure can comprise a fin-type transistor (FinFET) by including only the first active pattern AP1 and the second active pattern AP2 comprising fin-shaped patterns extending along the second direction D2 and projecting from the substrate 100 in the first direction D1, without the first active pattern AP1 and the second active pattern AP2 excluding the nanosheets.

[0060] According to some example embodiments, a device isolation film 105 may be disposed in the field region FR. The device isolation film 105 may be disposed on the substrate 100. The device isolation film 105 may be disposed at the bottom of the gate separation structure GC. For example, the device isolation film 105 may be disposed between a first fin pattern 101 and a second fin pattern 102 spaced apart in a third direction D3. The device isolation film 105 may be disposed on the substrate 100 such that the first active pattern AP1 and the second active pattern AP2 do not overlap in a first direction D1. The device isolation film 105 may be disposed between the first active pattern AP1 and the second active pattern AP2 in a third direction D3. The device isolation film 105 may fill at least a portion of a trench formed on the substrate 100.

[0061] According to some example embodiments, the device isolation film 105 may cover the side surfaces of the first fin pattern 101 and the second fin pattern 102. The upper surface of the device isolation film 105 may be configured to be lower than the upper surfaces of the first fin pattern 101 and the second fin pattern 102. Contrary to what is shown, the upper surface of the device isolation film 105 may be disposed on the same plane as the upper surfaces of the first fin pattern 101 and the second fin pattern 102. The device isolation film 105 may cover only a portion of the side surfaces of the first fin pattern 101 and the second fin pattern 102. In this case, a portion of the first fin pattern 101 and the second fin pattern 102 may protrude beyond the device isolation film 105 in the first direction D1. For example, the device isolation film 105 may comprise an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the device isolation film 105 is depicted as a single-layer film, this is for ease of explanation only, and the device isolation film 105 is not limited thereto.

[0062] According to some example embodiments, the first gate electrode 120 may be disposed on the first active region AR1 of the substrate 100. The first gate electrode 120 may be disposed on the first fin pattern 101. The first gate electrodes 120 may be configured to be spaced apart on the first active region AR1 of the substrate 100 in a second direction D2.

[0063] According to some example embodiments, the first gate electrode 120 may be disposed between first source / drain patterns 150 that are adjacent to each other in the second direction D2. In the second direction D2, the first gate electrode 120 may be disposed on both sides of the first source / drain pattern 150. In example embodiments, the first gate electrodes 120 disposed on both sides of the first source / drain pattern 150 may both be ordinary gate electrodes used as gates of transistors. In another example embodiment, even if the first gate electrode 120 located on one side of the first source / drain pattern 150 is used as a gate of a transistor, the first gate electrode 120 disposed on the other side of the first source / drain pattern 150 may be a dummy gate electrode.

[0064] According to some example embodiments, the first gate electrode 120 can be penetrated by a first active pattern AP1 extending along a second direction D2. The first gate electrode 120 can surround the first active pattern AP1. The first gate electrode 120 can surround at least a portion of the first active pattern AP1. For example, the first gate electrode 120 can surround the outer surface of the first active pattern AP1, except for the side surface of the first active pattern AP1 connected to the first source / drain pattern 150. The first gate electrode 120 can surround a plurality of first sheets of the first active pattern AP1.

[0065] According to some example embodiments, a portion of the first gate electrode 120 may be disposed between a plurality of first sheets of adjacent first active patterns AP1 in the first direction D1. A portion of the first gate electrode 120 may be disposed on the top first sheet among the plurality of first sheets of the first active patterns AP1.

[0066] According to some example embodiments, the first gate electrode 120 may include a first lower pattern 120B and a first upper pattern 120U. The first lower pattern 120B and the first upper pattern 120U may be connected in a first direction D1. The first lower pattern 120B may be disposed on the first fin pattern 101. The first upper pattern 120U may be disposed on the first lower pattern 120B.

[0067] According to some example embodiments, a first lower pattern 120B may surround a first active pattern AP1. The first lower pattern 120B may project outwards in a third direction D3 based on the center of the first active pattern AP1. For example, the side surfaces of the first lower pattern 120B in the third direction D3 may have a raised profile relative to the side surfaces of the first active pattern AP1 in the third direction D3 (first inner AP1_ISS, first outer AP1_OSS). As the first lower pattern 120B moves away from the substrate 100, the width of the first lower pattern 120B along the third direction D3 may increase in a first direction D1 and then decrease again.

[0068] According to some example embodiments, the first upper pattern 120U may penetrate at least a portion of the second interlayer insulating film 192. As the first upper pattern 120U moves away from the first lower pattern 120B in the first direction D1, the first upper pattern 120U may have a width that increases in the third direction D3.

[0069] According to some example embodiments, the first side surface 120SS of the first gate electrode 120 on the third direction D3 may include facets. Specifically, the side surface of the first lower pattern 120B on the third direction D3 may include facets. The first side surface 120SS may refer to the side surfaces of the first gate electrode 120 on the third direction D3 that are spaced apart. For example, the first side surface 120SS may include the side of the first gate electrode 120 on the third direction D3 facing the second gate electrode 220, and may include the other side of the first gate electrode 120 on the third direction D3 disposed on the side opposite to that side of the first gate electrode 120.

[0070] According to some example embodiments, at least a portion of the facets of the first side surface 120SS of the first gate electrode 120 may be aligned with a crystal plane of the substrate 100. Alignment of at least a portion of the facets of the first side surface 120SS of the first gate electrode 120 with a crystal plane of the substrate 100 may indicate that at least a portion of the facets of the first side surface 120SS of the first gate electrode 120 matches the crystal plane orientation of the substrate 100. For example, when the substrate 100 has a (110) crystal plane or a (100) crystal plane, and when the notch of the substrate 100 has a

[100] crystal orientation, at least a portion of the facets of the first side surface 120SS of the first gate electrode 120 may be aligned with a (100) crystal plane. In another example embodiment, when the substrate 100 has a (100) crystal plane and the notch of the substrate 100 has a

[110] crystal orientation, at least a portion of the facets of the first side surface 120SS of the first gate electrode 120 may be aligned with a (111) crystal plane. At least a portion of the facet region of the first side surface 120SS of the first gate electrode 120 may be aligned with the crystal faces of a plurality of first source / drain patterns 150 or a plurality of second source / drain patterns 250.

[0071] According to some example embodiments, the first side surface 120SS may include a first sub-side surface 120SS1, a second sub-side surface 120SS2, a third sub-side surface 120SS3, and a fourth sub-side surface 120SS4. The first sub-side surface 120SS1, the second sub-side surface 120SS2, and the third sub-side surface 120SS3 may be facets of a first lower pattern 120B. The fourth sub-side surface 120SS4 may be a side surface of a first upper pattern 120U. The first sub-side surface 120SS1, the second sub-side surface 120SS2, the third sub-side surface 120SS3, and the fourth sub-side surface 120SS4 may be connected to each other.

[0072] According to some example embodiments, a first sub-side surface 120SS1 of the first side surface 120SS may be connected to the lower surface of the first lower pattern 120B. The first sub-side surface 120SS1 of the first side surface 120SS may be a bottom facet of the first side surface 120SS. The first sub-side surface 120SS1 of the first side surface 120SS may be a facet such that, as the facet moves away from the first fin pattern 101 in a first direction D1, the facet moves away from the first active pattern AP1 in a third direction D3. For example, the first sub-side surface 120SS1 of the first side surface 120SS may be aligned with the (111) crystal plane.

[0073] According to some example embodiments, a second sub-side surface 120SS2 of the first side surface 120SS can be connected to the first sub-side surface 120SS1 of the first side surface 120SS. The second sub-side surface 120SS2 of the first side surface 120SS can be a facet such that as the facet moves away from the first fin pattern 101 in the first direction D1, the distance of the facet from the first active pattern AP1 in the third direction D3 remains unchanged. For example, the second sub-side surface 120SS2 of the first side surface 120SS can be aligned with the (100) crystal plane. The second sub-side surface 120SS2 of the first side surface 120SS can be parallel to the first direction D1.

[0074] According to some example embodiments, a third sub-side surface 120SS3 of the first side surface 120SS can be connected to a second sub-side surface 120SS2 of the first side surface 120SS. The third sub-side surface 120SS3 of the first side surface 120SS can be a facet such that, as the facet moves away from the first fin pattern 101 in a first direction D1, the facet moves closer to the first active pattern AP1 in a third direction D3. For example, the third sub-side surface 120SS3 of the first side surface 120SS can be aligned with the (111) crystal plane.

[0075] According to some example embodiments, a fourth sub-side surface 120SS4 of the first side surface 120SS may be connected to a third sub-side surface 120SS3 of the first side surface 120SS. The fourth sub-side surface 120SS4 of the first side surface 120SS may be a top facet of the first side surface 120SS. The fourth sub-side surface 120SS4 of the first side surface 120SS may be a facet such that, as the facet moves away from the first fin pattern 101 in the first direction D1, the facet moves closer to the second gate electrode 220 in the third direction D3.

[0076] According to some example embodiments, the first gate electrode 120 may have a symmetrical structure relative to the center of the first active pattern AP1 in the third direction D3. For example, the thickness TH120a of the portion of the first gate electrode 120 disposed on the first outer AP1_OSS in the third direction D3 and the thickness TH120b of the portion of the first gate electrode 120 disposed on the first inner AP1_ISS in the third direction D3 may be the same. The thickness TH120a of the portion of the first gate electrode 120 disposed on the first outer AP1_OSS in the third direction D3 may be the thickness of the first gate electrode 120 based on the thickest portion of the first outer AP1_OSS in the third direction D3. The thickness TH120b of the portion of the first gate electrode 120 disposed on the first inner AP1_ISS in the third direction D3 may be the thickness of the first gate electrode 120 based on the thickest portion of the first inner AP1_ISS in the third direction D3. The distance in the third direction D3 between the first side surface 120SS and the first outer AP1_OSS located on the opposite side of the second gate electrode 220 can be equal to the distance in the third direction D3 between the first side surface 120SS and the first inner AP1_ISS facing the second gate electrode 220.

[0077] According to some example embodiments, the second gate electrode 220 may be disposed on the second active region AR2 of the substrate 100. The second gate electrode 220 may be disposed on the second fin pattern 102. The second gate electrodes 220 may be configured to be spaced apart on the second active region AR2 of the substrate 100 in the second direction D2.

[0078] According to some example embodiments, the second gate electrode 220 may be disposed between adjacent second source / drain patterns 250 in the second direction D2. In the second direction D2, the second gate electrode 220 may be disposed on both sides of the second source / drain pattern 250. In example embodiments, the second gate electrodes 220 disposed on both sides of the second source / drain pattern 250 may both be ordinary gate electrodes used as gates of transistors. In another example embodiment, even if the second gate electrode 220 located on one side of the second source / drain pattern 250 is used as a gate of a transistor, the second gate electrode 220 disposed on the other side of the second source / drain pattern 250 may be a dummy gate electrode.

[0079] According to some example embodiments, a second active pattern AP2 extending along a second direction D2 can penetrate the second gate electrode 220. The second gate electrode 220 can surround the second active pattern AP2. The second gate electrode 220 can surround at least a portion of the second active pattern AP2. For example, the second gate electrode 220 can surround the outer surface of the second active pattern AP2, except for the side surface of the second active pattern AP2 connected to the second source / drain pattern 250. The second gate electrode 220 can surround a plurality of second sheets of the second active pattern AP2.

[0080] According to some example embodiments, a portion of the second gate electrode 220 may be disposed between a plurality of second sheets of adjacent second active patterns AP2 in the first direction D1. A portion of the second gate electrode 220 may be disposed on the top second sheet among the plurality of second sheets of the second active patterns AP2.

[0081] According to some example embodiments, the second gate electrode 220 may include a second lower pattern 220B and a second upper pattern 220U. The second lower pattern 220B and the second upper pattern 220U may be connected in a first direction D1. The second lower pattern 220B may be disposed on the second fin pattern 102. The second upper pattern 220U may be disposed on the second lower pattern 220B.

[0082] According to some example embodiments, the second lower pattern 220B may surround the second active pattern AP2. The second lower pattern 220B may protrude outward in a third direction D3 based on the center of the second active pattern AP2. For example, the side surface of the second lower pattern 220B in the third direction D3 may have a raised profile relative to the side surface of the second active pattern AP2 in the third direction D3 (second inner AP2_ISS, second outer AP2_OSS). As the second lower pattern 220B moves away from the substrate 100 in the first direction D1, the width of the second lower pattern 220B in the third direction D3 may increase and then decrease again.

[0083] According to some example embodiments, the second upper pattern 220U can penetrate at least a portion of the second interlayer insulating film 192. As the second upper pattern 220U moves away from the second lower pattern 220B in the first direction D1, the second upper pattern 220U can have a width that increases in the third direction D3.

[0084] According to some example embodiments, the second side surface 220SS of the second gate electrode 220 on the third direction D3 may include facets. Specifically, the side surface of the second lower pattern 220B on the third direction D3 may include facets. The second side surface 220SS may refer to the side surfaces of the second gate electrode 220 on the third direction D3 that are spaced apart. For example, the second side surface 220SS may include the side of the second gate electrode 220 on the third direction D3 facing the first gate electrode 120, and may include the other side of the second gate electrode 220 on the third direction D3 disposed on the side opposite to that side of the second gate electrode 220.

[0085] According to some example embodiments, at least a portion of the facets of the second side surface 220SS of the second gate electrode 220 may align with a crystal plane of the substrate 100. For example, when the substrate 100 has a (110) crystal plane or a (100) crystal plane, and the notch of the substrate 100 has a

[100] crystal orientation, at least a portion of the facets of the second side surface 220SS of the second gate electrode 220 may align with the (100) crystal plane. In another example embodiment, when the substrate 100 has a (100) crystal plane and the notch of the substrate 100 has a

[110] crystal orientation, at least a portion of the facets of the second side surface 220SS of the second gate electrode 220 may align with the (111) crystal plane. At least a portion of the facets of the second side surface 220SS of the second gate electrode 220 may align with the crystal planes of a plurality of first source / drain patterns 150 or a plurality of second source / drain patterns 250.

[0086] According to some example embodiments, the second side surface 220SS may include a fifth sub-side surface 220SS1, a sixth sub-side surface 220SS2, a seventh sub-side surface 220SS3, and an eighth sub-side surface 220SS4. The fifth sub-side surface 220SS1, the sixth sub-side surface 220SS2, and the seventh sub-side surface 220SS3 may be facets of the second lower pattern 220B. The eighth sub-side surface 220SS4 may be a side surface of the second upper pattern 220U. The fifth sub-side surface 220SS1, the sixth sub-side surface 220SS2, the seventh sub-side surface 220SS3, and the eighth sub-side surface 220SS4 may be connected to each other.

[0087] According to some example embodiments, the fifth sub-side surface 220SS1 of the second side surface 220SS can be connected to the lower surface of the second lower pattern 220B. The fifth sub-side surface 220SS1 of the second side surface 220SS can be the bottom facet of the second side surface 220SS. The fifth sub-side surface 220SS1 of the second side surface 220SS can be a facet that, as it moves away from the second fin pattern 102 in the first direction D1, moves away from the second active pattern AP2 in the third direction D3. For example, the fifth sub-side surface 220SS1 of the second side surface 220SS can be aligned with the (111) crystal plane.

[0088] According to some example embodiments, the sixth sub-side surface 220SS2 of the second side surface 220SS can be connected to the fifth sub-side surface 220SS1 of the second side surface 220SS. The sixth sub-side surface 220SS2 of the second side surface 220SS can be a facet such that as the facet moves away from the second fin pattern 102 in the first direction D1, the distance of the facet from the second active pattern AP2 in the third direction D3 remains unchanged. For example, the sixth sub-side surface 220SS2 of the second side surface 220SS can be aligned with the (100) crystal plane. The sixth sub-side surface 220SS2 of the second side surface 220SS can be parallel to the first direction D1.

[0089] According to some example embodiments, the seventh sub-side surface 220SS3 of the second side surface 220SS can be connected to the sixth sub-side surface 220SS2 of the second side surface 220SS. The seventh sub-side surface 220SS3 of the second side surface 220SS can be faceted such that, as the facet moves away from the second fin pattern 102 in the first direction D1, the facet moves closer to the second active pattern AP2 in the third direction D3. For example, the seventh sub-side surface 220SS3 of the second side surface 220SS can be aligned with the (111) crystal plane.

[0090] According to some example embodiments, the eighth sub-side surface 220SS4 of the second side surface 220SS can be connected to the seventh sub-side surface 220SS3 of the second side surface 220SS. The eighth sub-side surface 220SS4 of the second side surface 220SS can be the top facet of the second side surface 220SS. The eighth sub-side surface 220SS4 of the second side surface 220SS can be a facet such that as the facet moves away from the second fin pattern 102 in the first direction D1, the facet moves closer to the first gate electrode 120 in the third direction D3.

[0091] According to some example embodiments, the second gate electrode 220 may have a structure symmetrical about the center of the second active pattern AP2 in the third direction D3. The thickness TH220a of the portion of the second gate electrode 220 disposed on the second outer AP2_OSS in the third direction D3 and the thickness TH220b of the portion of the second gate electrode 220 disposed on the second inner AP2_ISS in the third direction D3 may be the same. The thickness TH220a of the portion of the second gate electrode 220 disposed on the second outer AP2_OSS in the third direction D3 may be the thickness of the second gate electrode 220 based on the thickest portion of the second outer AP2_OSS in the third direction D3. The thickness TH220b of the portion of the second gate electrode 220 disposed on the second inner AP2_ISS in the third direction D3 may be the thickness of the second gate electrode 220 based on the thickest portion of the second inner AP2_ISS in the third direction D3. The distance in the third direction D3 between the second side surface 220SS and the second outer AP2_OSS located on the opposite side of the first gate electrode 120 can be the same as the distance in the third direction D3 between the second side surface 220SS and the second inner AP2_ISS facing the first gate electrode 120.

[0092] According to some example embodiments, the width of the first gate electrode 120 in the third direction D3 can be the same as the width of the second gate electrode 220. The distance between the first side surfaces 120SS in the third direction D3 can be the same as the distance between the second side surfaces 220SS in the third direction D3. The thickness TH220a of the portion of the second gate electrode 220 disposed on the second outer AP2_OSS in the third direction D3 can be the same as the thickness TH120a of the portion of the first gate electrode 120 disposed on the first outer AP1_OSS in the third direction D3. The thickness TH220b of the portion of the second gate electrode 220 disposed on the second inner AP2_ISS in the third direction D3 can be the same as the thickness TH120b of the portion of the first gate electrode 120 disposed on the first inner AP1_ISS in the third direction D3.

[0093] According to some example embodiments, each of the first gate electrode 120 and the second gate electrode 220 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxide nitride. For example, the first gate electrode 120 and the second gate electrode 220 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium carbide (TiC), and tantalum carbonitride (TaCN). At least one of tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. However, the first gate electrode 120 and the second gate electrode 220 are not limited thereto. Conductive metal oxides and conductive metal nitrides may be, but are not limited to, the oxidation forms of the materials described above.

[0094] According to some example embodiments, the first gate insulating film 130 may extend along the upper surface of the first fin pattern 101 and the first side surface 120SS of the first gate electrode 120. The first gate insulating film 130 may extend along the side surface of the first lower pattern 120B, the lower surface of the first lower pattern 120B, and the side surface of the first upper pattern 120U. The first gate insulating film 130 may enclose the first active pattern AP1. The first gate insulating film 130 may surround the first gate electrode 120. The first gate insulating film 130 may be disposed along the periphery of a plurality of first sheets of the first active pattern AP1. The first gate insulating film 130 may be disposed between the first gate electrode 120 and the first active pattern AP1. The first gate insulating film 130 may not contact the device isolation film 105. For example, as... Figures 3 to 4 As shown, a portion of the lower surface of the first gate insulating film 130 may be spaced apart from a portion of the upper surface of the device isolation film 105 below it. The first gate insulating film 130 may extend along the side surface of the gate separation structure GC facing the first gate electrode 120. The first gate insulating film 130 may cover the side surface of the gate separation structure GC facing the first gate electrode 120 in the third direction D3.

[0095] According to some example embodiments, the second gate insulating film 230 may extend along the upper surface of the second fin pattern 102 and the second side surface 220SS of the second gate electrode 220. The second gate insulating film 230 may extend along the side surface of the second lower pattern 220B, the lower surface of the second lower pattern 220B, and the side surface of the second upper pattern 220U. The second gate insulating film 230 may enclose the second active pattern AP2. The second gate insulating film 230 may surround the second gate electrode 220. The second gate insulating film 230 may be disposed along the periphery of a plurality of second sheets of the second active pattern AP2. The second gate insulating film 230 may be disposed between the second gate electrode 220 and the second active pattern AP2. The second gate insulating film 230 may not contact the device isolation film 105. For example, as... Figures 3 to 4 As shown, a portion of the lower surface of the second gate insulating film 230 may be spaced apart from a portion of the upper surface of the device isolation film 105 below it. The second gate insulating film 230 may extend along the side surface of the gate separation structure GC facing the second gate electrode 220. The second gate insulating film 230 may cover the side surface of the gate separation structure GC facing the second gate electrode 220 on the third direction D3.

[0096] According to some example embodiments, the first gate insulating film 130 and the second gate insulating film 230 may not be connected to each other. The first gate insulating film 130 and the second gate insulating film 230 may be spaced apart from each other, and the gate separation structure GC is located between the first gate insulating film 130 and the second gate insulating film 230.

[0097] According to some example embodiments, each of the first gate insulating film 130 and the second gate insulating film 230 may include silicon oxide, silicon germanium oxide, germanium oxide, silicon oxynitride, silicon nitride, or a high-k material with a dielectric constant greater than that of silicon oxide. For example, the high-k material may include one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0098] Figures 2 to 4 The first gate insulating film 130 and the second gate insulating film 230 are shown as single-layer films, but this is only for illustrative purposes and the present disclosure is not limited thereto. Each of the first gate insulating film 130 and the second gate insulating film 230 may include a multilayer film. Each of the first gate insulating film 130 and the second gate insulating film 230 may include: an interface layer disposed between the first active pattern AP1 or the second active pattern AP2 and the first gate electrode 120 or the second gate electrode 220, and a high-k insulating film.

[0099] According to some example embodiments, the semiconductor device may include a negative capacitance (NC) field-effect transistor (FET) using a negative capacitor. For example, the first gate insulating film 130 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0100] According to some example embodiments, ferroelectric material films can have negative capacitance, and paraelectric material films can have positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor is positive, the total capacitance is reduced compared to the capacitance of each individual capacitor. On the other hand, when at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive and greater than the absolute value of each individual capacitor.

[0101] According to some example embodiments, when a ferroelectric material film with negative capacitance is connected in series with a paraelectric material film with positive capacitance, the total capacitance of the series-connected ferroelectric and paraelectric material films can be increased. By utilizing this increased total capacitance, the subthreshold swing (SS) of a transistor incorporating the ferroelectric material film at room temperature can be less than 60 mV / decade.

[0102] According to some example embodiments, the ferroelectric material film can possess ferroelectric properties. For example, the ferroelectric material film may include at least one selected from hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, in an example embodiment, hafnium zirconium oxide may be a material doped with zirconium (Zr) in hafnium oxide. In another example embodiment, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0103] According to some example embodiments, the ferroelectric material film may also include doped dopants. For example, the dopants may include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the ferroelectric material it contains.

[0104] According to some example embodiments, when the ferroelectric material film contains hafnium oxide, the dopants included in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0105] According to some example embodiments, when the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 at% aluminum. Here, the dopant ratio can be the ratio of aluminum to the sum of hafnium and aluminum.

[0106] According to some example embodiments, when the dopant is silicon (Si), the ferroelectric material film may include 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 to 80 at% zirconium.

[0107] According to some example embodiments, the paraelectric material film may have paraelectric properties. For example, the paraelectric material film may include at least one of silicon oxide and a metal oxide having a high k value. For example, the metal oxide included in the paraelectric material film may include at least one of hafnium oxide, zirconium oxide, and aluminum oxide. However, the metal oxide included in the paraelectric material film is not limited to these.

[0108] According to some example embodiments, ferroelectric and paraelectric material films may contain the same material. The ferroelectric material film may possess ferroelectric properties, but the paraelectric material film may not. For example, when both the ferroelectric and paraelectric material films contain hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film differs from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0109] According to some example embodiments, the ferroelectric material film can have a thickness exhibiting ferroelectric properties. The thickness of the ferroelectric material film can be, for example, from 0.5 to 10 nm, but is not limited thereto. The threshold thickness exhibiting ferroelectric properties can vary depending on the ferroelectric material, and therefore the thickness of the ferroelectric material film can vary depending on the ferroelectric material.

[0110] In an example embodiment, each of the first gate insulating film 130 and the second gate insulating film 230 may include a single ferroelectric material film. In another example embodiment, each of the first gate insulating film 130 and the second gate insulating film 230 may include a plurality of ferroelectric material films spaced apart from each other. Each of the first gate insulating film 130 and the second gate insulating film 230 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0111] According to some exemplary embodiments, the gate spacer 140 may be disposed on the side surfaces of the first gate electrode 120 and the second gate electrode 220. The gate spacer 140 may not be disposed between the first fin pattern 101 and the first active pattern AP1, between a plurality of first pieces of adjacent first active patterns AP1 in the first direction D1, between the second fin pattern 102 and the second active pattern AP2, or between a plurality of second pieces of adjacent second active patterns AP2 in the first direction D1. However, the exemplary embodiments are not limited thereto. For example, the gate spacer 140 may be disposed between the first fin pattern 101 and the first active pattern AP1, between a plurality of first pieces of adjacent first active patterns AP1 in the first direction D1, between the second fin pattern 102 and the second active pattern AP2, and between a plurality of second pieces of adjacent second active patterns AP2 in the first direction D1.

[0112] although Figure 2 Only the gate spacer 140 is shown disposed on the side surface of the first gate electrode 120, but... Figure 2 In the cross section taken along the second direction D2 in the second active region AR2 shown, the gate spacer 140 can be disposed on the side surface of the second gate electrode 220.

[0113] According to some example embodiments, the gate spacer 140 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. Although the gate spacer 140 is shown as a single layer, this is only for ease of explanation, and the gate spacer 140 is not limited thereto.

[0114] According to some example embodiments, a gate separation structure GC can be disposed on the third-direction D3 between the first gate electrode 120 and the second gate electrode 220. The gate separation structure GC can be disposed between a first side surface 120SS of the first gate electrode 120 and a second side surface 220SS of the second gate electrode 220, which face each other on the third-direction D3. The gate separation structure GC can be a second interlayer insulating film 192 disposed on the third-direction D3 between the first gate electrode 120 and the second gate electrode 220. The gate separation structure GC can electrically insulate the first gate electrode 120 and the second gate electrode 220. According to the example embodiments, the integration density and reliability of the semiconductor device can be improved.

[0115] According to some exemplary embodiments, a gate separation structure GC can be disposed between the device isolation film 105, the first gate insulating film 130, and the second gate insulating film 230. The lower surface of the gate separation structure GC can contact the device isolation film 105. The gate separation structure GC can contact the upper surface of the device isolation film 105. The side surface of the gate separation structure GC in the third direction D3 can be covered by the first gate insulating film 130 and the second gate insulating film 230. For example, the side surface of the gate separation structure GC facing the first gate electrode 120 in the third direction D3 can be covered by the first gate insulating film 130, and the side surface of the gate separation structure GC facing the second gate electrode 220 in the third direction D3 can be covered by the second gate insulating film 230.

[0116] According to some example embodiments, the gate separation structure GC may include a first portion 192P1, a second portion 192P2, a third portion 192P3, and a fourth portion 192P4. The first portion 192P1, the second portion 192P2, the third portion 192P3, and the fourth portion 192P4 may be connected to each other in a first direction D1. The first portion 192P1, the second portion 192P2, the third portion 192P3, and the fourth portion 192P4 may be sequentially disposed on the device isolation film 105 in the first direction D1.

[0117] According to some example embodiments, the first portion 192P1 may be the lowest region of the gate-separated structure GC. For example, the first portion 192P1 may include the lower surface of the gate-separated structure GC. The first portion 192P1 may be disposed between the lowest facet of the first side surface 120SS and the lowest facet of the second side surface 220SS. The first portion 192P1 may be disposed between the first sub-side surface 120SS1 of the first side surface 120SS and the fifth sub-side surface 220SS1 of the second side surface 220SS. As the first portion 192P1 is located in the third direction D3 between the first gate electrode 120 and the second gate electrode 220, away from the substrate 100 along the first direction D1, the width of the first portion 192P1 in the third direction D3 may be reduced. This may be because the facets of the first sub-side surface 120SS1 of the first side surface 120SS and the facets of the fifth sub-side surface 220SS1 of the second side surface 220SS are inclined to each other.

[0118] According to some example embodiments, the second portion 192P2 may be disposed on the first portion 192P1. The second portion 192P2 may be disposed between the first portion 192P1 and the third portion 192P3 in the first direction D1. The second portion 192P2 may be disposed between the second sub-side surface 120SS2 of the first side surface 120SS and the sixth sub-side surface 220SS2 of the second side surface 220SS. For example, as the second portion 192P2 is located in the third direction D3 between the first gate electrode 120 and the second gate electrode 220, away from the substrate 100 along the first direction D1, the width of the second portion 192P2 in the third direction D3 may remain unchanged. This may be because the facet of the second sub-side surface 120SS2 of the first side surface 120SS is parallel to the facet of the sixth sub-side surface 220SS2 of the second side surface 220SS in the first direction D1.

[0119] According to some example embodiments, the third portion 192P3 may be disposed on the second portion 192P2. The third portion 192P3 may be disposed between the second portion 192P2 and the fourth portion 192P4 in the first direction D1. The third portion 192P3 may be disposed between the third sub-side surface 120SS3 of the first side surface 120SS and the seventh sub-side surface 220SS3 of the second side surface 220SS. For example, as the third portion 192P3 is located in the third direction D3 between the first gate electrode 120 and the second gate electrode 220, away from the substrate 100 along the first direction D1, the width of the third portion 192P3 in the third direction D3 may be increased. This may be because the facets of the third sub-side surface 120SS3 of the first side surface 120SS and the seventh sub-side surface 220SS3 of the second side surface 220SS are inclined toward the first active pattern AP1 and the second active pattern AP2, respectively.

[0120] According to some example embodiments, the fourth portion 192P4 may be disposed on the third portion 192P3. The fourth portion 192P4 may be disposed between the first upper pattern 120U and the second upper pattern 220U. The fourth portion 192P4 may be the top region of the gate-separated structure GC. For example, the fourth portion 192P4 may include the upper surface of the gate-separated structure GC. The fourth portion 192P4 may be disposed between the top facet of the first side surface 120SS and the top facet of the second side surface 220SS. The fourth portion 192P4 may be disposed between the fourth sub-side surface 120SS4 of the first side surface 120SS and the eighth sub-side surface 220SS4 of the second side surface 220SS. As the fourth portion 192P4 is located in the third direction D3 between the first gate electrode 120 and the second gate electrode 220, away from the substrate 100 along the first direction D1, the width of the fourth portion 192P4 in the third direction D3 may be reduced. This could be due to the facets of the fourth sub-side surface 120SS4 of the first side surface 120SS and the eighth sub-side surface 220SS4 of the second side surface 220SS being inclined to each other. In other words, since the width of the first upper pattern 120U in the third direction D3 increases as the first upper pattern 120U moves away from the substrate 100 along the first direction D1, and since the width of the second upper pattern 220U in the third direction D3 increases as the second upper pattern 220U moves away from the substrate 100 along the first direction D1, the fourth portion 192P4 disposed between the first upper pattern 120U and the second upper pattern 220U can have a width that decreases in the third direction D3 as the fourth portion 192P4 moves away from the substrate 100 along the first direction D1.

[0121] According to some example embodiments, the gate-separated structure GC may include an insulating material. For example, the gate-separated structure GC may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, the example embodiments are not limited thereto.

[0122] According to some example embodiments, a first source / drain pattern 150 may be disposed in a first active region AR1. A second source / drain pattern 250 may be disposed in a second active region AR2. The first source / drain pattern 150 and the second source / drain pattern 250 may be disposed on a third direction D3.

[0123] According to some example embodiments, the first source / drain pattern 150 and the second source / drain pattern 250 may have different doping types. For example, the first source / drain pattern 150 may be p-type, and the second source / drain pattern 250 may be n-type. The first source / drain pattern 150 may contain a p-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). The second source / drain pattern 250 may include an n-type dopant. The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In another example embodiment, the first source / drain pattern 150 may be n-type, and the second source / drain pattern 250 may be p-type.

[0124] According to some example embodiments, the first source / drain pattern 150 may be connected to the first active pattern AP1 in the second direction D2. The first source / drain pattern 150 may be disposed between adjacent first gate electrodes 120 in the second direction D2. The first source / drain pattern 150 may be disposed on the first fin pattern 101.

[0125] According to some example embodiments, the first source / drain pattern 150 may be the source / drain of a PMOS transistor. The first source / drain pattern 150 may be the source / drain of a transistor that uses a first active pattern AP1 as its channel region.

[0126] According to some example embodiments, the second source / drain pattern 250 may be connected to the second active pattern AP2 in the second direction D2. The second source / drain pattern 250 may be disposed between adjacent second gate electrodes 220 in the second direction D2. The second source / drain pattern 250 may be disposed on the second fin pattern 102.

[0127] According to some example embodiments, the second source / drain pattern 250 can be the source / drain of an NMOS transistor. The second source / drain pattern 250 can be the source / drain of a transistor that uses a second active pattern AP2 as its channel region.

[0128] According to some example embodiments, a source / drain etch stop film 160 and a first interlayer insulating film 191 may be disposed on a first source / drain pattern 150 and a second source / drain pattern 250. The source / drain etch stop film 160 may extend along the upper surfaces of the first source / drain pattern 150 and the second source / drain pattern 250 and the upper surface of the device isolation film 105.

[0129] According to some example embodiments, the source / drain etch stop film 160 may include at least one of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0130] According to some example embodiments, a first interlayer insulating film 191 may be disposed on the source / drain etch stop film 160. The first interlayer insulating film 191 may be formed on the device isolation film 105. In a first direction D1, the first interlayer insulating film 191 may be disposed between the first source / drain pattern 150 and the second source / drain pattern 250. The first interlayer insulating film 191 may also be disposed on the sidewalls of the first source / drain pattern 150 and the second source / drain pattern 250 in a third direction D3.

[0131] According to some example embodiments, the second interlayer insulating film 192 may be disposed on the side surfaces of the first gate electrode 120 and the second gate electrode 220 on the third direction D3. The second interlayer insulating film 192 may be disposed between the first gate electrode 120 and the second gate electrode 220 on the third direction D3. The second interlayer insulating film 192 may form a gate separation structure GC located between the first gate electrode 120 and the second gate electrode 220. The second interlayer insulating film 192 may be disposed on the device isolation film 105.

[0132] According to some example embodiments, the first interlayer insulating film 191 and the second interlayer insulating film 192 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and low-k materials. For example, low-k materials may include, but are not limited to, tetraethyl fluorinated silicate (FTEOS), hydrosiloxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl silicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), polytetrafluoroethylene silicate (TOSZ), fluorosilicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0133] According to some example embodiments, a first source / drain contact 171 may be disposed on a first source / drain pattern 150. The first source / drain contact 171 may be connected to the first source / drain pattern 150. The first source / drain contact 171 may be connected to the first source / drain pattern 150 via a first interlayer insulating film 191 and a source / drain etch stop film 160. In the first direction D1, the first source / drain contact 171 may completely penetrate the first interlayer insulating film 191.

[0134] According to some example embodiments, the first source / drain contact 171 may include a first source / drain contact blocking film 171a and a first source / drain contact filling film 171b surrounded by the first source / drain contact blocking film 171a.

[0135] According to some example embodiments, the upper surface of the first source / leak contact barrier film 171a is depicted at substantially the same height as the upper surface of the first source / leak contact filler film 171b, but the upper surface of the first source / leak contact barrier film 171a is not limited thereto. Contrary to what is shown, the upper surface of the first source / leak contact barrier film 171a may be lower than the upper surface of the first source / leak contact filler film 171b.

[0136] According to some example embodiments, the first source / drain contact barrier film 171a may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional materials. According to some example embodiments, in a semiconductor device, the 2D material may be a metallic material and / or a semiconductor material. The two-dimensional material may include two-dimensional allotropes or two-dimensional compounds. For example, the two-dimensional material may include at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but the two-dimensional material is not limited thereto. In other words, the two-dimensional materials described above are listed only as examples, and therefore, the two-dimensional materials that may be included in the semiconductor devices of this disclosure are not limited to those described above.

[0137] According to some example embodiments, the first source / drain contact filler membrane 171b may include at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0138] According to some example embodiments, the first source / drain contact 171 is shown to include multiple conductive films, but is not limited thereto. Contrary to what is shown, the first source / drain contact 171 is clearly a single-layer thin film.

[0139] According to some example embodiments, a second source / drain contact 172 may be disposed on the second source / drain pattern 250. The second source / drain contact 172 may be connected to the second source / drain pattern 250. The second source / drain contact 172 may be connected to the second source / drain pattern 250 via a first interlayer insulating film 191 and a source / drain etch stop film 160. In the first direction D1, the second source / drain contact 172 may completely penetrate the first interlayer insulating film 191.

[0140] According to some example embodiments, the first interlayer insulating film 191 may not cover the upper surfaces of the first source / drain contact 171 and the second source / drain contact 172. In example embodiments, the upper surfaces of the first source / drain contact 171 and the second source / drain contact 172 do not protrude above the upper surfaces of the first gate electrode 120 and the second gate electrode 220. The upper surfaces of the first source / drain contact 171 and the second source / drain contact 172 may be disposed on the same plane as the upper surfaces of the first gate electrode 120 and the second gate electrode 220. Unlike the example shown, in another example embodiment, the upper surfaces of the first source / drain contact 171 and the second source / drain contact 172 may protrude above the upper surfaces of the first gate electrode 120 and the second gate electrode 220.

[0141] According to some example embodiments, the second source / leak contact 172 may include a second source / leak contact blocking film 172a and a second source / leak contact filling film 172b on the second source / leak contact blocking film 172a. The second source / leak contact blocking film 172a may extend along the side surface and bottom surface of the second source / leak contact filling film 172b. The description of the second source / leak contact blocking film 172a and the second source / leak contact filling film 172b is substantially the same as the description of the first source / leak contact blocking film 171a and the first source / leak contact filling film 171b, therefore the description of the second source / leak contact blocking film 172a and the second source / leak contact filling film 172b is omitted.

[0142] According to some example embodiments, a first etch stop film 193 and a third interlayer insulating film 194 may be disposed on a first interlayer insulating film 191, a second interlayer insulating film 192, a first gate electrode 120, a second gate electrode 220, a first source / drain contact 171, and a second source / drain contact 172. The first etch stop film 193 and the third interlayer insulating film 194 may be sequentially stacked in a first direction D1.

[0143] According to some example embodiments, the first etch stop film 193 may include a material having etch selectivity relative to the third interlayer insulating film 194. The first etch stop film 193 may include at least one and combinations thereof, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), and aluminum carbonitride (AlOC). Although the first etch stop film 193 is shown as a single layer, it is not limited thereto. Unlike what is shown, the first etch stop film 193 may not be formed. For example, the third interlayer insulating film 194 may include at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and low-k materials.

[0144] According to some example embodiments, interconnect vias 175 may be disposed within the third interlayer insulating film 194. Interconnect vias 175 may penetrate the first etch stop film 193 and directly connect to the first source / drain contact 171, the second source / drain contact 172, the first gate electrode 120, and the second gate electrode 220. Interconnect vias 175 may be disposed on the first source / drain contact 171, the second source / drain contact 172, the first gate electrode 120, and the second gate electrode 220.

[0145] According to some example embodiments, the interconnect via 175 may include a via blocking film 175a and a via filling film 175b. The via blocking film 175a may extend along the sidewalls and bottom surface of the via filling film 175b. For example, the via blocking film 175a may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and 2D materials. For example, the via filling film 175b may include at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0146] Figures 6 to 9 It is along Figure 1 The cross-sectional view taken by line B-B' is used to illustrate the semiconductor device according to an example embodiment; for ease of understanding of this disclosure, the description will be primarily based on references. Figures 1 to 5 The differences described.

[0147] Reference Figure 6 The first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 can be parallel in the first direction D1. For example, the first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 can be aligned with the (100) crystal plane.

[0148] According to some example embodiments, the first lower pattern 120B may include a region with a constant width in the third direction D3. For example, the first lower pattern 120B may include: a first bottom region connected to the first fin pattern 101 and having a width that increases in the third direction D3 as the first lower pattern 120B moves away from the first fin pattern 101 in the first direction D1; a first top region connected to the first upper pattern 120B and having a width that decreases in the third direction D3 as the first lower pattern 120B moves away from the first fin pattern 101 in the first direction D1; and a first intermediate region disposed between the first bottom region and the first top region. The first intermediate region of the first lower pattern 120B may have a constant width in the third direction D3.

[0149] According to some example embodiments, the second lower pattern 220B may include a region having a constant width in the third direction D3. For example, the second lower pattern 220B may include: a second bottom region connected to the second fin pattern 102 and having a width that increases in the third direction D3 as the second lower pattern 220B moves away from the second fin pattern 102 in the first direction D1; a second top region connected to the second upper pattern 220B and having a width that decreases in the third direction D3 as the second lower pattern 220B moves away from the second fin pattern 102 in the first direction D1; and a second intermediate region disposed between the second bottom region and the second top region. The second intermediate region of the second lower pattern 220B may have a constant width along the third direction D3.

[0150] Reference Figure 7 The first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 may not include a surface parallel to the first direction D1. For example, the first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 may be aligned with the (111) crystal plane. The first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 may include a plurality of facets that are not parallel in the first direction D1 and intersect at a desired and / or alternative desired and / or alternative predetermined angle.

[0151] Reference Figure 8The first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 can have a circular shape. The first side surface 120SS of the first gate electrode 120 can be bent outward in the third direction D3 relative to the center of the first active pattern AP1. The second side surface 220SS of the second gate electrode 220 can be bent outward in the third direction D3 relative to the center of the second active pattern AP2. The contours of the first side surface 120SS of the first gate electrode 120 and the second side surface 220SS of the second gate electrode 220 can be changed according to the process conditions for forming the first gate electrode 120 and the second gate electrode 220.

[0152] Reference Figure 9 The semiconductor device may also include a first insulating post 310 on the first fin pattern 101 and a second insulating post 320 on the second fin pattern 102.

[0153] According to some example embodiments, a first insulating post 310 may extend on the first fin pattern 101 in a first direction D1. The first insulating post 310 may be disposed between a first active portion AP1a and a second active portion AP1b. The first insulating post 310 may separate the first active pattern AP1 into a first active portion AP1a and a second active portion AP1b. The first active portion AP1a and the second active portion AP1b, spaced apart by the first insulating post 310, may serve as the channel region of a forksheet field-effect transistor (FET). The first insulating post 310 may be inserted into the first fin pattern 101. The first insulating post 310 may separate the first fin pattern 101 into a first fin portion 101a and a second fin portion 101b. The first active portion AP1a may be disposed on the first fin portion 101a in the first direction D1. The second active portion AP1b may be disposed on the second fin portion 101b in the first direction D1.

[0154] According to some example embodiments, the first gate electrode 120 may include a first gate portion 121 and a second gate portion 122. The first gate portion 121 and the second gate portion 122 may be spaced apart on a third direction D3, with a first insulating post 310 located between the first gate portion 121 and the second gate portion 122. The first gate portion 121 may be disposed on one side of the first insulating post 310, and the second gate portion 122 may be disposed on the other side of the first insulating post 310. The first gate portion 121 may be disposed on the side of the first insulating post 310 facing the second active pattern AP2 on the third direction D3. The second gate portion 122 may be disposed on the side of the first insulating post 310 facing the second active pattern AP2 on the third direction D3.

[0155] According to some example embodiments, the first gate portion 121 may surround the first active portion AP1a. The first gate portion 121 may fill the space formed by the first active portion AP1a and the first insulating pillar 310. For example, the first gate portion 121 may be disposed between a plurality of first wafers spaced apart in the first direction D1 of the first active portion AP1a.

[0156] According to some example embodiments, the first gate portion 121 may include a first portion upper pattern 121U and a first portion lower pattern 121B. The first portion upper pattern 121U and the first portion lower pattern 121B may be connected in a first direction D1.

[0157] According to some example embodiments, the first portion of the lower pattern 121B may be configured to be below the upper surface of the first insulating pillar 310. The first portion of the lower pattern 121B may surround the first active portion AP1a. The first portion of the lower pattern 121B's side surface 121SS may include facets. The first portion of the lower pattern 121B's side surface 121SS may be a surface opposite to the side surface of the first portion of the lower pattern 121B facing the first insulating pillar 310 in a third direction. The first portion of the lower pattern 121B's side surface 121SS may protrude outwardly in the third direction D3 based on the first insulating pillar 310. As the first portion of the lower pattern 121B moves away from the substrate 100 in the first direction D1, the width of the first portion of the lower pattern 121B along the third direction D3 may increase and then decrease again.

[0158] According to some example embodiments, the lower part of the first portion pattern 121B may include a facet that intersects the upper surface of the top first piece and the first insulating post 310, which protrude upward from the top first piece, at a desired and / or alternative predetermined angle. The top first piece is disposed at the top of the first active portion AP1a in the first direction D1. The lower part of the first portion pattern 121B may not cover the side surface of the first insulating post 310 that protrudes upward above the first active portion AP1a.

[0159] According to some example embodiments, the upper part of the first portion pattern 121U may be disposed on the lower part of the first portion pattern 121B. As the upper part of the first portion pattern 121U moves away from the lower part of the first portion pattern 121B in the first direction D1, the width of the upper part of the first portion pattern 121U in the third direction D3 may increase.

[0160] According to some example embodiments, the second gate portion 122 may surround the second active portion AP1b. The second gate portion 122 may fill the space formed by the second active portion AP1b and the first insulating pillar 310. For example, the second gate portion 122 may be disposed between a plurality of first pieces spaced apart in the first direction D1 of the second active portion AP1b.

[0161] According to some example embodiments, the second gate portion 122 may include a second upper pattern 122U and a second lower pattern 122B. The second upper pattern 122U and the second lower pattern 122B may be disposed in the first direction D1.

[0162] According to some example embodiments, the second lower portion pattern 122B may be configured to be below the upper surface of the first insulating pillar 310. The second lower portion pattern 122B may surround the second active portion AP1b. The second portion side surface 122SS of the second lower portion pattern 122B may include facets. The second portion side surface 122SS of the second lower portion pattern 122B may be the side surface of the second lower portion pattern 122B facing the second insulating pillar 320 in the third direction D3. The second portion side surface 122SS of the second lower portion pattern 122B may be a surface disposed on the side opposite to the side surface of the second lower portion pattern 122B facing the first insulating pillar 310 in the third direction D3. The second portion side surface 122SS of the second lower portion pattern 122B may protrude outward relative to the first insulating pillar 310 in the direction opposite to the third direction D3. As the second lower portion pattern 122B moves away from the substrate 100 in the first direction D1, the width of the second lower portion pattern 122B along the third direction D3 may increase and then decrease.

[0163] According to some example embodiments, the lower part of the second portion pattern 122B may include a facet that intersects the upper surface of the top first piece and the first insulating post 310, which protrudes upward from the top first piece, at a desired and / or alternative predetermined angle. The top first piece is disposed at the top of the first active portion AP1a in the first direction D1. The lower part of the second portion pattern 122B may not cover the side surface of the first insulating post 310 that protrudes above the second active portion AP1b.

[0164] According to some example embodiments, the upper pattern 122U of the second part can be disposed on the lower pattern 122B of the second part. As the upper pattern 122U of the second part moves away from the lower pattern 122B of the second part in the first direction D1, the width of the upper pattern 122U of the second part in the third direction D3 can be increased.

[0165] According to some example embodiments, based on the first insulating pillar 310, the first gate portion 121 and the second gate portion 122 can be symmetrically disposed in the third direction D3. For example, each of the first partial side surface 121SS and the second partial side surface 122SS of the first gate portion 121 may include a facet having a protruding profile in the outward direction relative to the first insulating pillar 310. The thickness of the first gate portion 121 disposed on the outer surface of the first active portion AP1a in the third direction D3 may be the same as the thickness of the second gate portion 122 disposed on the outer surface of the second active portion AP1b in the third direction D3, wherein the outer surface of the first active portion AP1a is disposed on the side opposite to the inner surface of the first active portion AP1a that contacts the first insulating pillar 310, and the outer surface of the second gate portion 122 is disposed on the side opposite to the inner surface of the second active portion AP1b that contacts the first insulating pillar 310.

[0166] According to some example embodiments, the first gate insulating film 130 may include a first portion insulating film 131 and a second portion insulating film 132. The first portion insulating film 131 and the second portion insulating film 132 may be spaced apart, and a first insulating post 310 is located between the first portion insulating film 131 and the second portion insulating film 132. The first portion insulating film 131 and the second portion insulating film 132 may not be connected to each other.

[0167] According to some example embodiments, a first portion of the insulating film 131 may surround the first gate portion 121. The first portion of the insulating film 131 may extend along the surfaces of the first active portion AP1a and the first insulating post 310. The first portion of the insulating film 131 may cover the lower surface of the first gate portion 121, the side surface of the upper pattern 121U of the first portion, and the first portion of the side surface 121SS of the lower pattern 121B of the first portion. The first portion of the insulating film 131 may not extend along the portion of the first insulating post 310 that protrudes upward beyond the first active portion AP1a.

[0168] According to some example embodiments, the second insulating film 132 may surround the second gate portion 122. The second insulating film 132 may extend along the surfaces of the second active portion AP1b and the first insulating pillar 310. The second insulating film 132 may cover the lower surface of the second gate portion 122, the side surface of the upper pattern 122U of the second portion, and the second side surface 122SS of the lower pattern 122B of the second portion. The second insulating film 132 may not extend along the portion of the first insulating pillar 310 that protrudes upward beyond the second active portion AP1b.

[0169] According to some example embodiments, the second insulating post 320 may extend on the second fin pattern 102 in a first direction D1. The second insulating post 320 may be disposed between the third active portion AP2a and the fourth active portion AP2b. The second insulating post 320 may separate the second active pattern AP2 into the third active portion AP2a and the fourth active portion AP2b. The third active portion AP2a and the fourth active portion AP2b, separated by the second insulating post 320, may be used as the channel region of a forksheet field-effect transistor (FET). The second insulating post 320 may be inserted into the second fin pattern 102. The second insulating post 320 may separate the second fin pattern 102 into the third fin portion 102a and the fourth fin portion 102b. The third active portion AP2a may be disposed on the third fin portion 102a in the first direction D1. The fourth active portion AP2b may be disposed on the fourth fin portion 102b in the first direction D1.

[0170] According to some example embodiments, the second gate electrode 220 may include a third gate portion 221 and a fourth gate portion 222. The third gate portion 221 and the fourth gate portion 222 may be spaced apart from each other on a third-direction D3, with a second insulating pillar 320 located between the third gate portion 221 and the fourth gate portion 222. The third gate portion 221 may be disposed on one side of the second insulating pillar 320, and the fourth gate portion 222 may be disposed on the other side of the second insulating pillar 320. The third gate portion 221 may be disposed on the side of the second insulating pillar 320 facing the first active pattern AP1 on the third-direction D3. The fourth gate portion 222 may be disposed on the side opposite to the side of the second insulating pillar 320 facing the first active pattern AP1 on the third-direction D3.

[0171] According to some example embodiments, the third gate portion 221 may surround the third active portion AP2a. The third gate portion 221 may fill the space formed by the third active portion AP2a and the second insulating pillar 320. For example, the third gate portion 221 may be disposed between a plurality of second plates spaced apart from each other in the first direction D1 of the third active portion AP2a.

[0172] According to some example embodiments, the third gate portion 221 may include a third upper pattern 221U and a third lower pattern 221B. The third upper pattern 221U and the third lower pattern 221B may be connected in the first direction D1.

[0173] According to some example embodiments, the lower third portion pattern 221B may be configured to be below the upper surface of the second insulating post 320. The lower third portion pattern 221B may surround the third active portion AP2a. The third portion side surface 221SS of the lower third portion pattern 221B may include facets. The third portion side surface 221SS of the lower third portion pattern 221B may be the side surface of the lower third portion pattern 221B facing the first insulating post 310 in the third third direction D3. The third portion side surface 221SS of the lower third portion pattern 221B may be a surface disposed on the side opposite to the side surface of the lower third portion pattern 221B facing the second insulating post 320 in the third third direction D3. The third portion side surface 221SS of the lower third portion pattern 221B may protrude outward relative to the second insulating post 320 in the third third direction D3. As the lower third pattern 221B moves away from the substrate 100 in the first direction D1, the width of the lower third pattern 221B along the third third direction D3 can increase and then decrease.

[0174] According to some example embodiments, the lower pattern 221B of the third portion may be a facet that intersects the upper surface of the top second piece and the second insulating post 320, which protrudes upward from the top second piece, at a desired and / or alternative predetermined angle. The top second piece is disposed at the top of the third active portion AP2a in the first direction D1. The lower pattern 221B of the third portion may not cover the side surface of the second insulating post 320 that protrudes upward above the third active portion AP2a.

[0175] According to some example embodiments, the upper third pattern 221U can be disposed on the lower third pattern 221B. As the upper third pattern 221U moves away from the lower third pattern 221B in the first direction D1, the width of the upper third pattern 221U along the third third direction D3 can be increased.

[0176] According to some example embodiments, the fourth gate portion 222 may surround the fourth active portion AP2b. The fourth gate portion 222 may fill the space formed by the fourth active portion AP2b and the second insulating post 320. For example, the fourth gate portion 222 may be disposed between a plurality of second plates spaced apart from each other in the first direction D1 of the fourth active portion AP2b.

[0177] According to some example embodiments, the fourth gate portion 222 may include an upper fourth portion pattern 222U and a lower fourth portion pattern 222B. The upper fourth portion pattern 222U and the lower fourth portion pattern 222B may be disposed on the first direction D1.

[0178] According to some example embodiments, the fourth lower portion pattern 222B may be configured to be below the upper surface of the second insulating pillar 320. The fourth lower portion pattern 222B may surround the fourth active portion AP2b. The fourth portion side surface 222SS of the fourth lower portion pattern 222B may include facets. The fourth portion side surface 222SS of the fourth lower portion pattern 222B may be a surface disposed on the side opposite to the side surface of the fourth lower portion pattern 222B facing the second insulating pillar 320 in the third direction D3. The fourth portion side surface 222SS of the fourth lower portion pattern 222B may protrude outward relative to the second insulating pillar 320 in the direction opposite to the third direction D3. As the fourth lower portion pattern 222B moves away from the substrate 100 in the first direction D1, the width of the fourth lower portion pattern 222B along the third direction D3 may increase and then decrease again.

[0179] According to some example embodiments, the lower pattern 222B of the fourth portion may include a facet that intersects the upper surface of the top second sheet and the second insulating post 320, which protrudes upward from the top second sheet, at a desired and / or alternative predetermined angle. The top second sheet is disposed at the top of the fourth active portion AP2b in the first direction D1. The lower pattern 222B of the fourth portion may not cover the side surface of the second insulating post 320 that protrudes above the fourth active portion AP2b.

[0180] According to some example embodiments, the upper pattern 222U of the fourth part can be disposed on the lower pattern 222B of the fourth part. As the upper pattern 222U of the fourth part moves away from the lower pattern 222B of the fourth part along the first direction D1, the width of the upper pattern 222U of the fourth part along the third direction D3 can increase.

[0181] According to some example embodiments, based on the second insulating pillar 320, the third gate portion 221 and the fourth gate portion 222 can be symmetrically arranged in the third direction D3. For example, each of the third portion side surface 221SS of the third gate portion 221 and the fourth portion side surface 222SS of the fourth gate portion 222 can include a facet having a convex profile in the outward direction relative to the second insulating pillar 320. The thickness of the third gate portion 221 disposed on the outer surface of the third active portion AP2a in the third direction D3 can be equal to the thickness of the fourth gate portion 222 disposed on the outer surface of the fourth active portion AP2b in the third direction D3, wherein the outer surface of the third active portion AP2a is disposed on the side opposite to the inner surface of the third active portion AP2a that contacts the second insulating pillar 320, and the outer surface of the fourth active portion AP2b is disposed on the side opposite to the inner surface of the fourth active portion AP2b that contacts the second insulating pillar 320.

[0182] According to some example embodiments, the second gate insulating film 230 may include a third insulating film 231 and a fourth insulating film 232. The third insulating film 231 and the fourth insulating film 232 may be spaced apart from each other, and the second insulating post 320 is located between the third insulating film 231 and the fourth insulating film 232. The third insulating film 231 and the fourth insulating film 232 may not be connected to each other.

[0183] According to some example embodiments, the third insulating film 231 may surround the third gate portion 221. The third insulating film 231 may extend along the surfaces of the third active portion AP2a and the second insulating pillar 320. The third insulating film 231 may cover the lower surface of the third gate portion 221, the side surface of the upper third pattern 221U, and the third side surface 221SS of the lower third pattern 221B. The third insulating film 231 may not extend along the portion of the second insulating pillar 320 that protrudes upward beyond the third active portion AP2a.

[0184] According to some example embodiments, the fourth insulating film 232 may surround the fourth gate portion 222. The fourth insulating film 232 may extend along the surfaces of the fourth active portion AP2b and the second insulating post 320. The fourth insulating film 232 may cover the lower surface of the fourth gate portion 222, the side surface of the upper pattern 222U of the fourth portion, and the fourth side surface 222SS of the lower pattern 222B of the fourth portion. The fourth insulating film 232 may not extend upwards beyond a portion of the fourth active portion AP2b along the second insulating post 320.

[0185] According to some example embodiments, the first insulating post 310 and the second insulating post 320 may include an insulating material. For example, each of the first insulating post 310 and the second insulating post 320 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. Although Figure 9 The first insulating post 310 and the second insulating post 320 are shown to comprise a single-layer film, but the example embodiment is not limited thereto. For example, it is clear that the first insulating post 310 and the second insulating post 320 may comprise a multilayer film.

[0186] Figure 9Interconnect vias 175 are shown disposed on the first gate portion 121, the second gate portion 122, the third gate portion 221, and the fourth gate portion 222, respectively, but the example embodiment is not limited thereto. For example, at least a portion of the first gate portion 121, the second gate portion 122, the third gate portion 221, and the fourth gate portion 222 may not be connected to the interconnect vias 175, and may be connected to a back-side via that penetrates the substrate 100 and the first fin pattern 101 or the second fin pattern 102 in the first direction D1.

[0187] Figure 10 It is along Figure 1 The cross-sectional view taken by line A-A' in the figure is used to illustrate a semiconductor device according to an example embodiment. Figure 11 It is along Figure 1 The cross-sectional view taken by line B-B' is used to illustrate a semiconductor device according to an example embodiment. For ease of understanding of this disclosure, the description will primarily focus on the device with reference to... Figures 1 to 5 The differences described.

[0188] Reference Figure 10 and Figure 11 The semiconductor device may include a first gate capping film 125, a second gate capping film 225, a first gate contact portion 181, and a second gate contact portion 182.

[0189] According to some example embodiments, a first gate capping film 125 may be disposed on the first gate electrode 120, the first gate insulating film 130, and the gate spacer 140. The upper surface of the first gate capping film 125 may be disposed on the same plane as the upper surface of the first interlayer insulating film 191 and the upper surface of the second interlayer insulating film 192. Unlike the examples shown, the first gate capping film 125 may be disposed between the gate spacers 140 in a second direction D2. In this case, the upper surface of the first gate capping film 125 and the upper surface of the gate spacer 140 may be disposed on the same plane.

[0190] According to some example embodiments, a first gate capping film 125 may be disposed on a first upper pattern 120U. The side surface of the first gate capping film 125 in the third direction D3 may be disposed on the same plane as the side surface of the first upper pattern 120U in the third direction D3. As the first gate capping film 125 moves away from the first upper pattern 120U along the first direction D1, the width of the first gate capping film 125 in the third direction D3 may increase.

[0191] According to some example embodiments, a second gate capping film 225 may be disposed on the second gate electrode 220, the second gate insulating film 230, and the gate spacer 140. The upper surface of the second gate capping film 225 may be disposed on the same plane as the upper surface of the first interlayer insulating film 191 and the upper surface of the second interlayer insulating film 192.

[0192] According to some example embodiments, a second gate capping film 225 may be disposed on the second upper pattern 220U. The side surface of the second gate capping film 225 along the third direction D3 may be disposed on the same plane as the side surface of the second upper pattern 220U in the third direction D3. As the second gate capping film 225 moves away from the second upper pattern 220U in the first direction D1, the width of the second gate capping film 225 in the third direction D3 may increase.

[0193] According to some example embodiments, the first gate capping film 125 and the second gate capping film 225 may be surrounded by a second interlayer insulating film 192 in a third direction D3. The side surfaces of the first gate capping film 125 and the second gate capping film 225 in the third direction D3 may be covered by the second interlayer insulating film 192. The first gate capping film 125 and the second gate capping film 225 may penetrate at least a portion of the second interlayer insulating film 192 in a first direction D1. The upper surfaces of the first gate capping film 125 and the second gate capping film 225 may be disposed on the same plane as the upper surface of the gate separation structure GC and the upper surface of the second interlayer insulating film 192.

[0194] According to some example embodiments, the first gate capping film 125 and the second gate capping film 225 may include at least one of, for example, silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. The first gate capping film 125 and the second gate capping film 225 may include materials that have etch selectivity relative to the first interlayer insulating film 191 and the second interlayer insulating film 192.

[0195] According to some example embodiments, a first gate contact 181 may be disposed on the first gate electrode 120. The first gate contact 181 may be connected to the first gate electrode 120 by penetrating the first gate capping film 125, the first etch stop film 193, and the third interlayer insulating film 194.

[0196] According to some example embodiments, the first gate contact 181 may include a first gate contact barrier film 181a and a first gate contact fill film 181b surrounded by the first gate contact barrier film 181a. The description of the materials included in the first gate contact barrier film 181a and the first gate contact fill film 181b may be the same as the description of the materials included in the first source / drain contact barrier film 171a and the first source / drain contact fill film 171b.

[0197] According to some example embodiments, the second gate contact 182 may be disposed on the second gate electrode 220. The second gate contact 182 may be connected to the second gate electrode 220 by penetrating the second gate capping film 225, the first etch stop film 193 and the third interlayer insulating film 194.

[0198] According to some example embodiments, the second gate contact 182 may include a second gate contact barrier film 182a and a second gate contact fill film 182b on the second gate contact barrier film 182a. The description of the materials contained in the second gate contact barrier film 182a and the second gate contact fill film 182b may be the same as the description of the materials contained in the first source / drain contact barrier film 171a and the first source / drain contact fill film 171b.

[0199] Figure 10 and Figure 11 The illustration shows the upper surfaces of the first gate contact 181 and the second gate contact 182 disposed above the upper surfaces of the first gate capping film 125 and the second gate capping film 225, but the example embodiment is not limited thereto. For example, the upper surfaces of the first gate contact 181 and the second gate contact 182 may be disposed on the same plane as the upper surfaces of the first gate capping film 125 and the second gate capping film 225. In this case, the interconnect via 175 may be connected to the first gate contact 181 and the second gate contact 182.

[0200] Figure 10 The example shows that the upper surface of the interconnect via 175 and the upper surface of the first gate contact 181 are disposed on the same plane, but the example embodiment is not limited thereto. For example, the upper surface of the first gate contact 181 may be disposed below the upper surface of the interconnect via 175.

[0201] Figure 12 It is along Figure 1 The cross-sectional view taken by line B-B' is used to illustrate a semiconductor device according to an example embodiment. For ease of understanding of this disclosure, the following description focuses on and refers to... Figure 10 and Figure 11 The differences mentioned above.

[0202] Reference Figure 12 A first gate capping film 125 may be disposed on the first gate electrode 120, the second gate electrode 220, the gate separation structure GC, and the second interlayer insulating film 192. The first gate capping film 125 may cover the upper surface of the gate separation structure GC, the upper surface of the first gate electrode 120, and the upper surface of the second gate electrode 220. The first gate capping film 125 may extend along a third direction D3. The first gate capping film 125 may be disposed on the first upper pattern 120U of the first gate electrode 120 and the second upper pattern 220U of the second gate electrode 220.

[0203] Figures 13 to 34 This illustrates the manufacturing process according to an example embodiment. Figure 2 and Figure 3 A diagram illustrating intermediate operations of a method for using a semiconductor device.

[0204] Reference Figure 13 and Figure 14 A first sacrificial film SL1 and a first active pattern AP1 can be alternately stacked on the substrate 100 and the first fin pattern 101. A second sacrificial film SL2 and a second active pattern AP2 can be alternately stacked on the substrate 100 and the second fin pattern 102. A device isolation film 105 can be formed between the first fin pattern 101 and the second fin pattern 102.

[0205] According to some example embodiments, the alternatingly stacked first sacrificial film SL1 and first active pattern AP1 may extend along the second direction D2. The alternatingly stacked second sacrificial film SL2 and second active pattern AP2 may also extend along the second direction D2. When the first sacrificial film SL1 and first active pattern AP1, as well as the second sacrificial film SL2 and second active pattern AP2, are patterned to be spaced apart in the third direction D3, a first fin pattern 101 and a second fin pattern 102 may be formed on the substrate 100.

[0206] According to some example embodiments, the first sacrificial film SL1 and the second sacrificial film SL2 may contain the same material. The first sacrificial film SL1 and the second sacrificial film SL2 may contain materials different from those of the first active pattern AP1 and the second active pattern AP2. For example, each of the first sacrificial film SL1 and the second sacrificial film SL2 may contain silicon germanium (SiGe), and each of the first active pattern AP1 and the second active pattern AP2 may contain silicon (Si).

[0207] Reference Figure 15 and Figure 16 This can form a dummy gate electrode 120D, a gate spacer 140, and a dummy capping film 125D.

[0208] According to some example embodiments, a dummy gate electrode 120D can be formed on alternately stacked first sacrificial film SL1 and first active pattern AP1, and alternately stacked second sacrificial film SL2 and second active pattern AP2. The dummy gate electrode 120D can extend in a third direction D3. The dummy gate electrode 120D can be formed on a device isolation film 105. The dummy gate electrode 120D can be disposed in a second direction D2 between a pair of gate spacers 140. The dummy gate electrode 120D can be disposed at multiple locations spaced apart in the second direction D2.

[0209] According to some example embodiments, a dummy capping film 125D may be disposed on the dummy gate electrode 120D and the gate spacer 140. The dummy capping film 125D may cover the dummy gate electrode 120D and the gate spacer 140. The dummy gate electrode 120D may comprise, for example, polysilicon, and the dummy capping film 125D may comprise, for example, silicon nitride. However, the example embodiments are not limited thereto.

[0210] Reference Figure 17 and Figure 18 A dummy gate electrode 120D, a gate spacer 140, and a dummy capping film 125D can be used in the second direction D2 (in... Figure 15 The first sacrificial film SL1 and the first active pattern AP1, which are alternately stacked, are patterned to form a first source / drain pattern 150. Subsequently, a second source / drain pattern 250 can be formed within the first source / drain pattern 150. Figure 5 A source / drain etch stop film 160 and a first interlayer insulating film 191 are formed on the middle layer. A first source / drain pattern 150 and a second source / drain pattern 250 are formed on the middle layer. Figure 5 In the process of etching the source / drain stop film 160 and the first interlayer insulating film 191, the dummy capping film 125D can be removed. Figure 15 middle).

[0211] According to some example embodiments, in order to space the first sacrificial film SL1 and the first active pattern AP1 extending along the second direction D2 in the second direction D2, a dummy gate electrode 120D, a gate spacer 140, and a dummy capping film 125D can be used. Figure 15 (In the middle) Remove and pattern a portion of the first sacrificial film SL1 and the first active pattern AP1. For example, a dummy gate electrode 120D, a gate spacer 140, and a dummy capping film 125D can be used (in Figure 15Using a mask, the first sacrificial film SL1 and the first active pattern AP1 are patterned by an etching process. Then, a first source / drain pattern 150 can be formed between the first sacrificial film SL1 and the first active pattern AP1, which are spaced apart along the second direction D2. For example, the first source / drain pattern 150 can be formed by epitaxial growth from the first sacrificial film SL1.

[0212] According to some example embodiments, in order to space the second sacrificial film SL2 and the second active pattern AP2 extending along the second direction D2 in the second direction D2, a dummy gate electrode 120D, a gate spacer 140, and a dummy capping film 125D can be used. Figure 15 (In the middle) Remove and pattern a portion of the second sacrificial film SL2 and the second active pattern AP2. For example, a dummy gate electrode 120D, a gate spacer 140, and a dummy capping film 125D can be used (in Figure 15 Using a mask, a second sacrificial film SL2 and a second active pattern AP2 are patterned through an etching process. Subsequently, a second source / drain pattern 250 can be formed between the second sacrificial film SL2 and the second active pattern AP2, spaced apart along the second direction D2. Figure 5 (in the middle). For example, the second source / drain pattern 250 can be formed by epitaxial growth from the second sacrificial film SL2 (in Figure 5 middle).

[0213] Reference Figure 19 and Figure 20 This can remove the dummy gate electrode 120D (in Figure 17 and Figure 18 (in the middle). For example, the dummy gate electrode 120D can be removed by an etching process (in the middle). Figure 17 and Figure 18 (In the middle). The first active pattern AP1 may be exposed in the second direction D2 between the gate spacers 140. The device isolation film 105 may be exposed between the alternatingly stacked first sacrificial film SL1 and the first active pattern AP1 and between the alternatingly stacked second sacrificial film SL2 and the second active pattern AP2.

[0214] Reference Figure 21 and Figure 22 A first epitaxial pattern 120E and a second epitaxial pattern 220E can be formed. The first epitaxial pattern 120E and the second epitaxial pattern 220E can be formed on the second direction D2 between the gate spacers 140.

[0215] According to some example embodiments, a first epitaxial pattern 120E can be formed by epitaxial growth from a first sacrificial film SL1. The first epitaxial pattern 120E can surround an alternately stacked first sacrificial film SL1 and a first active pattern AP1. A second epitaxial pattern 220E can be formed by epitaxial growth from a second sacrificial film SL2. The second epitaxial pattern 220E can surround an alternately stacked second sacrificial film SL2 and a second active pattern AP2.

[0216] According to some example embodiments, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have crystal planes corresponding to the crystal planes of the substrate 100. For example, when the upper surface of the substrate 100 has a (110) crystal plane and the notch of the substrate 100 has a

[100] crystal orientation, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have (100) crystal planes and (111) crystal planes. In another example embodiment, when the upper surface of the substrate 100 has a (100) crystal plane and the notch of the substrate 100 has a

[110] crystal orientation, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have (111) crystal planes. In another example embodiment, when the upper surface of the substrate 100 has a (100) crystal plane and the notch of the substrate 100 has a

[100] crystal orientation, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have (100) crystal planes.

[0217] According to some example embodiments, the (100) crystal planes of the first epitaxial pattern 120E and the second epitaxial pattern 220E may be parallel in the first direction D1. The (111) crystal planes of the first epitaxial pattern 120E and the second epitaxial pattern 220E intersect the first direction D1 and the third direction D3, and may be tilted relative to the first direction D1.

[0218] Reference Figure 23 and Figure 24 A protective film 195 can be formed. The protective film 195 can be formed on the first epitaxial pattern 120E and the second epitaxial pattern 220E. For example, the protective film 195 can contain a carbon-based material. The protective film 195 can include at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), and a silicon nitride film.

[0219] According to some example embodiments, the protective film 195 may be disposed between the gate spacers 140 in a second direction D2. The protective film 195 may extend between the gate spacers 140 along a third direction D3. The protective film 195 may cover the device isolation film 105.

[0220] Reference Figure 25 and Figure 26A first contact pattern 120C and a second contact pattern 220C can be formed. The first contact pattern 120C can be formed on the first epitaxial pattern 120E by penetrating a portion of the protective film 195. The second contact pattern 220C can be formed on the second epitaxial pattern 220E by penetrating a portion of the protective film 195.

[0221] According to some example embodiments, a portion of the protective film 195 may be removed to form a trench exposing the first epitaxial pattern 120E and the second epitaxial pattern 220E. For example, a portion of the protective film 195 may be removed by an etching process to form the trench. The first contact pattern 120C and the second contact pattern 220C may be formed within the formed trench. The first contact pattern 120C and the second contact pattern 220C may comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0222] Reference Figure 27 It can remove the protective film ( Figure 26 (In 195). With protective film 195 (in Figure 26 The middle part is removed, which can expose the first epitaxial pattern 120E and the first contact pattern 120C, the second epitaxial pattern 220E and the second contact pattern 220C, and the device isolation film 105.

[0223] Reference Figure 28 A second interlayer insulating film 192 can be formed. The second interlayer insulating film 192 can be formed on the first epitaxial pattern 120E and the first contact pattern 120C, the second epitaxial pattern 220E and the second contact pattern 220C, and the device isolation film 105. The second interlayer insulating film 192 can surround the first epitaxial pattern 120E and the first contact pattern 120C, as well as the second epitaxial pattern 220E and the second contact pattern 220C.

[0224] Reference Figure 29 and Figure 30 It can remove the first sacrificial membrane SL1 (in Figure 25 and Figure 28 (in the middle), the first extensional pattern 120E (in Figure 25 and Figure 28 (in the middle), and the first contact pattern 120C (in Figure 25 and Figure 28 (in the middle). With the first sacrificial membrane SL1 (in Figure 25 and Figure 28 The first active pattern 120E can be removed, and a first space SP1 can be formed between the first active patterns AP1 in the first direction D1. Figure 25 and Figure 28 (in) and the first contact pattern 120C (in) Figure 25 and Figure 28(in the middle), to form a first gate electrode trench 120T within the second interlayer insulating film 192.

[0225] Reference Figure 31 and Figure 32 A first gate insulating film 130 and a first gate electrode 120 can be formed thereon. The first gate insulating film 130 and the first gate electrode 120 can be formed in the first space SP1 (in... Figure 29 and Figure 30 (in the middle) The first gate insulating film 130 may surround the first active pattern AP1. The first gate insulating film 130 may be along the first gate electrode trench 120T (in the middle). Figure 30 The first gate electrode 120 extends to the bottom and side surfaces of the first gate insulating film 130. The first gate electrode 120 can fill the first gate electrode trench 120T on the first gate insulating film 130. Figure 30 middle).

[0226] Reference Figure 33 It can remove the second sacrificial membrane SL2 (in Figure 32 (in the middle), the second extensional pattern 220E (in Figure 32 (in) and second contact pattern 220C (in) Figure 32 (in the middle). With the second sacrificial membrane SL2 (in Figure 32 The middle) is removed, and a second space SP2 can be formed between the second active patterns AP2 in the first direction D1. When the second epitaxial pattern 220E (in Figure 32 (in) and second contact pattern 220C (in) Figure 32 When the middle layer is removed, a second gate electrode trench 220T can be formed in the second interlayer insulating film 192.

[0227] Reference Figure 34 A second gate insulating film 230 and a second gate electrode 220 can be formed thereon. The second gate insulating film 230 and the second gate electrode 220 can be formed in the second space SP2 (in... Figure 33 (in the middle) The second gate insulating film 230 may surround the second active pattern AP2. The second gate insulating film 230 may be along the second gate electrode trench 220T (in the middle). Figure 33 The second gate electrode 220 extends to the bottom and side surfaces of the second gate insulating film 230. The second gate electrode 220 can fill the second gate electrode trench 220T on the second gate insulating film 230. Figure 33 middle).

[0228] Then, refer to Figure 2 and Figure 3 A first etch stop film 193 and a third interlayer insulating film 194 can be formed on the second interlayer insulating film 192, and a first source / drain contact 171, a second source / drain contact 172, and an interconnect via 175 can be formed.

[0229] According to some example embodiments, when a semiconductor device is manufactured according to the method for manufacturing a semiconductor device according to this disclosure, the first epitaxial pattern 120E (in) Figure 24 (in the middle) and second epitaxial pattern 220E (in Figure 24 (middle) can be replaced with the first gate electrode 120 (in) Figure 34 (middle) and second gate electrode 220 (in Figure 34 Therefore, it is not necessary to use the first gate electrode 120 (in the middle). Figure 34 (in) and the second gate electrode 220 (in) Figure 34 A gate-separated structure GC is formed between (in) and (in) Figure 3 The separate process (in the middle) is used to form the first epitaxial pattern 120E (in the middle) Figure 24 (in the middle) and second epitaxial pattern 220E (in Figure 24 (in) and with the first gate electrode 120 (in Figure 34 (middle) and second gate electrode 220 ( Figure 34 In the process of replacing them (in the middle), the first gate electrode 120 (in Figure 34 (middle) and second gate electrode 220 (in Figure 34 (In the middle) can be spaced apart and electrically insulated.

[0230] According to some example embodiments, although as the size of semiconductor devices shrinks, in the first gate electrode 120 (at Figure 34 (in) and the second gate electrode 220 (in) Figure 34 A gate-separated structure GC is formed between (in) and (in) Figure 3 The manufacturing process becomes more challenging, especially for the first gate electrode 120 (in the middle). Figure 34 (in) and the second gate electrode 220 (in) Figure 34 The gap between the two gate electrodes becomes narrower, but the semiconductor device of this disclosure can be made narrower by using the first gate electrode 120 (in the middle). Figure 34 (middle) and second gate electrode 220 (in Figure 34 (in) Replace the first epitaxial pattern 120E (in) Figure 24 (in the middle) and second epitaxial pattern 220E (in Figure 24 (in) to stably form a gate-separated structure GC (in) Figure 3 (in the middle), without needing to form a gate-separated structure GC (in Figure 3 A separate process (in the middle). According to the example embodiment, the difficulty of the manufacturing process of semiconductor devices can be reduced.

[0231] Figures 35 to 45 This illustrates the manufacturing process according to an example embodiment. Figure 9 A diagram illustrating intermediate operations of a method using a semiconductor device is shown. For ease of understanding of this disclosure, the following description focuses on and refers to... Figures 13 to 34 The differences mentioned above. Figure 35 It shows Figure 14The diagram shows the subsequent operations.

[0232] Reference Figure 14 and Figure 35 A first insulating post groove 310T can be formed on the first fin pattern 101, and a second insulating post groove 320T can be formed on the second fin pattern 102.

[0233] According to some example embodiments, a portion of the alternately stacked first sacrificial film SL1 and the first active pattern AP1 can be removed to form a first insulating pillar trench 310T. With the formation of the first insulating pillar trench 310T, the first active pattern AP1 can be separated into a first active portion AP1a and a second active portion AP1b.

[0234] According to some example embodiments, a portion of the alternately stacked second sacrificial film SL2 and the second active pattern AP2 can be removed to form a second insulating pillar trench 320T. With the formation of the second insulating pillar trench 320T, the second active pattern AP2 can be separated into a third active portion AP2a and a fourth active portion AP2b.

[0235] Reference Figure 36 This can form a first insulating post 310 and a second insulating post 320. Each of the first insulating post 310 and the second insulating post 320 can fill the first insulating post groove 310T (in Figure 35 (in the middle) and second insulating column trench 320T (in Figure 35 (In the middle). The first insulating post 310 may be formed between the first active portion AP1a and the second active portion AP1b. The second insulating post 320 may be formed between the third active portion AP2a and the fourth active portion AP2b. The first insulating post 310 and the second insulating post 320 may be formed to protrude above the first active pattern AP1 and the second active pattern AP2.

[0236] Reference Figure 37 A first epitaxial pattern 120E and a second epitaxial pattern 220E can be formed. The first epitaxial pattern 120E can be formed by epitaxial growth from a first sacrificial film SL1. The first epitaxial pattern 120E can surround an alternately stacked first sacrificial film SL1 and a first active pattern AP1. The second epitaxial pattern 220E can be formed by epitaxial growth from a second sacrificial film SL2. The second epitaxial pattern 220E can surround an alternately stacked second sacrificial film SL2 and a second active pattern AP2.

[0237] According to some example embodiments, the first epitaxial pattern 120E may include a first portion epitaxial pattern 121E and a second portion epitaxial pattern 122E. The first portion epitaxial pattern 121E may surround a first active portion AP1a. The second portion epitaxial pattern 122E may surround a second active portion AP1b.

[0238] According to some example embodiments, the second epitaxial pattern 220E may include a third epitaxial pattern 221E and a fourth epitaxial pattern 222E. The third epitaxial pattern 221E may surround the third active portion AP2a. The fourth epitaxial pattern 222E may surround the fourth active portion AP2b.

[0239] According to some example embodiments, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have crystal planes corresponding to the crystal planes of the substrate 100. For example, when the upper surface of the substrate 100 has a (110) crystal plane and the notch of the substrate 100 has a

[100] crystal orientation, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have (100) crystal planes and (111) crystal planes. In another example embodiment, when the upper surface of the substrate 100 has a (100) crystal plane and the notch of the substrate 100 has a

[110] crystal orientation, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have (111) crystal planes. In another example embodiment, when the upper surface of the substrate 100 has a (100) crystal plane and the notch of the substrate 100 has a

[100] crystal orientation, the first epitaxial pattern 120E and the second epitaxial pattern 220E may have (100) crystal planes.

[0240] According to some example embodiments, the (100) crystal planes of the first epitaxial pattern 120E and the second epitaxial pattern 220E may be parallel in the first direction D1. The (111) crystal planes of the first epitaxial pattern 120E and the second epitaxial pattern 220E intersect the first direction D1 and the third direction D3, and may be tilted relative to the first direction D1.

[0241] According to some example embodiments, the first partial epitaxial pattern 121E and the second partial epitaxial pattern 122E may not contact the first insulating post 310. The first partial epitaxial pattern 121E and the second partial epitaxial pattern 122E are formed by epitaxial growth from the first sacrificial film SL1, therefore the first partial epitaxial pattern 121E and the second partial epitaxial pattern 122E may not be formed on the first insulating post 310 comprising insulating material. The first partial epitaxial pattern 121E and the second partial epitaxial pattern 122E may include facets that intersect the first insulating post 310 and the top first active pattern AP1 at a desired and / or alternative predetermined angle.

[0242] According to some example embodiments, the third epitaxial pattern 221E and the fourth epitaxial pattern 222E may not contact the second insulating post 320. The third epitaxial pattern 221E and the fourth epitaxial pattern 222E are formed by epitaxial growth from the second sacrificial film SL2, therefore the third epitaxial pattern 221E and the fourth epitaxial pattern 222E may not be formed on the second insulating post 320 containing insulating material. The third epitaxial pattern 221E and the fourth epitaxial pattern 222E may include facets that intersect the second insulating post 320 and the top second active pattern AP2 at a desired and / or alternative predetermined angle between the second insulating post 320 protruding upward from the second active pattern AP2 and the top second active pattern AP2.

[0243] Reference Figure 38 A protective film 195 can be formed. The protective film 195 can be formed on the first epitaxial pattern 120E and the second epitaxial pattern 220E. For example, the protective film 195 can contain a carbon-based material. The protective film 195 can include at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), and a silicon nitride film.

[0244] Reference Figure 39 A first contact portion 121C, a second contact portion 122C, a third contact portion 221C, and a fourth contact portion 222C can be formed on the first epitaxial pattern 120E. The first contact portion 121C and the second contact portion 122C can be formed on the second epitaxial pattern 220E by penetrating a portion of the protective film 195. The third contact portion 221C and the fourth contact portion 222C can be formed on the second epitaxial pattern 220E by penetrating a portion of the protective film 195.

[0245] According to some example embodiments, a first portion of contact 121C may be formed on a first portion of epitaxial pattern 121E. A second portion of contact 122C may be formed on a second portion of epitaxial pattern 122E. The first portion of contact 121C and the second portion of contact 122C may be spaced apart by a first insulating post 310.

[0246] According to some example embodiments, the third contact portion 221C may be formed on the third epitaxial pattern 221E. The fourth contact portion 222C may be formed on the fourth epitaxial pattern 222E. The third contact portion 221C and the fourth contact portion 222C may be spaced apart by the second insulating post 320.

[0247] Reference Figure 40 It can remove the protective film 195 (in Figure 39 When the protective film is removed at 195 (in Figure 39When the device is in operation, the first contact portion 121C, the second contact portion 122C, the third contact portion 221C, the fourth contact portion 222C, the first epitaxial pattern 120E, the second epitaxial pattern 220E, and the device isolation film 105 can be exposed.

[0248] Reference Figure 41 A second interlayer insulating film 192 can be formed. The second interlayer insulating film 192 can cover the first partial contact portion 121C, the second partial contact portion 122C, the third partial contact portion 221C, the fourth partial contact portion 222C, the first epitaxial pattern 120E, the second epitaxial pattern 220E, and the device isolation film 105. The second interlayer insulating film 192 can surround the first partial contact portion 121C, the second partial contact portion 122C, the third partial contact portion 221C, the fourth partial contact portion 222C, the first epitaxial pattern 120E, and the second epitaxial pattern 220E.

[0249] Reference Figure 42 It can remove the first sacrificial membrane SL1 (in Figure 41 (in the middle), the first extensional pattern 120E (in Figure 41 (in the middle), the first part of the contact section 121C (in Figure 41 (middle) and the second part contact part 122C (in Figure 41 (in the middle). The first sacrificial membrane SL1 can be removed (in Figure 41 (in the middle), the first part of the extension pattern 121E (in Figure 41 (in the middle) and the first part of the contact 121C (in Figure 41 (in the middle), to form the first gate portion trench 121T. When the first sacrificial film SL1 is removed (in Figure 41 (in the middle), the second part of the extension pattern 122E (in Figure 41 (middle) and the second part contact part 122C (in Figure 41 When (in the middle), a second gate portion trench 122T can be formed. The first active pattern AP1 can be exposed within the first gate portion trench 121T and the second gate portion trench 122T.

[0250] Reference Figure 43 It can form a first insulating film 131, a second insulating film 132, a first gate portion 121, and a second gate portion 122.

[0251] According to some example embodiments, the first insulating film 131 and the first gate portion 121 may be formed in the first gate portion trench 121T (in Figure 42 The first insulating film 131 may surround the first active portion AP1a. The first insulating film 131 may be along the first gate portion trench 121T (in the middle). Figure 42The first gate portion 121 extends from the bottom and side surfaces of the first gate portion 121 and the side surface of the first insulating pillar 310. The first gate portion 121 may fill the first gate portion trench 121T on the first portion insulating film 131 (in the middle). Figure 42 middle).

[0252] According to some example embodiments, the second insulating film 132 and the second gate portion 122 can be formed in the second gate portion trench 122T (in Figure 42 The second insulating film 132 may surround the second active portion Ap1b. The second insulating film 132 may be along the trench 122T of the second gate portion (in the middle). Figure 42 The second gate portion 122 extends from the bottom and side surfaces of the first insulating pillar 310 and the side surface of the second insulating film 132. The second gate portion 122 may fill the second gate portion trench 122T on the second insulating film 132. Figure 42 middle).

[0253] Reference Figure 44 It can remove the second sacrificial membrane SL2 (in Figure 43 (in the middle), the second extensional pattern 220E (in Figure 43 (middle), third part contact part 221C (in) Figure 43 (middle) and fourth part contact part 222C (in Figure 43 (in the middle). When the second sacrificial membrane SL2 is removed (in Figure 43 (in the middle), the third part of the extension pattern 221E (in Figure 43 (in the middle) and the third part contact part 221C (in Figure 43 When the second sacrificial film SL2 is removed (in the middle), a third gate portion trench 221T can be formed. Figure 43 (in the middle), the fourth part extension pattern 222E (in Figure 43 (middle) and fourth part contact part 222C (in Figure 43 When (in the middle), a fourth gate portion trench 222T can be formed. The second active pattern AP2 can be exposed within the third gate portion trench 221T and the fourth gate portion trench 222T.

[0254] Reference Figure 45 It can form a third insulating film 231, a fourth insulating film 232, a third gate portion 221 and a fourth gate portion 222.

[0255] According to some example embodiments, the third insulating film 231 and the third gate portion 221 can be formed in the third gate portion trench 221T (in Figure 44 The third insulating film 231 may surround the third active portion AP2a. The third insulating film 231 may be along the trench 221T of the third gate portion (in the middle). Figure 44The bottom and side surfaces of the third gate portion 221 and the side surface of the second insulating pillar 320 extend from the middle. The third gate portion 221 may fill the third gate portion trench 221T on the third portion insulating film 231 (in the middle). Figure 44 middle).

[0256] According to some example embodiments, the fourth insulating film 232 and the fourth gate portion 222 can be formed in the fourth gate portion trench 222T (in Figure 44 The fourth insulating film 232 may surround the fourth active portion AP2b. The fourth insulating film 232 may be along the fourth gate portion trench 222T (in the middle). Figure 44 The fourth gate portion 222 extends from the bottom and side surfaces of the fourth gate portion (in the middle) and the side surface of the second insulating pillar 320. The fourth gate portion 222 can fill the fourth gate portion trench 222T on the fourth portion insulating film 232 (in the middle). Figure 44 middle).

[0257] Reference Figure 9 A first etch stop film 193 and a third interlayer insulating film 194 can be formed on the second interlayer insulating film 192, and interconnect vias 175 can be formed on the first gate portion 121, the second gate portion 122, the third gate portion 221, and the fourth gate portion 222.

[0258] According to an example embodiment, a method of manufacturing a semiconductor device may include: forming a plurality of first active patterns, a plurality of first source / drain patterns, a plurality of second active patterns, and a plurality of second source / drain patterns on a substrate; the plurality of first active patterns being spaced apart from each other in a first direction intersecting with an upper surface of the substrate; the plurality of first active patterns extending in a second direction intersecting with the first direction; the plurality of first source / drain patterns extending in the first direction and being spaced apart from each other in the second direction; the plurality of first source / drain patterns being connected to opposite sides of the plurality of first active patterns in the second direction; the plurality of second active patterns being spaced apart from the plurality of first active patterns in a third direction, intersecting with the first and second directions; the plurality of second source / drain patterns extending in the first direction and being spaced apart from each other in the second direction; the plurality of second source / drain patterns being connected to opposite sides of the plurality of second active patterns in the second direction; and the plurality of first source / drain patterns being spaced apart from the plurality of second source / drain patterns in a third direction; forming a gate separation structure on the substrate between the plurality of first active patterns and the plurality of second active patterns in the third direction; and forming a structure surrounding the plurality of first active patterns. The first gate electrode comprises at least a portion thereof; and a second gate electrode comprising at least a portion thereof surrounding a plurality of second active patterns, wherein the first gate electrode and the second gate electrode may be formed after the gate separation structure and are spaced apart from the opposite side of the gate separation structure such that the gate separation structure may be located between the first gate electrode and the second gate electrode in a third direction. The first gate electrode may include a first lower pattern and a first upper pattern on the first lower pattern. The first lower pattern may surround the plurality of first active patterns and may protrude outward from the center of one of the plurality of first active patterns in a third direction. The width of the first upper pattern in a third direction may increase as the first upper pattern moves away from the first lower pattern in a first direction. The second gate electrode may include a second lower pattern and a second upper pattern on the second lower pattern. The second lower pattern may surround the plurality of second active patterns and may protrude outward from the center of one of the plurality of second active patterns in a third direction. The width of the second upper pattern in a third direction may increase as the second upper pattern moves away from the second lower pattern in a first direction.

[0259] In some embodiments, both the side surface of the first lower pattern in the third-direction orientation and the side surface of the second lower pattern in the third-direction orientation may include facets.

[0260] In some embodiments, the method may further include: forming a first fin pattern, forming a second fin pattern, and forming a device isolation film on the substrate before forming a plurality of first active patterns, a plurality of first source / drain patterns, a plurality of second active patterns, and a plurality of second source / drain patterns on the substrate. The first fin pattern and the second fin pattern may protrude from the substrate in a first direction through the device isolation film. The first fin pattern and the second fin pattern may extend in a second direction and may be spaced apart from each other in the first direction. A plurality of first active patterns may be formed at the top of the first fin pattern, and a plurality of second active patterns may be formed at the top of the second fin pattern. Forming a first gate electrode and forming a second gate electrode includes: forming a first gate insulating film surrounding the first gate electrode and forming a second gate insulating film surrounding the second gate electrode. A portion of the lower surface of the first gate insulating film and a portion of the lower surface of the second gate insulating film may not contact the upper surface of the device isolation film located below the portion of the lower surface of the first gate insulating film and the portion of the lower surface of the second gate insulating film.

[0261] In some embodiments, the first gate insulating film may extend along the side surface of the first lower pattern, the lower surface of the first lower pattern, and the side surface of the first upper pattern.

[0262] In some embodiments, a first gate insulating film may cover a first side surface of the gate separation structure facing the first gate electrode in a third-party upward direction, and a second gate insulating film may cover a second side surface of the gate separation structure facing the second gate electrode in a third-party upward direction.

[0263] While some exemplary embodiments have been described above with reference to the accompanying drawings, this disclosure is not limited to the above exemplary embodiments and can be made in various forms different from each other. Those skilled in the art to which this disclosure pertains will understand that other embodiments can be implemented without altering the technical spirit or characteristics of this disclosure. Therefore, in all respects, the above exemplary embodiments should be understood as non-limiting examples.

Claims

1. A semiconductor device, comprising: Multiple first source / drain patterns are provided on a substrate, the multiple first source / drain patterns extending in a first direction and spaced apart from each other in a second direction, the first direction intersecting the upper surface of the substrate, and the second direction intersecting the first direction; The first gate electrode is located between the plurality of first source / drain patterns; A first active pattern penetrates the first gate electrode in the second direction, and the first active pattern is connected to the plurality of first source / drain patterns; Multiple second source / drain patterns are spaced apart from the multiple first source / drain patterns in a third direction, which intersects the first direction and the second direction; A second gate electrode is spaced apart from the first gate electrode in the third direction, and the second gate electrode is located between the plurality of second source / drain patterns in the second direction; as well as The second active pattern penetrates the second gate electrode in the second direction, and the second active pattern is connected to the plurality of second source / drain patterns. Wherein, both the first gate electrode on the first side surface in the third direction and the second gate electrode on the second side surface in the third direction include facets.

2. The semiconductor device according to claim 1, further comprising: A gate separation structure is located between the first side surface of the first gate electrode and the second side surface of the second gate electrode. The first side surface of the first gate electrode and the second side surface of the second gate electrode face each other in the third direction.

3. The semiconductor device according to claim 2, wherein, The first portion of the gate separation structure includes the lower surface of the gate separation structure in the first direction. The first portion of the gate separation structure is located between the lowest facet of the first side surface of the first gate electrode and the lowest facet of the second side surface of the second gate electrode, and The width of the first portion decreases as the gate separation structure moves away from the substrate in the first direction.

4. The semiconductor device according to claim 2, further comprising: A first gate insulating film surrounds the first gate electrode and extends along the first side surface of the first gate electrode; as well as A second gate insulating film surrounds the second gate electrode and extends along the second side surface of the second gate electrode.

5. The semiconductor device according to claim 4, wherein, The gate separation structure is covered by the first gate insulating film and the second gate insulating film on the third-side upward side surface.

6. The semiconductor device according to claim 2, further comprising: A device isolation film is located on the substrate and below the gate separation structure. In the plan view, the device isolation film is located between the first active pattern and the second active pattern in the third direction.

7. The semiconductor device according to claim 6, wherein, The gate separation structure is in contact with the upper surface of the device isolation film.

8. The semiconductor device according to claim 1, wherein, A portion of the first side surface of the first gate electrode and a portion of the second side surface of the second gate electrode are parallel in the first direction.

9. The semiconductor device according to claim 1, wherein, The first gate electrode includes a first lower pattern in the first direction and a first upper pattern on the first lower pattern. The first lower pattern surrounds the first active pattern; The width of the first upper pattern in the third direction increases as the first upper pattern moves away from the substrate in the first direction; and The width of the first lower pattern in the third direction widens and then narrows as the first lower pattern moves away from the substrate in the first direction.

10. The semiconductor device according to claim 1, wherein, The first active pattern includes a plurality of first sheets stacked in the first direction; and The second active pattern includes a plurality of second sheets stacked in the first direction.

11. The semiconductor device according to claim 1, wherein, The facets in the first side surface of the first gate electrode are aligned with the crystal planes of the plurality of first source / drain patterns, or The facets in the second side surface of the second gate electrode are aligned with the crystal faces of the plurality of second source / drain patterns.

12. A semiconductor device, comprising: A first active pattern is located above a substrate in a first direction, which intersects with the upper surface of the substrate, and the first active pattern extends in a second direction, which intersects with the first direction; A first gate electrode surrounds at least a portion of the first active pattern; A second active pattern is located above the substrate in the first direction, and the second active pattern is spaced apart from the first active pattern in a third direction, the third direction intersecting the first direction and the second direction; A second gate electrode is spaced apart from the first gate electrode in the third direction and surrounds at least a portion of the second active pattern; as well as A gate separation structure is located between the first gate electrode and the second gate electrode in the third direction, wherein, The first gate electrode includes a first lower pattern and a first upper pattern on the first lower pattern. The first lower pattern surrounds the first active pattern and protrudes outward from the center of the first active pattern in the third direction. The width of the first upper pattern in the third direction increases as the first upper pattern moves further away from the first lower pattern in the first direction. The second gate electrode includes a second lower pattern and a second upper pattern on the second lower pattern. The second lower pattern surrounds the second active pattern and protrudes outward from the center of the second active pattern in the third direction. The width of the second upper pattern in the third direction increases as the second upper pattern moves away from the second lower pattern in the first direction.

13. The semiconductor device according to claim 12, wherein, Both the first lower pattern and the second lower pattern include facets on the third-direction side surface.

14. The semiconductor device according to claim 12, further comprising: A device isolation film is provided on the substrate and located below the gate separation structure, wherein the device isolation film is located between the first active pattern and the second active pattern in the third direction. A first gate insulating film surrounds the first gate electrode; as well as A second gate insulating film surrounds the second gate electrode. The lower surfaces of the first gate insulating film and the second gate insulating film do not contact the upper surface of the device isolation film.

15. The semiconductor device according to claim 14, wherein, The first gate insulating film extends along the side surface of the first lower pattern, the lower surface of the first lower pattern, and the side surface of the first upper pattern.

16. The semiconductor device according to claim 14, wherein, The first gate insulating film covers the first side surface of the gate separation structure facing the first gate electrode in a third-party upward direction, and The second gate insulating film covers the second side surface of the gate separation structure facing the second gate electrode on the third-party upward side.

17. The semiconductor device according to claim 12, wherein, The first inner side of the first active pattern faces the second active pattern from the third-party direction. The first outer side of the first active pattern is opposite to the first inner side of the first active pattern in the third direction, and The thickness of the portion of the first gate electrode located on the first outer side of the first active pattern in the third direction in the third direction is the same as the thickness of the portion of the first gate electrode located on the first inner side of the first active pattern in the third direction in the third direction.

18. The semiconductor device according to claim 17, wherein, The second inner side of the second active pattern faces the first active pattern from the third-party direction. The second outer side of the second active pattern is opposite to the second inner side of the second active pattern in the third direction, and The thickness of the portion of the second gate electrode located on the second outer side of the second active pattern in the third direction is the same as the thickness of the portion of the first gate electrode located on the first outer side of the first active pattern in the third direction.

19. The semiconductor device of claim 12, further comprising: The first source / drain pattern is spaced apart from the first gate electrode in the second direction. The first source / drain pattern is connected to the first active pattern in the second direction.

20. A semiconductor device, comprising: Multiple first source / drain patterns are provided on a substrate, the multiple first source / drain patterns extending in a first direction and spaced apart from each other in a second direction, the first direction intersecting the upper surface of the substrate, and the second direction intersecting the first direction; A first gate electrode is located between the plurality of first source / drain patterns in the second direction; A first gate insulating film surrounds the lower surface of the first gate electrode and the side surface of the first gate electrode; A first active pattern penetrates the first gate electrode in the second direction, and the first active pattern is connected to the plurality of first source / drain patterns; Multiple second source / drain patterns are spaced apart from the multiple first source / drain patterns in a third direction, which intersects the first direction and the second direction; A second gate electrode is spaced apart from the first gate electrode in the third direction, and the second gate electrode is located between the plurality of second source / drain patterns in the second direction; A second gate insulating film surrounds the lower surface of the second gate electrode and the side surface of the second gate electrode; as well as The second active pattern penetrates the second gate electrode in the second direction, and the second active pattern is connected to the plurality of second source / drain patterns. Wherein, the first gate electrode on the first side surface in the third direction and the second gate electrode on the second side surface in the third direction both include facets with (100) crystal planes.

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