Semiconductor device with source / drain regions surrounding gate structure

Abstract

A semiconductor device includes a gate structure, a first source / drain region, a second source / drain region, and a channel region. The gate structure has a central portion and a plurality of connecting portions. The plurality of connecting portions protrude from the central portion as viewed in plan. The first source / drain region surrounds the gate structure as viewed in plan. The second source / drain region is surrounded by the gate structure. The channel region is under the first source / drain region as viewed in cross-section, and surrounds the gate structure as viewed in plan.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 63 / 793,841 (priority date: April 24, 2025) and U.S. Patent Application No. 19 / 407,563 (priority date: December 3, 2025), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device having a source / drain region-around-gate structure, and more specifically, to a semiconductor device having a source / drain region-around-gate structure that can effectively form a wider channel in a transistor. Background Technology

[0003] Semiconductor components are essential in many modern applications. With the advancement of electronic technology, semiconductor components have become smaller in size while providing better functionality and incorporating more integrated circuits.

[0004] In semiconductor power devices, laterally diffused metal-oxide-semiconductor (LDMOS), double diffused metal-oxide-semiconductor (DDMOS), and vertical diffused metal-oxide-semiconductor (VDMOS) are commonly used in radio frequency (RF) power amplifiers and high-frequency power amplifiers. Because LDMOS, DDMOS, and VDMOS each have different characteristics and advantages, suitable components can be designed and selected according to the application requirements. However, in the rapidly evolving semiconductor field, while component sizes are shrinking, performance requirements are becoming increasingly stringent (e.g., generating higher on-state current within the same unit area). Therefore, in specific situations, relying solely on the advantages of traditional LDMOS, DDMOS, or VDMOS components is insufficient to meet the demands of new technology nodes. Overcoming the limitations of traditional components has thus become a crucial issue in this field.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes a gate structure, a first source / drain region, a second source / drain region, and a channel region. The gate structure has a central portion and a plurality of connection portions. Viewed from top, the plurality of connection portions protrude from the central portion. Viewed from top, the first source / drain region surrounds the gate structure. The second source / drain region is surrounded by the gate structure. Viewed in cross-section, the channel region is below the first source / drain region, and viewed from top, it surrounds the gate structure.

[0007] Another aspect of this disclosure provides a semiconductor device including a first transistor and a second transistor. Each of the first and second transistors includes a gate structure, a first source / drain region, a second source / drain region, and a channel region. The gate structure has a central portion and a plurality of connection portions. Viewed from top, the plurality of connection portions protrude from the central portion. Viewed from top, the first source / drain region surrounds the gate structure. The second source / drain region is surrounded by the gate structure. Viewed in cross-section, the channel region is below the first source / drain region, and viewed from top, it surrounds the gate structure. The first and second transistors are connected in parallel.

[0008] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0009] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments and claims. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0010] Figure 1 This is a top view schematic diagram of a semiconductor element according to some embodiments of the present disclosure.

[0011] Figure 2 This is a schematic cross-sectional view of a semiconductor element according to some embodiments of the present disclosure.

[0012] Figure 3 This is a schematic cross-sectional view of a semiconductor element according to some embodiments of the present disclosure.

[0013] Figure 4 This is a schematic diagram of a semiconductor element according to some embodiments of the present disclosure.

[0014] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a schematic diagram of a semiconductor element according to other embodiments of the present disclosure.

[0015] List of reference numerals

[0016] 10: Semiconductor components

[0017] 11: Semiconductor components

[0018] 12: Semiconductor components

[0019] 13: Semiconductor components

[0020] 14: Semiconductor components

[0021] 15: Semiconductor components

[0022] 16: Semiconductor components

[0023] 20: Semiconductor components

[0024] 30: Semiconductor components

[0025] 31: Semiconductor components

[0026] 32: Semiconductor components

[0027] 33: Semiconductor components

[0028] 34: Semiconductor components

[0029] 35: Semiconductor components

[0030] 36: Semiconductor components

[0031] 40: Semiconductor components

[0032] 50: Semiconductor components

[0033] 51: Semiconductor components

[0034] 52: Semiconductor components

[0035] 53: Semiconductor components

[0036] 54: Semiconductor components

[0037] 55: Semiconductor components

[0038] 56: Semiconductor components

[0039] 60: Semiconductor components

[0040] 70: Semiconductor components

[0041] 71: Semiconductor components

[0042] 72: Semiconductor components

[0043] 74: Semiconductor components

[0044] 75: Semiconductor components

[0045] 76: Semiconductor components

[0046] 80: Semiconductor components

[0047] 90: Semiconductor components

[0048] 91: Semiconductor components

[0049] 92: Semiconductor components

[0050] 93: Semiconductor components

[0051] 94: Semiconductor components

[0052] 95: Semiconductor components

[0053] 96: Semiconductor components

[0054] 100: Source / Drain Region

[0055] 100B: Bottom surface

[0056] 200: Source / Drain Region

[0057] 200T: Top surface

[0058] 200B: Bottom surface

[0059] 300: Gate structure

[0060] 300a: Circular section

[0061] 300b: Connection part

[0062] 300c: Elliptical portion

[0063] 300d: Hexagonal section

[0064] 300S1: Sidewall

[0065] 300S2: Sidewall

[0066] 300B: Bottom surface

[0067] 301: Gate structure

[0068] 302: Gate structure

[0069] 304: Gate structure

[0070] 305: Gate structure

[0071] 310: Insulator

[0072] 310T: Top surface

[0073] 320: Gate conductor

[0074] 400: Contact Area

[0075] 401: Contact Area

[0076] 402: Contact Area

[0077] 404: Contact Area

[0078] 405: Contact Area

[0079] 400B: Bottom surface

[0080] 500: Contact Area

[0081] 500B: Bottom surface

[0082] 500T: Top surface

[0083] 600: Dual diffusion region

[0084] 700: Ontology area

[0085] 800: Passage Area

[0086] 1010: Semiconductor components

[0087] 1020: Semiconductor Components

[0088] 1021: Semiconductor Components

[0089] 1022: Semiconductor Components

[0090] 1023: Semiconductor Components

[0091] 1024: Semiconductor Components

[0092] 1025: Semiconductor components

[0093] 1026: Semiconductor Components

[0094] 1030: Semiconductor Components

[0095] 1040: Semiconductor Components

[0096] 1041: Semiconductor Components

[0097] 1042: Semiconductor Components

[0098] 1043: Semiconductor Components

[0099] 1044: Semiconductor Components

[0100] 1045: Semiconductor Components

[0101] 1046: Semiconductor Components

[0102] S1: Inner wall

[0103] S2: Top surface

[0104] S3: Lateral wall

[0105] S4: Bottom surface

[0106] S5: Curved sidewall

[0107] X: X-axis

[0108] Y: Y-axis

[0109] Z: Z-axis Detailed Implementation

[0110] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0111] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagrams, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0112] Figure 1This is a top view schematic diagram of a semiconductor element 10 according to some embodiments of the present disclosure. For ease of understanding, the top view schematic diagram is perpendicular to the plane defined by the X-axis and Y-axis (i.e., Figure 2 Observe along the Z-axis (as shown). The X-axis, Y-axis, and Z-axis are perpendicular to each other.

[0113] In some embodiments, the semiconductor element 10 is a transistor or part of a transistor. Viewed from above, the semiconductor element 10 includes a first source / drain region 100, a second source / drain region 200, a gate structure 300, a first contact region 400, and a second contact region 500.

[0114] The gate structure 300 is generally circular. Specifically, the gate structure 300 has a circular portion 300a and a plurality of connection portions 300b. The plurality of connection portions 300b protrude from the circular portion 300a and are evenly distributed around the circular portion 300a. In some embodiments, the gate structure 300 has four connection portions 300b. Two connection portions 300b are aligned with each other along the X-axis, while the other two connection portions 300b are aligned with each other along the Y-axis.

[0115] The gate structure 300 includes an insulator 310 and a gate conductor 320. Viewed from top, the gate conductor 320 is covered by the insulator 310. Therefore, the gate conductor 320 is indicated by dashed lines and described in subsequent figures.

[0116] The first source / drain region 100 surrounds the gate structure 300. For example... Figure 1 As shown, the first source / drain region 100 includes several portions separated by the connection portion 300b. In some embodiments, the number of portions of the first source / drain region 100 is equal to the number of portions of the connection portion 300b.

[0117] The second source / drain region 200 is disposed in the center of the gate structure 300. In other words, the second source / drain region 200 is surrounded by the gate structure 300. The first source / drain region 100 and the second source / drain region 200 are separated by the gate structure 300. In some embodiments, the second source / drain region 200 is circular. In some embodiments, the diameter D1 of the second source / drain region 200 is larger than the width W1 of the connection portion 300b.

[0118] The first contact region 400 is located above the first source / drain region 100 (shown in...). Figure 3The first contact region 400 is electrically coupled to the first source / drain region 100. As described above, the first source / drain region 100 includes several portions, and the first contact region 400 includes several portions corresponding to the portions of the first source / drain region 100. The number of portions of the first contact region 400 is equal to the number of portions of the first source / drain region 100. The first contact region 400 is surrounded by the first source / drain region 100. In some embodiments, the first contact region 400 is rectangular. The portions of the first contact region 400 have the same shape. The first contact region 400 and the gate structure 300 are separated by the first source / drain region 100. In some embodiments, the portions of the first contact region 400 are configured to provide contact for the semiconductor element 10 to connect to the outside. The portions of the first contact region 400 receive the same signal (or the same control voltage); in other words, the entire first source / drain region 100 is configured to receive the same signal by the first contact region 400.

[0119] From a top view, the second contact region 500 is surrounded by the second source / drain region 200. The second contact region 500 is positioned above the second source / drain region 200 (shown in...). Figure 2 and Figure 3 The second contact region 500 is electrically coupled to the second source / drain region 200. The second contact region 500 is rectangular. In some embodiments, the second contact region 500 is disposed in the center of the second source / drain region 200. The second contact region 500 and the gate structure 300 are separated by the second source / drain region 200. The second contact region 500 is configured to provide a contact for the semiconductor element 10 to connect to the outside.

[0120] In some embodiments, the first source / drain region 100 and the second source / drain region 200 are heavily doped regions. In some embodiments, the first source / drain region 100 and the second source / drain region 200 are n-type doped regions. In some embodiments, the first source / drain region 100 and the second source / drain region 200 are n-type heavily doped regions.

[0121] In some embodiments, contact regions 400 and 500 are heavily doped regions. In some embodiments, contact regions 400 and 500 are p-type doped regions. In some embodiments, contact regions 400 and 500 are heavily p-type doped regions.

[0122] See Figure 2 . Figure 2 For semiconductor element 10 according to certain embodiments of this disclosure along Figure 1 A schematic diagram of the cross-section of the midline segment AA.

[0123] The semiconductor element 10 further includes a double diffusion region 600, a body region 700, and a channel region 800. The double diffusion region 600 is disposed below the second source / drain region 200 and extends from the bottom surface 200B of the second source / drain region 200 along the sidewall 300S1 of the gate structure 300 to the bottom surface 300B of the gate structure 300.

[0124] The body region 700 is disposed below the first source / drain region 100, the gate structure 300, and the second source / drain region 200. In some embodiments, the body region 700 may be a substrate of the semiconductor device 10, or a semiconductor layer disposed above the substrate of the semiconductor device 10.

[0125] In some embodiments, the substrate of the semiconductor element 10 includes a bulk semiconductor substrate composed of at least one semiconductor material. The bulk semiconductor substrate may be formed of, for example, a single-element semiconductor (such as silicon or germanium), a compound semiconductor (such as silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors, or group II-VI compound semiconductors), or a combination thereof. In some embodiments, the substrate includes an insulating silicon-based structure, comprising, from bottom to top: a support substrate, an insulating layer, and a top semiconductor material layer. The support substrate and the top semiconductor material layer may be formed of the same material as the aforementioned bulk semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides of silicon oxide, silicon nitride, and boron nitride in any order. The thickness of the insulating layer may be between 10 nanometers and about 200 nanometers. This insulating layer can eliminate leakage current between adjacent components in the substrate.

[0126] The channel region 800 can be formed by applying a control current to the gate conductor 320, causing charge to accumulate in the body region 700 surrounding the sidewall 300S2 of the gate structure 300. In some embodiments, the channel region 800 extends from the bottom surface 100B of the first source / drain region 100 along the sidewall 300S2 to the bottom surface 300B. When the channel region 800 is formed, the first source / drain region 100 and the second source / drain region 200 can be electrically coupled to each other through the channel region 800.

[0127] In some embodiments, the double-diffusion region 600 refers to a region formed in a semiconductor layer by sequentially diffusing two dopants with opposite conductivity into it, thereby forming a defined junction structure for use in a transistor device. In some embodiments, the double-diffusion process includes first diffusing one type of dopant (i.e., p-type) into the semiconductor layer, and then diffusing another type of dopant with opposite conductivity (i.e., n-type) into the previously formed region. This sequential diffusion creates dopant concentration gradients in the horizontal and vertical directions, forming a region where the ranges of the two dopants overlap.

[0128] The double-diffused region 600 is configured to define the channel region 800 and the source / drain junction structural elements of the semiconductor element 10. Specifically, the channel region 800 is connected to the first source / drain region 100 and the double-diffused region 600. In some embodiments, the double-diffused region 600 allows for precise control of the channel length and doping concentration of the channel region 800, thereby affecting the threshold voltage, on-resistance, and breakdown voltage characteristics of the semiconductor element 10. In some embodiments, the double-diffused region 600 allows for the formation of a shallow and well-controlled channel region 800 near the heavily doped source / drain regions (i.e., the first source / drain region 100 and the second source / drain region 200), thereby reducing parasitic resistance and improving switching speed to enhance the performance of the semiconductor element 10.

[0129] The dual diffusion region 600 facilitates the horizontal (along the X-axis) extension of the channel length below the gate structure 300, thereby improving electrostatic control and enabling the semiconductor element 10 to withstand higher voltages without premature breakdown.

[0130] The gate structure 300 includes an insulator 310 and a gate conductor 320. The gate conductor 320 is surrounded by the insulator 310. Therefore, the gate conductor 320 is electrically insulated from the first source / drain region 100, the second source / drain region 200, the double-diffused region 600, the channel region 800, and the body region 700.

[0131] The gate conductor 320 has an inner sidewall S1 facing the second source / drain region 200, a top surface S2, an outer sidewall S3 opposite to the inner sidewall S1, a bottom surface S4 opposite to the top surface S2, and a curved sidewall S5. The top surface S2 connects the inner sidewall S1 and the outer sidewall S3. The bottom surface S4 connects the inner sidewall S1 and the curved sidewall S5 and is generally parallel to the top surface S2. The curved sidewall S5 connects the bottom surface S4 and the outer sidewall S3. In some embodiments, the curved sidewall S5 is curved outward.

[0132] In some embodiments, the top surface S2 and the bottom surface S4 are parallel to the X-axis, and the inner sidewall S1 and the outer sidewall S3 are parallel to the Y-axis.

[0133] like Figure 2As shown, the top surface 310T of the insulator 310, the top surface 200T of the second source / drain region 200, and the top surface 500T of the contact region 500 are coplanar with each other.

[0134] like Figure 2 As shown, the first source / drain region 100 extends below the connection portion 300b of the gate structure 300.

[0135] refer to Figure 3 . Figure 3 For semiconductor element 10 according to some embodiments of this disclosure Figure 1 A schematic diagram of the cross-section of the midline segment BB.

[0136] In some embodiments, the double diffusion region 600, the body region 700, the channel region 800, and the gate conductor 320 are radially symmetrical along the Z-axis passing through the center of the second source / drain region 200. Therefore, Figure 2 and Figure 3 The dual diffusion region 600, body region 700, channel region 800 and gate conductor 320 shown are generally similar in shape.

[0137] The cross-sectional view along line segment BB shows that contact area 400 is located above the first source / drain region 100 and is in direct contact with the first source / drain region 100.

[0138] In some embodiments, the bottom surface 400B of the contact area 400 and the bottom surface 200B are coplanar with each other. In other embodiments, the bottom surface 400B may be coplanar with the bottom surface 500B of the contact area 500, and the bottom surface 100B may be coplanar with the bottom surface 200B.

[0139] Since the channel region 800 is formed by applying a control voltage to the gate conductor 320, the shape of the channel region 800 is related to the shape of the gate conductor 320. Specifically, from a top view, the gate conductor 320 is annular, therefore, from a top view, the channel region 800 is also annular.

[0140] In some prior art, the spatial arrangement of semiconductor devices does not optimize channel distribution, limiting channel width and thus restricting the current that can be conducted. Compared to these prior art techniques, this disclosure employs a ring-shaped channel region 800, which effectively achieves a better channel distribution. The channel region 800 in this disclosure has a larger equivalent width, and therefore can achieve a higher conduction current.

[0141] Furthermore, the semiconductor device 10 of this disclosure combines the advantages of LDMOS and VDMOS, enabling it to operate at higher frequency signals, be manufactured with higher integration density, and be compatible with CMOS. Therefore, increasing the on-current in the channel region 800 also facilitates the miniaturization of the semiconductor device 10 of this disclosure.

[0142] See Figure 4 . Figure 4 This is a schematic diagram of a semiconductor element 20 according to some embodiments of the present disclosure.

[0143] Semiconductor element 20 includes a plurality of semiconductor elements 10. In some embodiments, the length and width of semiconductor element 10 may be equal, that is, semiconductor element 10 is approximately square. Figure 4 The semiconductor element 20 shown includes six semiconductor elements 10; however, this disclosure is not limited thereto, and the semiconductor element 20 may include any number of semiconductor elements 10.

[0144] For ease of understanding, the semiconductor elements 10 of semiconductor element 20 are labeled as 11, 12, 13, 14, 15 and 16 respectively.

[0145] Semiconductor elements 11, 12, and 13 are arranged in the same column along the X-axis, while semiconductor elements 14, 15, and 16 are arranged in another column below semiconductor elements 11, 12, and 13 along the X-axis. The semiconductor elements 10 are interconnected; in other words, there are no gaps between adjacent semiconductor elements 10.

[0146] In some embodiments, the contact regions 400 of semiconductor elements 10 are electrically coupled to each other, and the contact regions 400 of adjacent semiconductor elements 10 are in direct contact with each other. For example, the contact regions 400 of semiconductor elements 11, 12, 14, and 15 (also designated as 401, 402, 404, and 405, respectively) are in contact with each other. In some embodiments, contact regions 401, 402, 404, and 405 are monolithic structures. In some embodiments, adjacent contact regions 400 in semiconductor element 20 are monolithic structures.

[0147] In some embodiments, the gate structures 300 of semiconductor elements 10 are interconnected. For example, the gate structure 300 of semiconductor element 12 (also designated 302) is interconnected with the gate structures 300 of adjacent semiconductor elements 11, 14, and 15 (also designated 301, 304, and 305, respectively). Specifically, the gate structure 302 is connected to the gate structure 300 of the adjacent semiconductor element 10 through a connection portion 300b. The connection portions 300b of the adjacent semiconductor elements 10 are aligned and in contact with each other. In some embodiments, the insulator 310 of semiconductor elements 11 to 16 is a monolithic structure.

[0148] In some embodiments, the gate conductors 320 of the gate structure 300 of the semiconductor element 20 are configured to receive the same control voltage. In some embodiments, the gate conductors 320 of the gate structure 300 of the semiconductor element 20 are electrically coupled to each other.

[0149] In some embodiments, the first source / drain regions 100 of semiconductor element 10 are interconnected with each other. For example, the first source / drain region 100 (also designated as 102) of semiconductor element 12 is interconnected with the first source / drain regions 100 (also designated as 101, 103 and 105, respectively) of adjacent semiconductor elements 11, 13 and 15.

[0150] Since the contact regions 400 are electrically coupled to each other, the first source / drain regions 100 of the semiconductor element 20 are electrically coupled to each other and receive the same signal from the contact regions 400.

[0151] In some embodiments, the contact regions 400 of the semiconductor elements 10 of the semiconductor element 20 are electrically coupled to each other and receive the same signal. Correspondingly, the second source / drain regions 200 of the semiconductor elements 10 of the semiconductor element 20 are electrically coupled to each other and configured to receive the same signal from the contact regions 400. In some embodiments, semiconductor element 20 is a transistor, which is equivalent to a parallel connection of semiconductor element 10. Compared to a single semiconductor element 10, semiconductor element 20 can conduct higher currents through a channel region with an equivalent width that is approximately six times the width of channel region 800.

[0152] The shape of semiconductor element 10 is not limited to Figures 1 to 4 The structure. In some embodiments, such as Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 Some components of semiconductor element 10 have the same characteristics as... Figures 1 to 4 Different shapes with different structures. Please see Figures 5 to 16 .

[0153] Figure 5 This is a schematic diagram of a semiconductor element 30 according to some embodiments of the present disclosure. Semiconductor element 30 is similar to semiconductor element 10. Figures 1 to 4 Compared to the semiconductor element 10 shown, the gate structure 300 of the semiconductor element 30 is roughly elliptical when viewed from above.

[0154] In some embodiments, the gate structure 300 of the semiconductor element 30 has a connection portion 300b and an elliptical portion 300c (instead of a circular portion 300a). The connection portion 300b protrudes from the elliptical portion 300c and is evenly distributed around the elliptical portion 300c.

[0155] Since the gate structure 300 is basically elliptical, the gate conductor 320 of the semiconductor element 30 and the channel region 800 of the semiconductor element 30 are approximately elliptical when viewed from above.

[0156] It should be noted that the other components in semiconductor element 30 are similar to those in semiconductor element 10, therefore, for the sake of brevity, the details of these components are omitted here.

[0157] Figure 6 This is a schematic diagram of a semiconductor element 40 according to some embodiments of the present disclosure. The semiconductor element 40 includes a plurality of semiconductor elements 30. In some embodiments, the semiconductor elements 30 are approximately square. Figure 6 The semiconductor element 40 shown includes six semiconductor elements 30; however, this disclosure is not limited thereto, and the semiconductor element 40 may include any number of semiconductor elements 30. For ease of understanding, the semiconductor elements 30 of the semiconductor element 40 are designated as 31, 32, 33, 34, 35, and 36, respectively.

[0158] Similar to semiconductor element 20, semiconductor element 40 uses semiconductor element 30 as a transistor.

[0159] Figure 7 This is a schematic diagram of a semiconductor element 50 according to some embodiments of the present disclosure. Semiconductor element 50 is similar to semiconductor element 10. Figures 1 to 4 Compared to the semiconductor element 10 shown, the gate structure 300 of the semiconductor element 50 is approximately hexagonal when viewed from above. In some embodiments, the gate structure 300 of the semiconductor element 50 may be a convex polygon.

[0160] In some embodiments, the gate structure 300b of the semiconductor element 50 has a plurality of connection portions 300b and a hexagonal portion 300d (rather than a circular portion 300a). The connection portions 300b protrude from the hexagonal portion 300d and are evenly distributed around the hexagonal portion 300d.

[0161] Since the gate structure 300 is basically hexagonal, the gate conductor 320 of the semiconductor element 50 and the channel region 800 of the semiconductor element 50 are approximately hexagonal when viewed from above.

[0162] It should be noted that the other components in semiconductor element 50 are similar to those in semiconductor element 10, therefore, for the sake of brevity, the details of these components are omitted here.

[0163] Figure 8 This is a schematic diagram of a semiconductor element 60 according to some embodiments of the present disclosure. The semiconductor element 60 includes a plurality of semiconductor elements 50. In some embodiments, the semiconductor elements 50 are approximately square. Figure 8The semiconductor element 60 shown includes six semiconductor elements 50; however, this disclosure is not limited thereto, and the semiconductor element 60 may include any number of semiconductor elements 50. For ease of understanding, the semiconductor elements 50 of the semiconductor element 60 are designated as 51, 52, 53, 54, 55, and 56, respectively.

[0164] Similar to semiconductor element 20, semiconductor element 60 uses semiconductor element 50 as a transistor.

[0165] Figure 9 This is a schematic diagram of a semiconductor element 70 according to some embodiments of the present disclosure. Semiconductor element 70 is similar to semiconductor element 10. Figures 1 to 4 Compared to the semiconductor element 10 shown, the second source / drain region 200 of the semiconductor element 70 is approximately elliptical when viewed from above.

[0166] It should be noted that the other components in semiconductor element 70 are similar to those in semiconductor element 10, therefore, for the sake of brevity, the details of these components are omitted here.

[0167] Figure 10 This is a schematic diagram of a semiconductor element 80 according to some embodiments of the present disclosure. The semiconductor element 80 includes a plurality of semiconductor elements 70. In some embodiments, the semiconductor elements 70 are approximately square. Figure 10 The semiconductor element 80 shown includes six semiconductor elements 70; however, this disclosure is not limited thereto, and the semiconductor element 80 may include any number of semiconductor elements 70. For ease of understanding, the semiconductor elements 70 of the semiconductor element 80 are designated as 71, 72, 73, 74, 75, and 76, respectively.

[0168] Similar to semiconductor element 20, semiconductor element 80 uses semiconductor element 70 as a transistor.

[0169] Figure 11 This is a schematic diagram of a semiconductor element 90 according to some embodiments of the present disclosure. Semiconductor element 90 is similar to semiconductor element 10. Figures 1 to 4 Compared to the semiconductor element 10 shown, the second source / drain region 200 of the semiconductor element 90 is approximately hexagonal when viewed from above.

[0170] It should be noted that the other components in semiconductor element 90 are similar to those in semiconductor element 10, therefore, for the sake of brevity, the details of these components are omitted here.

[0171] Figure 12 This is a schematic diagram of a semiconductor element 1010 according to some embodiments of the present disclosure. The semiconductor element 1010 includes a plurality of semiconductor elements 90. In some embodiments, the semiconductor elements 90 are approximately square. Figure 12The semiconductor element 1010 shown includes six semiconductor elements 90; however, this disclosure is not limited thereto, and the semiconductor element 1010 may include any number of semiconductor elements 90. For ease of understanding, the semiconductor elements 90 of the semiconductor element 1010 are designated as 91, 92, 93, 94, 95, and 96, respectively.

[0172] Similar to semiconductor element 20, semiconductor element 1010 uses semiconductor element 90 as a transistor.

[0173] Figure 13 This is a schematic diagram of a semiconductor element 1020 according to some embodiments of the present disclosure. Semiconductor element 1020 is similar to semiconductor element 10. Figures 1 to 4 Compared to the semiconductor element 10 shown, the contact area 400 of the semiconductor element 1020, when viewed from above, is a quarter circle located at each corner of the semiconductor element 1020, and the arc of these quarter circles bulges outward toward the second source / drain region 200.

[0174] In various embodiments, the contact area 400 of the semiconductor element 1020, viewed from above, may be a quarter-ellipse (not shown) located at each corner of the semiconductor element 1020.

[0175] Figure 14 This is a schematic diagram of a semiconductor element 1030 according to some embodiments of the present disclosure. The semiconductor element 1030 includes a plurality of semiconductor elements 1020. In some embodiments, the semiconductor elements 1020 are approximately square. Figure 14 The semiconductor element 1030 shown includes six semiconductor elements 1020; however, this disclosure is not limited thereto, and the semiconductor element 1030 may include any number of semiconductor elements 1020. For ease of understanding, the semiconductor elements 1020 of the semiconductor element 1030 are designated as 1021, 1022, 1023, 1024, 1025, and 1026, respectively.

[0176] Similar to semiconductor element 20, semiconductor element 1030 uses semiconductor element 1020 as a transistor.

[0177] In some embodiments, the contact regions 400 of semiconductor elements 1020 are electrically coupled to each other, and the contact regions 400 of adjacent semiconductor elements 1020 are in direct contact with each other. For example, the contact regions 400 of semiconductor elements 1021, 1022, 1024, and 1025 (also designated as 401, 402, 404, and 405, respectively) are in contact with each other. Figure 14 As shown, contact areas 401, 402, 404, and 405 form a circle. In some embodiments, contact areas 401, 402, 404, and 405 are single-unit structures. In some embodiments, adjacent contact areas 400 in the semiconductor element 1030 are single-unit structures.

[0178] Figure 15 This is a schematic diagram of a semiconductor element 1040 according to some embodiments of the present disclosure. Semiconductor element 1040 is similar to semiconductor element 10. Figures 1 to 4 Compared to the semiconductor element 10 shown, the contact areas 400 of the semiconductor element 1040, viewed from above, are quadrilaterals located at each corner of the semiconductor element 1040. In some embodiments, the quadrilateral is a quarter of a regular hexagon. In various embodiments, the quadrilateral is a quarter of any hexagon.

[0179] Figure 16 This is a schematic diagram of a semiconductor element 1050 according to some embodiments of the present disclosure. The semiconductor element 1050 includes a plurality of semiconductor elements 1040. In some embodiments, the semiconductor elements 1040 are approximately square. Figure 16 The semiconductor element 1050 shown includes six semiconductor elements 1040; however, this disclosure is not limited thereto, and the semiconductor element 1050 may include any number of semiconductor elements 1040. For ease of understanding, the semiconductor elements 1040 of the semiconductor element 1050 are designated as 1041, 1042, 1043, 1044, 1045, and 1046, respectively.

[0180] Similar to semiconductor element 20, semiconductor element 1050 uses semiconductor element 1040 as a transistor.

[0181] In some embodiments, the contact regions 400 of semiconductor elements 1050 are electrically coupled to each other, and the contact regions 400 of adjacent semiconductor elements 1040 are in direct contact with each other. For example, the contact regions 400 of semiconductor elements 1041, 1042, 1044, and 1045 (also designated as 401, 402, 404, and 405, respectively) are in contact with each other. Figure 16 As shown, contact regions 401, 402, 404, and 405 form a hexagon. In some embodiments, contact regions 401, 402, 404, and 405 are single-unit structures. In some embodiments, adjacent contact regions 400 in the semiconductor element 1050 are single-unit structures.

[0182] In various embodiments, the second source / drain region 200, gate structure 300, and contact region 400 of the semiconductor element may be used. Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 15 The structures shown are freely combinable. For example, the semiconductor element of this disclosure may include... Figure 5 The gate structure 300 shown Figure 9 The second source / drain region 200 shown is... Figure 13The contact area 400 is shown, while the other components are largely the same as those of semiconductor element 10.

[0183] One aspect of this disclosure provides a semiconductor device including a gate structure, a first source / drain region, a second source / drain region, and a channel region. The gate structure has a central portion and a plurality of connection portions. Viewed from top, the plurality of connection portions protrude from the central portion. Viewed from top, the first source / drain region surrounds the gate structure. The second source / drain region is surrounded by the gate structure. Viewed in cross-section, the channel region is below the first source / drain region, and viewed from top, it surrounds the gate structure.

[0184] Another aspect of this disclosure provides a semiconductor device including a first transistor and a second transistor. Each of the first and second transistors includes a gate structure, a first source / drain region, a second source / drain region, and a channel region. The gate structure has a central portion and a plurality of connection portions. Viewed from top, the plurality of connection portions protrude from the central portion. Viewed from top, the first source / drain region surrounds the gate structure. The second source / drain region is surrounded by the gate structure. Viewed in cross-section, the channel region is below the first source / drain region, and viewed from top, it surrounds the gate structure. The first and second transistors are connected in parallel.

[0185] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0186] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A gate structure having a central portion and a plurality of connection portions, wherein, viewed from top view, the plurality of connection portions protrude from the central portion; A first source / drain region, viewed from above, surrounds the gate structure; A second source / drain region is surrounded by the gate structure; and A channel region, viewed in cross-section, is located below the first source / drain region; viewed from above, the channel region surrounds the gate structure.

2. The semiconductor device of claim 1, further comprising: A first contact region is located above the first source / drain region; as well as A second contact region is located above the second source / drain region.

3. The semiconductor element as claimed in claim 2, wherein, viewed from above, the first contact area is rectangular or quarter-circular.

4. The semiconductor device of claim 1, further comprising: A dual-diffusion region is disposed below the second source / drain region, and in cross-section, the dual-diffusion region extends from a bottom surface of the second source / drain region along a first sidewall of the gate structure to a bottom surface of the gate structure. The channel region connects the first source / drain region and the double diffusion region.

5. The semiconductor device of claim 4, wherein the channel region extends from a bottom surface of the first source / drain region along a second sidewall of the gate structure to the bottom surface of the gate structure.

6. The semiconductor device of claim 4, further comprising: A body region is disposed below the first source / drain region, the gate structure, and the double diffusion region.

7. The semiconductor device of claim 1, wherein the gate structure comprises; An insulator; and A gate conductor is surrounded by the insulator.

8. The semiconductor device of claim 7, wherein, Viewed in cross-section, the gate conductor includes: One top surface; One bottom surface, opposite to the top surface; An outer wall connects to the top surface; An inner wall, opposite to the outer wall, connects the top surface and the bottom surface; and A curved sidewall connects the outer sidewall and the bottom surface.

9. The semiconductor element of claim 8, wherein the curved sidewall is curved outward.

10. The semiconductor device of claim 8, wherein, viewed from top view, the gate conductor is ring-shaped.

11. The semiconductor device of claim 7, wherein the central portion of the gate structure is elliptical, and the gate conductor is elliptical.

12. The semiconductor device of claim 7, wherein the central portion of the gate structure is hexagonal, and the gate conductor is hexagonal.

13. The semiconductor device of claim 1, wherein the central portion of the gate structure is circular.

14. The semiconductor device of claim 1, wherein the second source / drain region is elliptical.

15. The semiconductor device of claim 1, wherein the second source / drain region is hexagonal.

16. The semiconductor device of claim 1, wherein the first source / drain region and the second source / drain region are n-type doped regions.

17. A semiconductor element, comprising: A first transistor and a second transistor, wherein the first transistor and the second transistor each include: A gate structure having a central portion and a plurality of connection portions, wherein, viewed from top view, the plurality of connection portions protrude from the central portion; A first source / drain region, viewed from above, surrounds the gate structure; A second source / drain region is surrounded by the gate structure; and A channel region, viewed in cross-section, is located below the first source / drain region; viewed from top view, this channel region surrounds the gate structure. The first transistor and the second transistor are connected in parallel.

18. The semiconductor device of claim 17, wherein one of the plurality of connection portions of the first transistor is connected to one of the plurality of connection portions of the second transistor. Each gate structure includes an insulator and a gate conductor, wherein the insulator of the first transistor and the insulator of the second transistor are monolithic structures.

19. The semiconductor device of claim 17, wherein the first source / drain region of the first transistor is connected to the second transistor.

20. The semiconductor device of claim 17, wherein each of the first transistor and the second transistor further comprises: A first contact region is located above the first source / drain region; as well as A second contact region is surrounded by the second source / drain region; The first contact area of ​​the first transistor is connected to the second transistor and is a single-unit structure.

Images