Semiconductor device structure and method of forming the same

Abstract

Semiconductor device structures and methods of forming the same are provided. The method includes forming a semiconductor nanostructure over a substrate and forming an epitaxial structure adjacent to sidewalls of the semiconductor nanostructure. The method also includes forming a gate stack over the semiconductor nanostructure. The gate stack has a gate dielectric layer and a titanium-containing gate electrode. The method further includes forming an opening extending toward a bottom of the epitaxial structure. The opening is spaced apart from the epitaxial structure. In addition, the method includes performing an implantation process to form a doped region near a bottom of the opening, and the doped region and the epitaxial structure are oppositely doped. The method includes forming a conductive structure that partially or completely fills the opening.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs. Each generation features smaller and more complex circuits than the previous one.

[0003] In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, these advancements have also increased the complexity of handling and manufacturing ICs. As component sizes continue to shrink, manufacturing processes become increasingly difficult to execute. Therefore, forming reliable semiconductor devices at ever-smaller dimensions remains a challenge. Summary of the Invention

[0005] One embodiment of this application provides a semiconductor device structure, including: a semiconductor nanostructure; an epitaxial structure located next to the semiconductor nanostructure, wherein the epitaxial structure has a first portion and a second portion, the second portion being spaced apart from the semiconductor nanostructure through the first portion, and the first portion and the second portion having different dopant concentrations; a conductive structure located below the epitaxial structure; and a doped region located between the epitaxial structure and the conductive structure, wherein the doped region is spaced apart from the epitaxial structure, the doped region is electrically connected to the conductive structure, and the doped region and the epitaxial structure are doped in opposite directions.

[0006] Another embodiment of this application provides a method for forming a semiconductor device structure, comprising: forming a semiconductor nanostructure over a substrate; forming an epitaxial structure adjacent to the sidewalls of the semiconductor nanostructure; forming a gate stack over the semiconductor nanostructure, wherein the gate stack has a gate dielectric layer and a titanium-containing gate electrode; forming an opening extending toward the bottom of the epitaxial structure, wherein the opening is spaced apart from the epitaxial structure; performing an implantation process to form a doped region near the bottom of the opening, wherein the doped region and the epitaxial structure are oppositely doped; and forming a conductive structure that at least partially fills the opening.

[0007] An embodiment of this application further provides a method for forming a semiconductor device structure, comprising: forming a plurality of sacrificial nanostructures and a plurality of semiconductor nanostructures above a substrate, wherein the sacrificial nanostructures and the semiconductor nanostructures are arranged alternately; forming an epitaxial structure next to the semiconductor nanostructures; removing the sacrificial nanostructures; forming a gate stack enclosing the semiconductor nanostructures, wherein the gate stack has a gate dielectric layer and the dielectric constant of the gate dielectric layer is greater than the dielectric constant of a gate spacer formed next to the gate stack; forming a doped region extending upward toward the bottom of the epitaxial structure, wherein the doped region and the epitaxial structure have different dopants and the doped region is spaced apart from the epitaxial structure; and forming a conductive structure electrically connected to the doped region, wherein the conductivity of the conductive structure is greater than the conductivity of the epitaxial structure. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0009] Figures 1A to 1D This is a top view of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0010] Figures 2A to 2D These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0011] Figures 3A to 3T These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0012] Figure 4A This is a top view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0013] Figure 4B This is a top view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0014] Figure 5 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0015] Figure 6 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0016] Figure 7This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0017] Figure 8 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Embodiments of this disclosure may relate to FinFET structures with fins. Fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fins. However, fins can be formed using one or more other suitable processes.

[0021] Embodiments of this disclosure may relate to gate-all-around (GAA) transistor structures. GAA structures can be patterned using any suitable method. For example, structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. In some embodiments, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0022] Some embodiments of this disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Additional components may be added to the semiconductor device structure. For different embodiments, some of the components described below may be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific order, these operations may also be performed in another logical order.

[0023] Figures 2A to 2D These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. For example... Figure 2A As shown, a semiconductor substrate 100 is received or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 may include silicon or other elemental semiconductor materials such as germanium. The semiconductor substrate 100 may be undoped or doped (e.g., p-type, n-type, or combinations thereof). In some embodiments, the semiconductor substrate 100 includes an epitaxially grown semiconductor layer located on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon-germanium, silicon, germanium, one or more other suitable materials, or combinations thereof.

[0024] In some other embodiments, the semiconductor substrate 100 comprises a compound semiconductor. For example, the compound semiconductor includes one or more group III-V compound semiconductors having the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4The defined components, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and together they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable compound semiconductors, including group II-VI compound semiconductors, may also be used.

[0025] In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be fabricated using a SIMOX process, a wafer bonding process, another suitable method, or a combination thereof. In some other embodiments, the semiconductor substrate 100 comprises a multilayer structure. For example, the semiconductor substrate 100 includes a silicon-germanium layer formed on a bulk silicon layer.

[0026] like Figure 2A As shown, according to some embodiments, a semiconductor stack having multiple semiconductor layers is formed over a semiconductor substrate 100. In some embodiments, the semiconductor stack includes multiple semiconductor layers 102a, 102b, and 102c. The semiconductor stack also includes multiple semiconductor layers 104a, 104b, and 104c. In some embodiments, as... Figure 2A As shown, semiconductor layers 102a-102c and semiconductor layers 104a-104c are arranged and laid out in an alternating manner.

[0027] In some embodiments, semiconductor layers 102a-102c serve as sacrificial layers (or sacrificial nanostructures), which are removed in subsequent processes to release semiconductor layers 104a-104c. The released semiconductor layers 104a-104c can form multiple semiconductor nanostructures and serve as the channel structure for one or more transistors.

[0028] In some embodiments, the semiconductor layers 104a-104c used to form the channel structure are made of a different material than semiconductor layers 102a-102c. In some embodiments, semiconductor layers 104a-104c are made of or comprise silicon. In some other embodiments, semiconductor layers 104a-104c are made of or comprise silicon, germanium, another suitable material, or a combination thereof. In some embodiments, semiconductor layers 102a-102c are made of or comprise silicon-germanium.

[0029] In some other embodiments, semiconductor layers 104a-104c are made of silicon-germanium, and semiconductor layers 102a-102c are made of silicon-germanium with a different concentration of germanium atoms than semiconductor layers 104a-104c. Due to the different compositions, different etch selectivity and / or different oxidation rates can be achieved between semiconductor layers 102a-102c and semiconductor layers 104a-104c during subsequent processing.

[0030] This disclosure contemplates that semiconductor layers 102a-102c and semiconductor layers 104a-104c include any combination of semiconductor materials that can provide desired etch selectivity, desired oxidation rate differences and / or desired performance characteristics (e.g., materials that maximize current).

[0031] In some embodiments, semiconductor layers 102a-102c and 104a-104c are formed using multiple epitaxial growth operations. In some embodiments, semiconductor layers 102a-102c and 104a-104c can be configured as a superlattice structure with alternating layers of different semiconductor materials. Each of semiconductor layers 102a-102c and 104a-104c can be formed using selective epitaxial growth (SEG), CVD processes (e.g., vapor phase epitaxy (VPE), low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, another suitable process, or combinations thereof.

[0032] In some embodiments, semiconductor layers 102a-102c and 104a-104c are grown in situ within the same process chamber. In some embodiments, the growth of semiconductor layers 102a-102c and 104a-104c is performed alternately and sequentially within the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum in the process chamber is not broken until the epitaxial growth of the semiconductor stack is completed.

[0033] Next, a hard mask element is formed on top of the semiconductor stack to assist in the subsequent patterning of the semiconductor stack. For example... Figure 2B As shown, each hard mask element may include a first mask layer 108 and a second mask layer 110. The first mask layer 108 and the second mask layer 110 may be made of different materials. One or more photolithography processes and one or more etching processes are used to pattern the semiconductor stack into multiple fin structures.

[0034] Fin structures can be patterned using any suitable method. For example, fin structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process.

[0035] According to some embodiments, such as Figure 2B As shown, a portion of the semiconductor stack is removed to form multiple fin structures and multiple trenches 112. The fin structures include fin structures 106A and 106B in a first region and fin structures 106A' and 106B' in a second region. Figure 2B As shown, the dashed line separates the first region from the second region. Figure 2B As shown, each fin structure 106A-106B and 106A'-106B' may include portions of semiconductor layers 102a-102c and 104a-104c and multiple semiconductor fins (including semiconductor fins 101A, 101B, 101A', and 101B'). During the etching process that forms the fin structures, the semiconductor substrate 100 may also be partially removed. The remaining protruding portions of the semiconductor substrate 100 form the semiconductor fins 101A-101B and 101A'-101B'.

[0036] Figures 1A to 1D This is a top view of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. (e.g.) Figure 1A As shown, according to some embodiments, a plurality of fin structures 106A, 106B, 106A', and 106B' are formed. In some embodiments, the fin structures 106A-106B and 106A'-106B' are longitudinally oriented. In some embodiments, as... Figure 1A As shown, the longitudinal directions of fin structures 106A-106B and 106A'-106B' are substantially parallel to each other. In some embodiments, Figure 2B It is along Figure 1A The cross-sectional view of the structure intercepted by lines 2B-2B and 2B'-2B' in the diagram.

[0037] Subsequently, according to some embodiments, such as Figure 1B and Figure 2C As shown, an isolation structure 115 is formed. In some embodiments, Figure 2C It is along Figure 1B The cross-sectional view of the structure intercepted by lines 2C-2C and 2C'-2C' in the diagram. (See diagram below.) Figure 1B As shown, a first portion of the isolation structure 115 extends between fin structures 106A and 106B, and a second portion of the isolation structure 115 extends between fin structures 106A' and 106B'. Figure 2C As shown, according to some embodiments, the isolation structure 115 is formed laterally around the lower portions of the fin structures 106A-106B and 106A'-106B'. In some embodiments, the isolation structure 115 includes a dielectric filler 114 and a liner layer 113 adjacent to the semiconductor fins 101A-101B and 101A'-101B'.

[0038] In some embodiments, the isolation structure 115 comprises one or more oxide-based materials. In some embodiments, one or more dielectric layers for forming the dielectric filler 114 are deposited over the fin structures 106A-106B and 106A'-106B' and the semiconductor substrate 100. The dielectric layers may be made of or comprise silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphate silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k materials, porous dielectric materials, one or more other suitable materials, or combinations thereof. The liner layer 113 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, one or more other suitable materials or combinations thereof. The dielectric layer and the liner layer 113 may be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, one or more other suitable processes or combinations thereof.

[0039] Subsequently, a planarization process is used to partially remove the dielectric layer and liner layer 113. Hard mask elements (including the first mask layer 108 and the second mask layer 110) can also be used as stop layers for the planarization process. The planarization process may include chemical mechanical polishing (CMP), grinding, dry polishing, etching, one or more other suitable processes, or combinations thereof.

[0040] Subsequently, one or more etch-back processes are used to partially remove the dielectric layer and liner layer 113. As a result, the remaining portion of the dielectric layer forms the dielectric filler 114 of the isolation structure 115. (As...) Figure 2C As shown, the upper portions of fin structures 106A-106B and 106A'-106B' protrude from the top surface of the isolation structure 115.

[0041] In some embodiments, such as Figure 2C As shown, the etch-back process used to form the isolation structure 115 is carefully controlled to ensure that the top surface of the isolation structure 115 is located at an appropriate height level. In some embodiments, the top surface of the isolation structure 115 is lower than the bottom surface of the semiconductor layer 102a, which serves as a sacrificial layer. Therefore, the side surfaces of the bottommost sacrificial layer (i.e., semiconductor layer 102a) are exposed and not covered by the isolation structure 115, thereby facilitating subsequent removal processes of the semiconductor layers 102a-102c.

[0042] In some embodiments, such as Figure 2C As shown, the top surface of the isolation structure 115 is not flat. In some embodiments, the isolation structure 115 has a first portion PA and a second portion PB. The first portion PA is located next to the semiconductor fin 101A. The first portion PA is located between the second portion PB and the semiconductor fin 101A, and the first portion PA is thicker than the second portion PB. In some embodiments, as Figure 2C As shown, the isolation structure 115 gradually thins along the direction away from the semiconductor fin 101A. In some embodiments, the first portion PA has a curved upper surface.

[0043] Subsequently, the hard mask elements (including the first mask layer 108 and the second mask layer 110) are removed. Optionally, in some other embodiments, the hard mask elements are removed or consumed during the planarization process and / or etch-back process that forms the isolation structure 115.

[0044] Subsequently, according to some embodiments, such as Figure 1C As shown, dummy gate stacks 120A, 120B, 120A', and 120B' are formed to extend across fin structures 106A-106B and 106A'-106B'. In some embodiments, Figure 2D It is along Figure 1C The cross-sectional view of the structure intercepted by lines 2D-2D and 2D'-2D'. Figures 3A to 3T These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. In some embodiments, Figure 3A It shows the respective along Figure 1C The cross-sectional views of the two parts R1 and R2 of the structure intercepted by lines 3A-3A and 3A'-3A' are shown.

[0045] like Figure 1C , Figure 2D and Figure 3A As shown, according to some embodiments, dummy gate stacks 120A-120B and 120A'-120B' partially cover fin structures 106A-106B and 106A'-106B' and extend across fin structures 106A-106B and 106A'-106B'. In some embodiments, dummy gate stacks 120A and 120B enclose fin structures 106A and 106B, and dummy gate stacks 120A' and 120B' enclose fin structures 106A' and 106B'. Figure 2D As shown, the dummy gate stack 120B extends across and wraps around the fin structures 106A and 106B, and the dummy gate stacks 120A' and 120B' wrap around the fin structures 106A' and 106B'. Figure 1CAs shown, the remaining portions of fin structures 106A-106B and 106A'-106B' are exposed and not covered by the dummy gate stacks 120A-120B and 120A'-120B'.

[0046] In some embodiments, the dummy gate stacks 120A-120B and 120A'-120B' are longitudinally oriented along a first direction, while the fin structures 106A-106B and 106A'-106B' are longitudinally oriented along a second direction other than the first direction. In some embodiments, such as Figure 1C As shown, the first direction is substantially perpendicular to the second direction. In some embodiments, a first portion of the isolation structure 115 is disposed between fin structures 106A and 106B, and a second portion of the isolation structure 115 is disposed between fin structures 106A' and 106B'.

[0047] like Figure 2D and Figure 3A As shown, each of the dummy gate stacks 120A-120B and 120A'-120B' includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 may be made of or comprise silicon oxide or another suitable material. The dummy gate electrode 118 may be made of or comprise polysilicon or another suitable material.

[0048] In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 115 and the fin structures 106A-106B and 106A'-106B'. The dummy gate dielectric material layer can be deposited using an ALD process, a CVD process, one or more other suitable processes, or a combination thereof. The dummy gate electrode layer can be deposited using a CVD process. Subsequently, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form dummy gate stacks 120A-120B and 120A'-120B'.

[0049] In some embodiments, hard mask elements 122 and 124 are used to assist in the patterning process for forming dummy gate stacks 120A and 120B. Using hard mask elements 122 and 124 as etch masks, one or more etch processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. As a result, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate stacks 120A-120B and 120A'-120B'.

[0050] Subsequently, according to some embodiments, one or more spacer layers are deposited over the dummy gate stacks 120A-120B and 120A'-120B', the fin structures 106A-106B and 106A'-106B', and the exposed portions of the isolation structure 115. The spacer layers extend along the top and sidewalls of the dummy gate stacks 120A-120B and 120A'-120B'. The spacer layers also extend along the top of the fin structures 106A-106B and 106A'-106B'.

[0051] In some embodiments, the spacer layers are made of different materials. In some other embodiments, the spacer layers are made of the same material. The spacer layers may be made of or include silicon nitride, silicon carbide, silicon carbide, silicon oxynitride-containing silicon carbide, silicon oxide, another suitable material, or a combination thereof. The spacer layers may be deposited sequentially using CVD, ALD, physical vapor deposition (PVD), another suitable process, or a combination thereof.

[0052] Subsequently, according to some embodiments, the spacer layer is partially removed. One or more anisotropic etching processes can be used to partially remove the spacer layer. Therefore, as... Figure 1D and Figure 3B As shown, the remaining portion of the spacer layer forms the gate spacer layer 128'. In some embodiments, Figure 3B It shows the respective along Figure 1D The cross-sectional views of the structures R1 and R2 cut by lines 3B-3B and 3B'-3B' are shown.

[0053] According to some embodiments, such as Figure 3B As shown, gate spacer 128' extends along the sidewalls of dummy gate stacks 120A-120B and 120A'-120B'. In some embodiments, similar to dummy gate stacks 120A-120B and 120A'-120B', gate spacer 128' extends longitudinally along a first direction, while fin structures 106A and 106B extend longitudinally along a second direction other than the first direction. In some embodiments, the first direction is substantially perpendicular to the second direction.

[0054] Subsequently, fin structures 106A-106B and 106A'-106B' are partially removed to form multiple grooves 130. These grooves 130 accommodate subsequently formed epitaxial structures that can be used as source / drain structures. Figure 3BAs shown, each groove 130 in portions R1 and R2 exposes a side surface of semiconductor layers 104a-104c, on which an epitaxial structure, such as a source / drain structure, will subsequently be formed. Depending on the context, a source / drain structure may refer individually or collectively to a source structure or a drain structure.

[0055] One or more etching processes can be used to form the groove 130. In some embodiments, a dry etching process is used to form the groove 130. Alternatively, a wet etching process can be used to form the groove 130. In some embodiments, the groove 130 extends into the fin structures 106A and 106A'. In some embodiments, such as Figure 3B As shown, the recess 130 further extends into the semiconductor fins 101A and 101A'. In some embodiments, the gate spacer 128' and the recess 130 are formed simultaneously using the same etching process performed in the same process chamber.

[0056] In some embodiments, the recess 130 has substantially vertical sidewalls. The profile of the recess 130 can be fine-tuned by adjusting the etching process parameters. In these cases, due to the profile of the recess 130, the upper semiconductor layer (such as semiconductor layer 104c) is substantially the same width as the lower semiconductor layer (such as semiconductor layer 104b).

[0057] However, the embodiments of this disclosure have many variations. In some other embodiments, each recess 130 has sloping sidewalls. The upper portion of the recess 130 is larger (or wider) than the lower portion of the recess 130. In these cases, due to the contour of the recess 130, the upper semiconductor layer (such as semiconductor layer 104c) is narrower than the lower semiconductor layer (such as semiconductor layer 104b).

[0058] like Figure 3C As shown, according to some embodiments, a patterned mask layer 301 is formed to cover the recess 130 in portion R2. The recess 130 in portion R1 is exposed. The patterned mask layer 301 may include a patterned photoresist layer. Then, according to some embodiments, such as Figure 3C As shown, the groove 130 in portion R1 is deepened. One or more etching processes may be used to partially remove the semiconductor fin 101A in portion R1. As a result, the groove 130 is deepened. In some embodiments, the groove 130 in portion R1 further extends toward the interface between the semiconductor fin 101A and the semiconductor substrate 100. In some embodiments, the groove 130 in portion R1 passes through the semiconductor fin 101A.

[0059] like Figure 3CAs shown, the groove 130 in portion R1 is deeper than the groove 130 in portion R2 by a depth difference D. The depth difference D can range from about 20 nm to about 40 nm. In some cases, if the depth difference D is less than about 20 nm, the groove 130 in portion R2 may become too deep for the subsequent formation of the doped region 328 in portion R2 (see...). Figure 3R The space left is insufficient. Alternatively, the groove 130 in part R1 may be too shallow, which may affect the subsequent formation of the through-hole opening 322A in part R1 (see Figure 3P This can have adverse effects. In some other cases, if the depth difference D exceeds about 40 nm, the semiconductor layers 104a-104c in portion R1 may be damaged during the deepening of the recess 130 in portion R1.

[0060] Next, the patterned mask layer 301 is removed. Then, the semiconductor layers 102a-102c, which serve as sacrificial layers, are removed. As a result, according to some embodiments, a... Figure 3D The structure is shown. One or more etching processes can be used to remove semiconductor layers 102a-102c. (As shown...) Figure 3D As shown, after removing the semiconductor layers 102a-102c, multiple grooves 302 are formed.

[0061] like Figure 3D As shown, the remaining portions of semiconductor layers 104a-104c, released from semiconductor layers 102a-102c, form multiple semiconductor nanostructures 104a', 104b', and 104c'. These are supported by dummy gate stacks 120A-120B and 120A'-120B' (see also...) Figure 2D After removing the semiconductor layers 102a-102c, the semiconductor nanostructures 104a'-104c' remain firmly in place.

[0062] Subsequently, according to some embodiments, a dielectric layer is deposited to overfill the groove 302 and surround the semiconductor nanostructures 104a'-104c'. The dielectric layer may also extend over the top and sidewalls of the dummy gate stacks 120A-120B and 120A'-120B'.

[0063] The dielectric layer may be made of oxide materials, nitride materials, another suitable material, or combinations thereof. The dielectric layer may be made of silicon oxide, silicon oxynitride, aluminum oxide, silicon nitride, another suitable material, or combinations thereof, or may include silicon oxide, silicon oxynitride, aluminum oxide, silicon nitride, another suitable material, or combinations thereof.

[0064] In some embodiments, the dielectric layer is a single layer. In some other embodiments, the dielectric layer comprises multiple sublayers. In some embodiments, the sublayers of the dielectric layer are made of the same material. In some other embodiments, some sublayers of the dielectric layer are made of different materials.

[0065] The dielectric layer can be deposited using CVD, ALD, flowable chemical vapor deposition (FCVD), another suitable process, or a combination thereof. In some embodiments, the formation of the dielectric layer also involves one or more etching processes used to refine the profile of the deposited sublayers of the dielectric layer.

[0066] like Figure 3E As shown, according to some embodiments, a plurality of dielectric nanostructures 306a, 306b, and 306c are formed in the groove 302. In some embodiments, one or more etching processes are used to partially remove the previously deposited dielectric layer. A portion of the dielectric layer outside the groove 302 is removed. As a result, as... Figure 3E As shown, the remaining portion of the dielectric layer forms dielectric nanostructures 306a, 306b, and 306c. Dielectric nanostructures 306a-306c can be used as sacrificial nanostructures. Figure 3E As shown, dielectric nanostructures 306a-306c and semiconductor nanostructures 104a'-104c' are arranged alternately.

[0067] like Figure 3F As shown, according to some embodiments, dielectric nanostructures 306a-306c are partially removed to pull back the side surfaces of the dielectric nanostructures 306a-306c. One or more etching processes can be used to partially remove the dielectric nanostructures 306a-306c. As a result, the side surfaces of the dielectric nanostructures 306a-306c recede from the side surfaces of the semiconductor nanostructures 104a'-104c'. Figure 3F As shown, grooves 132A, 132B, and 132C are formed by the lateral etching of dielectric nanostructures 306a-306c. Grooves 132A-132C can be used to accommodate internal spacers that will be formed later.

[0068] In some embodiments, the lower recess (such as recess 132A) is wider or deeper than the upper recess (such as recess 132B). Figure 3F As shown, groove 132A has a depth DA, groove 132B has a depth DB, and groove 132C has a depth DC. In some embodiments, depth DA is greater than depth DB, and depth DB is greater than depth DC.

[0069] However, the embodiments disclosed herein are not limited thereto. In some other embodiments, depths DA, DB, and DC are equal. In some other embodiments, depth DC is greater than depth DB, and depth DB is greater than depth DA.

[0070] like Figure 3G As shown, according to some embodiments, a plurality of internal spacers 136A, 136B, and 136C are formed. In some embodiments, an insulating layer is deposited to overfill the grooves 132A-132C. The insulating layer may be made of or include silicon carbide (SiCN), silicon carbide oxynitride (SiOCN), silicon carbide oxynitride (SiOC), silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

[0071] In some embodiments, the dielectric nanostructures 306a-306c are made of silicon oxide, and the insulating layer is made of silicon oxynitride, silicon nitride, another suitable material, or a combination thereof. In some embodiments, the dielectric nanostructures 306a-306c are made of silicon nitride, and the insulating layer is made of silicon oxynitride, silicon oxide, another suitable material, or a combination thereof. In some embodiments, the dielectric nanostructures 306a-306c are made of silicon oxynitride, and the insulating layer is made of silicon oxynitride, another suitable material, or a combination thereof. In some embodiments, the dielectric nanostructures 306a-306c are made of aluminum oxide, and the insulating layer is made of silicon oxynitride, another suitable material, or a combination thereof.

[0072] In some embodiments, the insulating layer used to form the internal spacers 136A-136C is a single layer. In some other embodiments, the insulating layer comprises multiple sublayers. Some sublayers may be made of different materials and / or contain different compositions. The insulating layer may be deposited using CVD processes, ALD processes, another suitable process, or combinations thereof.

[0073] Subsequently, one or more etching processes are used to partially remove the insulating layer. The portion of the insulating layer outside the grooves 132A-132C is removed. As a result, according to some embodiments, such as Figure 3G As shown, the remaining portion of the insulating layer forms the internal spacers 136A-136C. One or more etching processes may include dry etching, wet etching, or a combination thereof.

[0074] like Figure 3G As shown, internal spacers 136A-136C cover the side surfaces of dielectric nanostructures 306a-306c. Internal spacers 136A-136C can be used to prevent subsequently formed epitaxial structures (e.g., used as source / drain structures) from being damaged during subsequent processes for removing dielectric nanostructures 306a-306c.

[0075] In some embodiments, the internal spacers 136A-136C are made of a low-k material with a dielectric constant lower than that of silicon oxide. In these cases, the internal spacers 136A-136C can also be used to reduce the parasitic capacitance between the subsequently formed source / drain structure and the gate stack. As a result, the operating speed of the semiconductor device structure can be improved.

[0076] like Figure 3G As shown, internal spacer 136A has a width WA, internal spacer 136B has a width WB, and internal spacer 136C has a width WC. In some embodiments, width WA is greater than width WB, and width WB is greater than width WC.

[0077] However, the embodiments disclosed herein are not limited thereto. In some other embodiments, widths WA, WB, and WC are equal. In some other embodiments, width WC is greater than width WB, and width WB is greater than width WA.

[0078] like Figure 3H As shown, according to some embodiments, a semiconductor isolation structure 137 and an isolation element 308 are sequentially formed above the bottom of the recess 130 in portions R1 and R2. In some embodiments, the semiconductor isolation structure 137 is an undoped epitaxial structure. In some embodiments, the semiconductor isolation structure 137 is substantially free of n-type or p-type dopant. The semiconductor isolation structure 137 can serve as an isolation structure. The semiconductor isolation structure 137 can help reduce or prevent current leakage from the epitaxial structure that will be formed later. The semiconductor isolation structure 137 can provide a relatively flat surface to facilitate the subsequent formation of the epitaxial structure.

[0079] In some embodiments, such as Figure 3H As shown, due to the deepening of the groove 130 in portion R1, the semiconductor discrete structure 137 in portion R1 is longer than the semiconductor discrete structure 137 in portion R2. In some embodiments, the bottom of the semiconductor discrete structure 137 in portion R1 is closer to the semiconductor substrate 100 than the bottom of the semiconductor discrete structure 137 in portion R2.

[0080] The semiconductor discrete structure 137 may be made of or include silicon germanium, silicon, another suitable material, or a combination thereof. The semiconductor discrete structure 137 may be formed using selective epitaxial growth (SEG), CVD processes (e.g., vapor phase epitaxy (VPE), low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, another suitable process, or a combination thereof.

[0081] In some embodiments, the formation of the semiconductor discrete structure 137 involves one or more etching processes used to fine-tune the contour of the semiconductor discrete structure 137. The etching process may also remove epitaxial material grown on the side surfaces of the semiconductor nanostructures 104a'-104c' during the formation of the semiconductor discrete structure 137.

[0082] The isolation element 308 may be made of or comprise a dielectric material. The isolation element 308 may be made of or comprise silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, another suitable material, or a combination thereof. In some other embodiments, the isolation element 308 is made of or comprises a semiconductor material.

[0083] In some embodiments, a dielectric layer (such as a silicon nitride layer) is deposited over the dummy gate stacks 120A-120B and 120A'-120B' and the sidewalls of the recess 130. A barrier layer is formed over the dielectric layer, and then the barrier layer is etched back. After the barrier layer is etched back, the upper portion of the dielectric layer is exposed. The exposed portion of the dielectric layer is then removed. The barrier layer is then removed. The remaining portion of the dielectric layer has a thinner portion extending along the sidewalls of the recess 130 and a thicker portion directly above the semiconductor isolation structure 137. The dielectric layer is then thinned using an etching process. As a result, the thinner portion extending along the sidewalls of the recess 130 is removed. The thicker portion directly above the semiconductor isolation structure 137 is thinned and forms the isolation element 308.

[0084] like Figure 3I As shown, according to some embodiments, an epitaxial structure 138 is formed above the isolation element 308 in portions R1 and R2 and the side surfaces of the semiconductor nanostructures 104a'-104c'. Multiple epitaxial structures 138 are formed next to or adjacent to the semiconductor nanostructures 104a'-104c'. In some embodiments, the epitaxial structures 138 are connected to the semiconductor nanostructures 104a'-104c'. In some embodiments, the epitaxial structures 138 overfill the recess 130 to ensure complete contact with the side surfaces of the adjacent semiconductor nanostructures 104a'-104c'.

[0085] In some embodiments, each epitaxial structure 138 has a lightly doped first portion 138a adjacent to the semiconductor nanostructures 104a'-104c'. In some embodiments, each epitaxial structure 138 further has a second portion 138b, which is spaced apart from the side surfaces of the semiconductor nanostructures 104a'-104c' by the first portion 138a. In some embodiments, each epitaxial structure 138 further has a third portion 138c surrounded by the second portion 138b. In some embodiments, the first portion 138a, the second portion 138b, and the third portion 138c of the epitaxial structure 138 are doped with the same dopant but with different dopant concentrations. In some embodiments, the third portion 138c has a higher dopant concentration than the second portion 138b, which in turn has a higher dopant concentration than the first portion 138a.

[0086] In some embodiments, the epitaxial structure 138 is an n-type doped epitaxial structure. The epitaxial structure 138 may include epitaxially grown silicon, epitaxially grown silicon germanium (SiGe), or another suitable epitaxially grown semiconductor material. The n-type dopant may include phosphorus (P), antimony (Sb), arsenic (As), another suitable element, or a combination thereof.

[0087] In some embodiments, the epitaxial structure 138 is a p-type doped epitaxial structure. The epitaxial structure 138 may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or another suitable epitaxially grown semiconductor material. In some embodiments, the epitaxial structure 138 is doped with one or more suitable p-type dopants. For example, the epitaxial structure 138 is a SiGe source / drain component doped with boron (B), gallium (Ga), indium (In), or another suitable dopant.

[0088] In some embodiments, the epitaxial structure 138 is doped in situ during epitaxial growth. The initial reactive gas mixture used to form the epitaxial structure 138 contains a dopant. In some other embodiments, the epitaxial structure 138 is not doped during its growth. Instead, the epitaxial structure 138 is doped in a subsequent process after its formation.

[0089] In some embodiments, doping is achieved using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, another suitable process, or a combination thereof. In some embodiments, the epitaxial structure 138 is further exposed to one or more annealing processes to activate the dopant. For example, a rapid thermal annealing process is used.

[0090] In some embodiments, the formation of the epitaxial structure 138 involving thermal processes is performed after the semiconductor layers 102a-102c are replaced with dielectric nanostructures 306a-306c. Since the semiconductor layers 102a-102c have been previously removed, germanium diffusion from these layers into the nearby semiconductor nanostructures 104a'-104c' can be prevented during the formation of the epitaxial structure 138. Therefore, the semiconductor nanostructures 104a'-104c' can have a low atomic concentration of germanium impurities, improving the quality and reliability of the semiconductor nanostructures 104a'-104c'.

[0091] like Figure 3J As shown, according to some embodiments, a contact etch stop layer 139 and a dielectric layer 140 are sequentially formed over the epitaxial structure 138 to laterally surround the dummy gate stacks 120A-120B and 120A'-120B'. The contact etch stop layer 139 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, another suitable material, or a combination thereof. The dielectric layer 140 may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k material, a porous dielectric material, another suitable material, or a combination thereof.

[0092] In some embodiments, an etch stop material layer and a dielectric material layer are deposited sequentially. The etch stop material layer can be deposited using CVD, ALD, PVD, one or more other suitable processes, or combinations thereof. The dielectric material layer can be deposited using FCVD, CVD, ALD, another suitable process, or combinations thereof.

[0093] Subsequently, a planarization process was used to partially remove the etch stop material layer and the dielectric material layer. The result is as follows: Figure 3J As shown, the remaining portions of the etch stop material layer and the dielectric material layer form the contact etch stop layer 139 and the dielectric layer 140, respectively. The planarization process may include CMP, grinding, etching, dry polishing, one or more other suitable processes, or combinations thereof.

[0094] In some embodiments, hard mask elements 122 and 124 that define the dummy gate stacks 120A-120B and 120A'-120B' are removed during the planarization process. In some embodiments, as Figure 3J As shown, after the planarization process, the top surfaces of the contact etch stop layer 139, dielectric layer 140, gate spacer 128' and dummy gate electrode 118 are substantially flush.

[0095] After that, as Figure 3K As shown, according to some embodiments, dummy gate stacks 120A-120B and 120A'-120B' and dielectric nanostructures 306a-306c (used as sacrificial nanostructures) are removed. In some embodiments, one or more etching processes are used to remove the dummy gate stacks 120A-120B and 120A'-120B' and dielectric nanostructures 306a-306c. The result is as follows: Figure 3K As shown, multiple grooves 142 and recesses 144 are formed.

[0096] Due to high etch selectivity, the semiconductor nanostructures 104a'-104c' are lightly (or essentially not) etched. The semiconductor nanostructures 104a'-104c', suspended above semiconductor fins 101A and 101B, can be used as the channel structure for transistors. In some other embodiments, the etchant used to remove the dielectric nanostructures 306a-306c also slightly removes the semiconductor nanostructures 104a'-104c'. As a result, after removing the dielectric nanostructures 306a-306c, the obtained semiconductor nanostructures 104a'-104c' become thinner.

[0097] In some embodiments, the internal portions of the semiconductor nanostructures 104a'-104c' are substantially the same thickness as the edge portions of the semiconductor nanostructures 104a'-104c'. In some other embodiments, the internal portions of the semiconductor nanostructures 104a'-104c' are thicker than the edge portions of the semiconductor nanostructures 104a'-104c'. In some other embodiments, the internal portions of the semiconductor nanostructures 104a'-104c' are thinner than the edge portions of the semiconductor nanostructures 104a'-104c'.

[0098] After removing the dielectric nanostructures 306a-306c (used as sacrificial nanostructures), grooves 144 are formed. Grooves 144 surround each semiconductor nanostructure 104a'-104c'. Figure 3K As shown, even with the formation of grooves 144 between semiconductor nanostructures 104a'-104c', the semiconductor nanostructures 104a'-104c' are still supported by adjacent elements (such as epitaxial structure 138). Therefore, after removing the dummy gate stacks 120A-120B and 120A'-120B' and the dielectric nanostructures 306a-306c, the released semiconductor nanostructures 104a'-104c' remain in situ.

[0099] like Figure 3L As shown, according to some embodiments, metal gate stacks 156A, 156B, 156A', and 156B' are formed to fill trench 142. The metal gate stacks 156A-156B and 156A'-156B' further extend into recess 144 to enclose each semiconductor nanostructure 104a'-104c'.

[0100] Each of the metal gate stacks 156A-156B and 156A'-156B' includes a plurality of metal gate stack layers. The metal gate stack layers of the metal gate stacks 156A-156B and 156A'-156B' may include a gate dielectric layer 150, a power function adjustment layer 152, and a conductive filler 154. The power function adjustment layer 152 and the conductive filler 154 may together serve as the gate electrode of the metal gate stacks 156A-156B and 156A'-156B'. In some embodiments, the formation of the metal gate stacks 156A-156B and 156A'-156B' involves depositing a plurality of metal gate stack layers that fill trenches 142 and recesses 144. The metal gate stack layers extend into the recesses 144 to enclose each semiconductor nanostructure 104a'-104c'.

[0101] In some embodiments, the gate dielectric layer 150 is made of or includes a dielectric material having a high dielectric constant (high K). In some embodiments, the gate dielectric layer 150 has a higher dielectric constant than the gate spacer 128'. In some embodiments, the gate dielectric layer 150 has a higher dielectric constant than the inner spacers 136A-136C. In some embodiments, the gate dielectric layer 150 is thinner than each of the gate spacer 128' and the inner spacers 136A-136C. In some embodiments, as Figure 3L As shown, the contact etch stop layer 139 is located between the gate dielectric layer 150 and the dielectric layer 140.

[0102] The gate dielectric layer 150 may be made of or comprise a metal-containing dielectric material. The gate dielectric layer 150 may be made of or comprise hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or combinations thereof. The gate dielectric layer 150 may be deposited using ALD processes, CVD processes, one or more other applicable processes, or combinations thereof.

[0103] In some embodiments, an interface layer is formed on the surface of the semiconductor nanostructures 104a'-104c' prior to the formation of the gate dielectric layer 150. The interface layer is very thin and is made of, for example, silicon oxide or germanium oxide. In some embodiments, the interface layer is formed by applying an oxidant to the surface of the semiconductor nanostructures 104a'-104c'. For example, a liquid containing hydrogen peroxide may be applied to or provided to the surface of the semiconductor nanostructures 104a'-104c' to form the interface layer.

[0104] The power function adjustment layer 152 can be used to provide the desired work function to the transistor to improve device performance, including an improved threshold voltage. In some embodiments, the power function adjustment layer 152 surrounding the semiconductor nanostructures 104a'-104c' is used to form an NMOS device. The power function adjustment layer 152 is an n-type power function adjustment layer. The n-type power function adjustment layer is capable of providing a power function value suitable for the device, such as equal to or less than about 4.5 eV.

[0105] The n-type work function adjustment layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function adjustment layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function adjustment layer is a titanium-containing layer. The titanium-containing layer may be made of or include TiAl, TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.

[0106] In some embodiments, the power function adjustment layer 152 surrounding the semiconductor nanostructures 104a'-104c' is used to form a PMOS device. In these cases, the power function adjustment layer 152 is a p-type power function adjustment layer. The p-type power function adjustment layer is capable of providing a power function value suitable for the device, such as equal to or greater than about 4.8 eV.

[0107] The p-type work function adjustment layer may include a metal, a metal carbide, a metal nitride, another suitable material, or a combination thereof. For example, p-type metals include titanium nitride, tantalum nitride, tungsten nitride, titanium, one or more other suitable materials, or a combination thereof. In some embodiments, the p-type work function adjustment layer is a titanium-containing layer.

[0108] The power function adjustment layer 152 may also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminum compounds, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the power function adjustment layer 152 can be adjusted to modify the power function level.

[0109] A power function adjustment layer 152 can be deposited over the gate dielectric layer 150 using ALD, CVD, PVD, electroplating, electroless plating, one or more other suitable processes, or combinations thereof. In some embodiments, the formation of the power function adjustment layer involves one or more patterning processes. As a result, n-type power function adjustment layers and p-type power function adjustment layers can be selectively formed over different regions.

[0110] In some embodiments, different portions of the metal gate stacks 156A-156B and 156A'-156B' encapsulate semiconductor nanostructures 104a'-104c' of different devices, including PMOS and NMOS devices. Therefore, different portions of the metal gate stacks 156A and 156B have different types of power function adjustment layers or different combinations of power function adjustment layers. Multiple deposition processes and multiple patterning processes can be used to selectively form different power function adjustment layers at different portions of the metal gate stacks 156A-156B and 156A'-156B'.

[0111] In some embodiments, a barrier layer is formed prior to the power function adjustment layer 152 to connect the gate dielectric layer 150 to the subsequently formed power function adjustment layer 152. The barrier layer may also prevent diffusion between the gate dielectric layer 150 and the subsequently formed power function adjustment layer 152. The barrier layer may be made of or comprise a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or combinations thereof. The barrier layer may be deposited using ALD, CVD, PVD, electroplating, electroless plating, one or more other suitable processes, or combinations thereof.

[0112] In some embodiments, the conductive filler 154 of the metal gate stacks 156A-156B and 156A'-156B' is made of or comprises a metallic material. The metallic material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or combinations thereof. A conductive layer for forming the conductive filler 154 may be deposited over the power function adjustment layer 152 using CVD, ALD, PVD, electroplating, electroless plating, spin coating, one or more other suitable processes, or combinations thereof.

[0113] In some embodiments, a barrier layer is formed over the work function adjustment layer 152 prior to the formation of the conductive layer for forming the conductive filler 154. The barrier layer serves to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function adjustment layer 152. The barrier layer may be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or combinations thereof. The barrier layer may be deposited using ALD processes, PVD processes, electroplating processes, electroless plating processes, one or more other suitable processes, or combinations thereof.

[0114] Subsequently, according to some embodiments, a planarization process is performed to remove portions of the metal gate stack layer outside the trench 142 and recess 144. As a result, as... Figure 3L As shown, the remaining portion of the metal gate stack layer forms metal gate stacks 156A-156B and 156A'-156B'.

[0115] In some embodiments, the groove 144 is filled after the functional adjustment layer 152 is formed. As a result, as Figure 3L As shown, according to some embodiments, the subsequently formed conductive filler 154 can be prevented from entering the groove 144. In some embodiments, the conductive filler 154 fills the remaining space of the groove 142.

[0116] like Figure 3L As shown, each of the metal gate stacks 156A-156B and 156A'-156B' has an upper portion located above the semiconductor nanostructure 104c'. Each of the metal gate stacks 156A-156B and 156A'-156B' also has a lower portion located below the semiconductor nanostructure 104c'. Figure 3L As shown, the lower portion has a first portion with a width of W1, a second portion with a width of W2, and a third portion with a width of W3. The third portion is located between semiconductor nanostructures 104c' and 104b', and next to the internal spacer 136C. The second portion is located between semiconductor nanostructures 104b' and 104a', and next to the internal spacer 136B. The first portion is located between semiconductor nanostructure 104a' and semiconductor fin 101A, and next to the internal spacer 136A. In some embodiments, the width W3 is greater than the width W2, and the width W2 is greater than the width W1.

[0117] In some embodiments, semiconductor layers 102a-102c are replaced with dielectric nanostructures 306a-306c before forming the epitaxial structure 138. During the thermal process for forming the epitaxial structure 138, the germanium-containing semiconductor layers 102a-102c have been removed. Therefore, the diffusion of germanium impurities from semiconductor layers 102a-102c to semiconductor nanostructures 104a'-104c' is significantly reduced or prevented. As a result, semiconductor nanostructures 104a'-104c' have a low atomic concentration of germanium impurities, improving the quality and reliability of semiconductor nanostructures 104a'-104c'. Semiconductor nanostructures 104a'-104c' may have an atomic concentration of germanium impurities ranging from about 0% to about 0.01%.

[0118] In some embodiments, the semiconductor nanostructures 104a'-104c' are primarily composed of silicon and exhibit high etch selectivity compared to the dielectric nanostructures 306a-306c. As a result, minimal or no over-etching is required to remove the dielectric nanostructures 306a-306c and release the semiconductor nanostructures 104a'-104c'. This significantly reduces the surface roughness of the semiconductor nanostructures 104a'-104c', which in turn reduces current congestion and surface scattering. Consequently, the electrical properties of the semiconductor nanostructures 104a'-104c', including carrier mobility, are enhanced.

[0119] like Figure 3M As shown, according to some embodiments, an etch stop layer 158 and a dielectric layer 160 are deposited sequentially. The material and formation method of the etch stop layer 158 may be the same as or similar to the material and formation method of the contact etch stop layer 139. The material and formation method of the dielectric layer 160 may be the same as or similar to the material and formation method of the dielectric layer 140.

[0120] Subsequently, according to some embodiments, such as Figure 3M As shown, a metal-semiconductor compound structure 162 and conductive contacts 164 are formed. In some embodiments, dielectric layer 160, etch stop layer 158, dielectric layer 140, and contact etch stop layer 139 are partially removed to form contact openings exposing the epitaxial structure 138. A protective layer 159 is then deposited over the sidewalls and bottom of the contact opening. Then, one or more etching processes are used to remove portions of the protective layer 159 at the bottom of the contact opening and to deepen the contact opening. As a result, the contact opening extends further into the epitaxial structure 138.

[0121] After cleaning the surface of the epitaxial structure 138, a metal layer (such as titanium and / or nickel) is deposited on the epitaxial structure 138. A thermal operation can be used to initiate a reaction between the metal layer and the epitaxial structure 138. As a result, a metal-semiconductor compound structure 162 is formed. The remaining portion of the metal layer extending on the sidewalls of the contact opening can then be removed using a cleaning operation.

[0122] Next, a conductive layer is deposited to overfill the contact opening. The conductive layer can be made of or include tungsten, cobalt, ruthenium, titanium, another suitable material, or a combination thereof. The conductive layer can be deposited using CVD, ALD, PVD, electroplating, another suitable process, or a combination thereof. Then, a planarization process (such as CMP) is used to remove portions of the conductive layer outside the contact opening. The result is as follows: Figure 3M As shown, according to some embodiments, the remaining portion of the conductive layer forms a conductive contact 164. The conductive contact 164 can be used as a front conductive structure electrically connected to the epitaxial structure 138.

[0123] In some embodiments, the conductivity of the metal-semiconductor compound structure 162 is between that of the epitaxial structure 138 and the conductivity of the conductive contact 164. In some embodiments, each of the metal-semiconductor compound structure 162 and the conductive contact 164 has a higher conductivity than the epitaxial structure 138. In some embodiments, such as Figure 3M As shown, each metal-semiconductor compound structure 162 includes a curved profile.

[0124] like Figure 3N As shown, according to some embodiments, a front-side interconnect structure 166 is formed over a dielectric layer 160 and conductive contacts 164. The front-side interconnect structure 166 may include multiple dielectric layers and multiple conductive components. The conductive components may include multiple conductive contacts, multiple conductive vias, and multiple wires. Various device elements can be integrated through these conductive components.

[0125] After that, as Figure 3N As shown, according to some embodiments, a carrier substrate 170 is bonded to a front-side interconnect structure 166 via a bonding layer 168. The carrier substrate 170 may include a semiconductor substrate (such as a silicon wafer), a dielectric substrate (such as a glass wafer), another suitable substrate, or a combination thereof. The bonding layer 168 may be an oxide-containing layer. The bonding layer 168 may include multiple sublayers. The carrier substrate 170 may be bonded to the front-side interconnect structure 166 via oxide-to-oxide bonding.

[0126] like Figure 3OAs shown, according to some embodiments, the semiconductor substrate 100 is thinned. As a result, the bottoms of the semiconductor fins 101A and 101A' and the isolation structure 115 ( Figure 3O (Not shown in the image) Exposed. The semiconductor substrate 100 can be thinned using a planarization process such as CMP. The semiconductor fin 101A and the isolation structure 115 can now be used together as a substrate.

[0127] like Figure 3P As shown, a patterned mask element 320 is formed over semiconductor fin 101A. The patterned mask element 320 has an opening that defines the location and outline of a via opening to be formed later. The patterned mask element 320 may be made of or include silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, another suitable material, or a combination thereof. The formation of the patterned mask element 320 may include a deposition process to form a mask layer, followed by a patterning process that defines the mask layer as the patterned mask element 320. The patterning process may include one or more photolithography processes and one or more etching processes.

[0128] Subsequently, using a patterned mask element 320 as an etching mask, an etching process is used to partially remove semiconductor fins 101A and 101A' to form via openings 322A and 322B. The semiconductor isolation structure 137 in portion R1 is closer to the opening of the patterned mask element 320 and is made of a material other than semiconductor fins 101A. For example, the semiconductor isolation structure 137 may include silicon germanium. Therefore, the semiconductor isolation structure 137 and the isolation element 308 in portion R1 are also partially removed, deepening the via opening 322A to expose the bottom of the epitaxial structure 138 in portion R1. The semiconductor isolation structure 137 in portion R2 is spaced apart from the opening of the patterned mask element 320. Therefore, the semiconductor isolation structure 137 and the isolation element 308 in portion R2 are not etched. In some embodiments, such as Figure 3P As shown, the through-hole opening 322A is deeper than the through-hole opening 322B. In some embodiments, such as Figure 3P As shown, due to the etching process, the via opening 322B also extends upward into the semiconductor fin 101A'. The semiconductor fin 101A' is also partially etched.

[0129] like Figure 3Q As shown, according to some embodiments, a mask element 324 is formed to cover the through-hole opening 322A. The mask element 324 has an opening that exposes the semiconductor fin 101A'. Then, according to some embodiments, such as Figure 3QAs shown, a doped region 328 is formed near the bottom of the via opening 322B. In some embodiments, an ion implantation process 326 is used to form the doped region 328.

[0130] In some embodiments, the doped region 328 and the epitaxial structure 138 above the doped region 328 are doped in opposite directions. In some embodiments, the epitaxial structure 138 is n-type doped, and the doped region 328 is p-type doped. The p-type dopant in the doped region 328 may include boron (B), gallium (Ga), indium (In), or another suitable dopant. In some other embodiments, the epitaxial structure 138 is p-type doped, and the doped region 328 is n-type doped. The n-type dopant in the doped region 328 may include phosphorus (P), antimony (Sb), arsenic (As), another suitable element, or a combination thereof.

[0131] In some embodiments, portions of the patterned mask element 320 are also exposed by openings in the mask element 324. In some embodiments, during the ion implantation process 326, some dopant used to form the doped region 328 may also enter the exposed surface portion of the patterned mask element 320 near the via opening 322B. In some embodiments, other portions of the patterned mask element 320 covered by the mask element 324 during the ion implantation process 326 are substantially free of dopant used to form the doped region 328.

[0132] In some embodiments, such as Figure 3Q As shown, the doped region 328 is vertically spaced from the epitaxial structure 138 and the semiconductor discrete structure 137 above it. In some embodiments, such as Figure 3Q As shown, the middle portion of the doped region 328 is thicker than the edge portions of the doped region 328. The doped region 328 and the epitaxial structure 138 can together form a vertical PIN diode. In some embodiments, the doped region 328 and the epitaxial structure 138 can be used for electrostatic discharge (ESD) applications.

[0133] In some embodiments, the dopant concentration of the epitaxial structure 138 is greater than the dopant concentration of the doped region 328. The dopant concentration of the epitaxial structure 138 can be from about 10... 20 cm -3 To about 10 21 cm -3 Within a certain range. The dopant concentration in doped region 328 can range from approximately 10... 12 cm -3 To about 10 20 cm -3 Within a certain range. In some cases, if the dopant concentration in doped region 328 is too high (e.g., greater than about 10), 20 cm -3Dopant may diffuse from doped region 328 into the epitaxial structure 138 above, adversely affecting its performance and reliability. In other cases, if the dopant concentration in doped region 328 is too low (e.g., below about 10⁻⁶), the dopant may diffuse into the epitaxial structure 138 above, adversely affecting its performance and reliability. 12 cm -3 The depletion region may become too wide, which could lead to an undesirable high ESD trigger voltage.

[0134] Subsequently, according to some embodiments, such as Figure 3R As shown, mask element 324 is removed to expose through-hole opening 322A.

[0135] Next, a protective layer 174 is deposited over the sidewalls and bottom of via openings 322A and 322B. Then, one or more etching processes are used to remove portions of the protective layer 174 at the bottom of via openings 322A and 322B. After cleaning operations on the exposed bottom surface of the epitaxial structure 138 in portion R1 and the bottom surface of the doped region 328 in portion R2, a metal layer (such as titanium and / or nickel) is deposited on the epitaxial structure 138 and the doped region 328. Thermal operations can be used to initiate a reaction between the metal layer and the epitaxial structure 138 and the doped region 328. As a result, metal-semiconductor compound structures 176A and 176B are formed. Then, cleaning operations can be used to remove the remaining portions of the metal layer extending on the sidewalls of via openings 322A and 322B.

[0136] After that, as Figure 3S As shown, according to some embodiments, back-side conductive structures 178A and 178B are formed to partially or completely fill via openings 322A and 322B. In some embodiments, a conductive layer is deposited to overfill via openings 322A and 322B. The conductive layer may be made of or comprise tungsten, cobalt, ruthenium, titanium, another suitable material, or a combination thereof. The conductive layer may be deposited using CVD, ALD, PVD, electroplating, another suitable process, or a combination thereof. A portion of the conductive layer outside via openings 322A and 322B is then removed using a planarization process (such as CMP). As a result, as Figure 3S As shown, the remaining portion of the conductive layer forms back-side conductive structures 178A and 178B.

[0137] In some embodiments, the electrical conductivity of the metal-semiconductor compound structures 176A and 176B is between that of the epitaxial structure 138 (or the doped region 328) and the electrical conductivity of the back-side conductive structures 178A and 178B. In some embodiments, each of the metal-semiconductor compound structures 176A and 176B and the back-side conductive structures 178A and 178B has a greater electrical conductivity than the epitaxial structure 138 or the doped region 328. In some embodiments, each of the metal-semiconductor compound structures 176A and 176B includes a curved profile.

[0138] like Figure 3T As shown, according to some embodiments, a back-side interconnect structure 340 is then formed over the patterned mask element 320 and back-side conductive structures 178A and 178B. The back-side interconnect structure 340 may include multiple dielectric layers and multiple conductive components, including conductive components 342A and 342B. The conductive components may include multiple conductive contacts, multiple conductive vias, and multiple wires. Various device elements can be integrated through these conductive components.

[0139] Figure 4A This is a top view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments. (e.g.) Figure 4A As shown, the semiconductor device structure has regions RA and RB. In some embodiments, Figure 3T The structure in the middle, part R1, is formed in region RA, and Figure 3T Part R2 of the structure is formed in region RB. Figure 4A The diagram also shows the back-side conductive structures 178A and 178B of portions of R1 and R2. In some embodiments, in cross-sectional views (such as...) Figure 3T As shown), the back-side conductive structure 178A is longer than the back-side conductive structure 178B, and in the top view (such as...) Figure 4A (As shown) Backside conductive structure 178B is closer to the corner C of the semiconductor device structure than backside conductive structure 178A.

[0140] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 4B This is a top view of an intermediate stage of the process for forming a portion of a semiconductor device structure according to some embodiments. In some embodiments, the region RB having a vertical PIN diode laterally surrounds the region RA.

[0141] Many variations and / or modifications can be made to the embodiments of this disclosure. In some embodiments, three channel structures (such as semiconductor nanostructures 104a'-104c') are formed adjacent to a nearby epitaxial structure. However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure. In some embodiments, more than three semiconductor nanostructures are formed adjacent to a nearby epitaxial structure. In some other embodiments, fewer than three semiconductor nanostructures are formed adjacent to a nearby epitaxial structure. The total number of semiconductor nanostructures (or channel structures) formed adjacent to a nearby epitaxial structure can be fine-tuned to meet requirements. For example, 2 to 10 semiconductor nanostructures can be formed adjacent to a nearby epitaxial structure. Semiconductor nanostructures can have many suitable profiles. Semiconductor nanostructures can include nanosheets, nanowires, or other suitable nanostructures.

[0142] In some embodiments, such as Figures 3B to 3E As shown, semiconductor layers 102a-102c are replaced with dielectric nanostructures 306a-306c. However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, semiconductor layers 102a-102c are not replaced with dielectric nanostructures 306a-306c. In some embodiments, this is not performed. Figures 3C to 3E The process is shown in the diagram. In these cases, it is similar to... Figure 3F Then, the semiconductor layers 102a-102c are partially removed to form a recess 132 for accommodating the subsequently formed internal spacers.

[0143] In some embodiments, only one type of doping region is formed (such as...) Figure 3T (Doped region 328 in the text). However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, n-type doped regions and p-type doped regions are formed.

[0144] Figure 5 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments. For example... Figure 5 As shown, the semiconductor device structure includes portions P1 and P2. Figure 5 As shown, an n-type doped epitaxial structure 138N, a p-type doped epitaxial structure 138P, an internal spacer 136, and a metal gate stack 156 are formed. The metal gate stack 156 in portion P1 includes an n-type work function adjustment layer 152N. The metal gate stack 156 in portion P2 includes a p-type work function adjustment layer 152P. It can be used... Figures 3A to 3T The similar forming process shown forms each of sections P1 and P2. Similar reference numerals are used to denote similar elements.

[0145] In part P1, a p-type doped region 328P is formed below one of the n-type doped epitaxial structures 138N. In some embodiments, the p-type doped region 328P is perpendicularly spaced from the semiconductor discrete structure 137 and the n-type doped epitaxial structure 138N. Figure 5 As shown, the back-side conductive structure 178B in portion P1 has a height H3, and the semiconductor discrete structure 137 has a height H1. The back-side conductive structure 178B and the semiconductor discrete structure 137 are perpendicularly spaced apart by a distance H2. The height H1 can range from about 8 nm to about 14 nm. The height H3 can range from about 8 nm to about 14 nm. The distance H2 can range from about 20 nm to about 26 nm.

[0146] In some cases, if the distance from H1 is outside the range of approximately 8 nm to approximately 14 nm, the formation of the back-side conductive structure 178A in part of R1 (e.g., see...) Figures 3N to 3S This may be adversely affected. In some cases, if the distance to H2 is less than approximately 20 nm, the back-side conductive structure 138B and the p-type doped region 328P may be too close to the epitaxial structure 138N, which may lead to high PN junction leakage in some situations. In some other cases, if the distance to H2 is greater than approximately 26 nm, the back-side conductive structure 138B and the p-type doped region 328P may be too far from the epitaxial structure 138N, which may lead to high PN junction resistance.

[0147] In part P2, an n-type doped region 328N is formed below one of the p-type doped epitaxial structures 138P. In some embodiments, the n-type doped region 328N is perpendicularly spaced from the semiconductor discrete structure 137 and the p-type doped epitaxial structure 138P. Figure 5 As shown, the back-side conductive structure 178B' in portion P2 has a height H3', and the semiconductor discrete structure 137 has a height H1'. The back-side conductive structure 178B' is perpendicularly spaced from the semiconductor discrete structure 137 by a distance H2'. The height H1' can range from about 8 nm to about 14 nm. The height H3' can range from about 8 nm to about 14 nm. The distance H2' can range from about 20 nm to about 26 nm. In some embodiments, the n-type doped region 328N and the p-type doped region 328P are formed separately. Patterned mask elements can be used to assist in the formation of the n-type doped region 328N and the p-type doped region 328P in different ion implantation processes.

[0148] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 6 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments. Formation and Figure 5A structure similar to the one shown. In some embodiments, the p-type doped region 328P extends upward to reach the upper semiconductor separation structure 137. In some embodiments, the n-type doped region 328N extends upward to reach the upper semiconductor separation structure 137. The heights of the n-type doped region 328N and the p-type doped region 328P can be adjusted as needed by fine-tuning the ion implantation process used to form the n-type doped region 328N and the p-type doped region 328P.

[0149] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 7 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, according to some embodiments. Formation and Figure 5 A structure similar to the one shown. In some embodiments, the p-type doped region 328P extends upward to enter the upper semiconductor separation structure 137. In some embodiments, the n-type doped region 328N extends into the upper semiconductor separation structure 137. The heights of the n-type doped region 328N and the p-type doped region 328P can be adjusted as needed by fine-tuning the ion implantation process used to form the n-type doped region 328N and the p-type doped region 328P.

[0150] In some embodiments, such as Figures 3H to 3I As shown, the semiconductor discrete structure 137 and the isolation element 308 are formed prior to the formation of the epitaxial structure 138. However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, the semiconductor discrete structure 137 and the isolation element 308 are not formed.

[0151] Figure 8 This is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. In some embodiments, the semiconductor discrete structure 137 and the isolation element 308 are not formed. In some embodiments, the n-type doped epitaxial structure 138N and the p-type doped epitaxial structure 138P are formed directly on the semiconductor fin 101. In some embodiments, such as Figure 8 As shown, each of the n-type doped epitaxial structure 138N and the p-type doped epitaxial structure 138P has a circular bottom surface. In some embodiments, the p-type doped region 328P is perpendicularly spaced from the circular bottom surface of the n-type doped epitaxial structure 138N. In some embodiments, the n-type doped region 328N is perpendicularly spaced from the circular bottom surface of the p-type doped epitaxial structure 138P.

[0152] Embodiments of this disclosure form a semiconductor device structure having a semiconductor nanostructure and a back-side conductive structure, the back-side conductive structure extending toward an epitaxial structure adjacent to the semiconductor nanostructure. A doped region is formed between the back-side conductive structure and the epitaxial structure. The doped region and the epitaxial structure are doped in opposite directions. The doped region and the epitaxial structure can together form a vertical PIN diode suitable for electrostatic discharge (ESD) applications. The doped region is vertically spaced from the epitaxial structure, thereby preventing dopant from diffusing into the upper epitaxial structure and adversely affecting it. Therefore, the performance and reliability of the semiconductor device structure are significantly improved.

[0153] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor nanostructure and an epitaxial structure adjacent to the semiconductor nanostructure. The epitaxial structure has a first portion and a second portion, the second portion being spaced apart from the semiconductor nanostructure by the first portion, and the first portion and the second portion having different dopant concentrations. The semiconductor device structure also includes a conductive structure located below the epitaxial structure and a doped region located between the epitaxial structure and the conductive structure. The doped region is spaced apart from the epitaxial structure, and the doped region and the epitaxial structure are doped in opposite directions. The doped region is electrically connected to the conductive structure.

[0154] In some embodiments, the epitaxial structure is n-type doped, and the doped region is p-type doped.

[0155] In some embodiments, the middle portion of the doped region is thicker than the edge portion of the doped region.

[0156] In some embodiments, the semiconductor device structure further includes: a second semiconductor nanostructure; a second epitaxial structure located next to the second semiconductor nanostructure; a second conductive structure located below the second epitaxial structure; and a second doped region located between the second epitaxial structure and the second conductive structure, wherein the second doped region is spaced apart from the second epitaxial structure, the second doped region and the second epitaxial structure are doped in opposite directions, and the doped region and the second doped region are doped in opposite directions.

[0157] In some embodiments, the semiconductor device structure further includes a semiconductor discrete structure located between the epitaxial structure and the doped region.

[0158] In some embodiments, the semiconductor discrete structure is substantially undoped.

[0159] In some embodiments, the semiconductor separation structure is perpendicularly spaced from the doped region.

[0160] In some embodiments, the doped region extends upward to reach the semiconductor discrete structure.

[0161] In some embodiments, the doped region extends into the semiconductor discrete structure.

[0162] In some embodiments, the semiconductor device structure further includes: a second semiconductor nanostructure; a second epitaxial structure located next to the second semiconductor nanostructure; and a second conductive structure located below the second epitaxial structure and electrically connected to the second epitaxial structure, wherein the second conductive structure is longer than the conductive structure.

[0163] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a semiconductor nanostructure over a substrate and forming an epitaxial structure adjacent to the sidewalls of the semiconductor nanostructure. The method further includes forming a gate stack over the semiconductor nanostructure. The gate stack has a gate dielectric layer and a titanium-containing gate electrode. The method further includes forming an opening extending toward the bottom of the epitaxial structure. The opening is spaced apart from the epitaxial structure. Furthermore, the method includes performing an implantation process to form a doped region near the bottom of the opening, wherein the doped region and the epitaxial structure are oppositely doped. The method includes forming a conductive structure that partially or completely fills the opening.

[0164] In some embodiments, the method further includes: forming a second semiconductor nanostructure; forming a second epitaxial structure next to the second semiconductor nanostructure; forming a second doped region below the second epitaxial structure, wherein the second doped region is spaced apart from the second epitaxial structure, the second doped region and the second epitaxial structure are doped in opposite directions, and the doped region and the second doped region are doped in opposite directions; and forming a second conductive structure below the second epitaxial structure.

[0165] In some embodiments, the method further includes: forming a second semiconductor nanostructure; forming a second epitaxial structure next to the second semiconductor nanostructure; forming a second opening that exposes the bottom of the second epitaxial structure; and forming a second conductive structure in the second opening.

[0166] In some embodiments, the method further includes covering the bottom of the second epitaxial structure during the formation of the doped region.

[0167] In some embodiments, in a cross-sectional view, the second conductive structure is longer than the conductive structure, and in a top view, the conductive structure is closer to the corner of the semiconductor device structure than the second conductive structure.

[0168] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a plurality of sacrificial nanostructures and a plurality of semiconductor nanostructures over a substrate. The sacrificial nanostructures and semiconductor nanostructures are arranged alternately. The method further includes partially removing the sacrificial nanostructures and semiconductor nanostructures to form a trench exposing the side surfaces of the sacrificial nanostructures and semiconductor nanostructures. The method further includes forming an epitaxial structure in the trench, with the epitaxial structure located adjacent to the semiconductor nanostructures. Furthermore, the method includes removing the sacrificial nanostructures and forming a gate stack enclosing the semiconductor nanostructures. The gate stack has a gate dielectric layer having a dielectric constant greater than that of gate spacers formed adjacent to the gate stack. The method includes forming a doped region extending upward toward the bottom of the epitaxial structure. The doped region and the epitaxial structure have different dopants, and the doped region is spaced apart from the epitaxial structure. The method further includes forming a conductive structure electrically connected to the doped region. The conductivity of the conductive structure is greater than that of the epitaxial structure.

[0169] According to some embodiments, a method for forming a semiconductor device structure is provided, comprising: forming a plurality of sacrificial nanostructures and a plurality of semiconductor nanostructures over a substrate, wherein the sacrificial nanostructures and the semiconductor nanostructures are arranged alternately; forming an epitaxial structure next to the semiconductor nanostructures; removing the sacrificial nanostructures; forming a gate stack enclosing the semiconductor nanostructures, wherein the gate stack has a gate dielectric layer and the dielectric constant of the gate dielectric layer is greater than the dielectric constant of a gate spacer formed next to the gate stack; forming a doped region extending upward toward the bottom of the epitaxial structure, wherein the doped region and the epitaxial structure have different dopants and the doped region is spaced apart from the epitaxial structure; and forming a conductive structure electrically connected to the doped region, wherein the conductivity of the conductive structure is greater than the conductivity of the epitaxial structure.

[0170] In some embodiments, the method further includes forming a semiconductor isolation structure prior to forming the epitaxial structure, wherein the semiconductor isolation structure is located between the epitaxial structure and the substrate.

[0171] In some embodiments, the method further includes: forming a plurality of second sacrificial nanostructures and a plurality of second semiconductor nanostructures over the substrate, wherein the second sacrificial nanostructures and the second semiconductor nanostructures are arranged alternately; forming a second epitaxial structure next to the second semiconductor nanostructures; forming a second semiconductor separation structure prior to forming the second epitaxial structure, wherein the second semiconductor separation structure is located between the second epitaxial structure and the substrate; removing the second sacrificial nanostructures; partially removing the substrate to form an opening exposing the bottom of the second epitaxial structure; and forming a second conductive structure that at least partially fills the opening.

[0172] In some embodiments, the second semiconductor discrete structure is longer than the semiconductor discrete structure.

[0173] In some embodiments, the doped region and the epitaxial structure are doped in opposite directions.

[0174] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, comprising: Semiconductor nanostructures; An epitaxial structure is located next to the semiconductor nanostructure, wherein the epitaxial structure has a first portion and a second portion, the second portion being spaced apart from the semiconductor nanostructure by the first portion, and the first portion and the second portion having different dopant concentrations; A conductive structure is located below the epitaxial structure; and A doped region is located between the epitaxial structure and the conductive structure, wherein the doped region is spaced apart from the epitaxial structure, the doped region is electrically connected to the conductive structure, and the doped region and the epitaxial structure are doped in opposite directions.

2. The semiconductor device structure according to claim 1, wherein, The epitaxial structure is n-type doped, and the doped region is p-type doped.

3. The semiconductor device structure according to claim 1, wherein, The middle portion of the doped region is thicker than the edge portion of the doped region.

4. The semiconductor device structure according to claim 1, further comprising: Second semiconductor nanostructure; The second epitaxial structure is located next to the second semiconductor nanostructure; The second conductive structure is located below the second epitaxial structure; as well as The second doped region is located between the second epitaxial structure and the second conductive structure, wherein the second doped region is spaced apart from the second epitaxial structure, the second doped region and the second epitaxial structure are doped in opposite directions, and the doped region and the second doped region are doped in opposite directions.

5. The semiconductor device structure according to claim 1, further comprising: A semiconductor discrete structure is located between the epitaxial structure and the doped region.

6. The semiconductor device structure according to claim 5, wherein, The semiconductor discrete structure is essentially undoped.

7. The semiconductor device structure according to claim 5, wherein, The semiconductor separation structure is perpendicularly spaced from the doped region.

8. The semiconductor device structure according to claim 5, wherein, The doped region extends upward to reach the semiconductor discrete structure.

9. A method for forming a semiconductor device structure, comprising: Semiconductor nanostructures are formed on the substrate; An epitaxial structure is formed adjacent to the sidewall of the semiconductor nanostructure; A gate stack is formed on top of the semiconductor nanostructure, wherein the gate stack has a gate dielectric layer and a titanium-containing gate electrode; An opening is formed extending toward the bottom of the epitaxial structure, wherein the opening is spaced apart from the epitaxial structure; An implantation process is performed to form a doped region near the bottom of the opening, wherein the doped region and the epitaxial structure are oppositely doped; and A conductive structure is formed that at least partially fills the opening.

10. A method for forming a semiconductor device structure, comprising: Multiple sacrificial nanostructures and multiple semiconductor nanostructures are formed on a substrate, wherein the sacrificial nanostructures and the semiconductor nanostructures are arranged alternately. An epitaxial structure is formed next to the semiconductor nanostructure; Remove the sacrificial nanostructure; A gate stack is formed to encapsulate the semiconductor nanostructure, wherein the gate stack has a gate dielectric layer and the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer formed next to the gate stack; A doped region is formed extending upward toward the bottom of the epitaxial structure, wherein the doped region and the epitaxial structure have different dopants, and the doped region is spaced apart from the epitaxial structure; and A conductive structure is formed that is electrically connected to the doped region, wherein the conductivity of the conductive structure is greater than the conductivity of the epitaxial structure.

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