Integrated circuit structure with uniform grid metal gate and trench contact plug for barrel gate with pyramidal channel structure

Abstract

Disclosed herein are integrated circuit structures with uniform grid metal gates and trench contact plugs for barrel gates with pyramidal channel structures. Integrated circuit structures with uniform grid metal gates and trench contact cuts with pyramidal channel structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramidal angle. A gate electrode is positioned over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure has a concave profile with a cut angle laterally spaced apart from the pyramidal angle of the pyramidal profile of the vertical stack of horizontal nanowires.

Description

[0001] This application is a divisional application of Chinese patent application No. 202311789979.0, filed on December 25, 2023, entitled "Integrated circuit structure with a uniform grid metal gate for barrel gate and trench contact plug with a pyramidal channel structure". Technical Field

[0002] The embodiments disclosed herein belong to the field of integrated circuit structure and fabrication, and specifically to an integrated circuit structure having a uniform grid metal gate and trench contact cuts, and a method for fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts. Background Technology

[0003] Over the past few decades, feature scaling in integrated circuits has been a driving force behind the continued growth of the semiconductor industry. Scaling to increasingly smaller features allows for increased density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of an increased number of memory or logic devices on a single chip, facilitating the creation of products with increased capacity. However, the pursuit of ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly critical.

[0004] In the fabrication of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors) have become increasingly prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and the ability to implement less complex tri-gate fabrication processes. On the other hand, as microelectronic device dimensions scale down to below the 10-nanometer (nm) node, maintaining improved mobility and short-channel control presents challenges in device fabrication. Nanowires used to fabricate devices offer improved short-channel control.

[0005] However, scaling up multi-gate and nanowire transistors is not without its consequences. As the size of these basic building blocks of microelectronic circuit systems decreases, and as the absolute number of basic building blocks fabricated in a given area increases, limitations on the photolithography processes used to pattern these building blocks become unavoidable. In particular, there may be a trade-off between the minimum size (critical size) of a feature patterned in a semiconductor stack and the spacing between such features. Attached Figure Description

[0006] Figures 1A-1D Angled cross-sectional and plan views are shown of various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cutouts, according to embodiments of the present disclosure.

[0007] Figures 2A-2C A cross-sectional view illustrating a comparative aspect of an integrated circuit structure having a uniform grid metal gate and trench contact cutouts according to an embodiment of the present disclosure is shown.

[0008] Figure 3 A cross-sectional view illustrating a comparative aspect of an integrated circuit structure having a uniform grid metal gate and trench contact cutouts according to an embodiment of the present disclosure is shown.

[0009] Figure 4A A cross-sectional view of an integrated circuit structure having fins and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0010] Figure 4B A cross-sectional view of an integrated circuit structure having fins and a notched metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0011] Figure 5A A cross-sectional view of an integrated circuit structure having nanowires and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0012] Figure 5B A cross-sectional view of an integrated circuit structure having nanowires and notched metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0013] Figures 6A-6D Cross-sectional views of various operations in a method for fabricating a full-around-gate integrated circuit structure having a subtractive metal gate structure with a barrel-shaped architecture are shown.

[0014] Figures 6E-6H Cross-sectional views are shown of various operations in a method for fabricating a fully all-around gate integrated circuit structure having a barrel-shaped additive metal gate structure according to embodiments of the present disclosure.

[0015] Figures 7A-7J Cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure according to embodiments of the present disclosure are shown.

[0016] Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0017] Figure 9 A cross-sectional view through nanowires and fins is shown of a non-end cap architecture (left-hand side (a)) according to an embodiment of the present disclosure relative to a self-aligned gate end cap (SAGE) architecture (right-hand side (b)).

[0018] Figure 10Cross-sectional views are shown of various operations in a method for fabricating a self-aligned gate end cap (SAGE) structure having a fully surrounding gate device, according to embodiments of the present disclosure.

[0019] Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0020] Figure 11B An embodiment according to this disclosure is shown. Figure 11A A cross-sectional view of the source or drain of a nanowire-based integrated circuit structure taken along the a-a' axis.

[0021] Figure 11C An embodiment according to this disclosure is shown. Figure 11A A cross-sectional channel view of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0022] Figure 12 A computing device according to one embodiment of the present disclosure is shown.

[0023] Figure 13 An intermediary layer including one or more embodiments of the present disclosure is shown. Detailed Implementation

[0024] An integrated circuit structure having a uniform grid metal gate and trench contact notch is described, as well as a method for fabricating an integrated circuit structure having a uniform grid metal gate and trench contact notch. In the following description, numerous specific details, such as specific integration and material systems, are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features (e.g., integrated circuit design layouts) have not been described in detail to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0025] For reference purposes only, certain terms may also be used in the following description and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientations in the referenced figures. Terms such as “front,” “rear,” “back,” and “side” describe the orientation and / or position of portions of a component within a consistent but arbitrary frame of reference, which are readily apparent from the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0026] The embodiments described herein are applicable to front-end process (FEOL) semiconductor fabrication and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0027] The embodiments described herein are applicable to back-end process (BEOL) semiconductor fabrication and structures. BEOL is the second part of IC fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for chip-to-package connections. During the fabrication phase of BEOL, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0028] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme can be illustrated using the FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using the BEOL processing scenario, such a method can also be applied to FEOL processing.

[0029] One or more embodiments described herein relate to an integrated circuit structure fabricated as a uniform grid including a metal gate and trench contact cutouts, which may be referred to as a pixel structure. One or more embodiments described herein relate to a full-around gate device fabricated using multiple common and extended metal gate cutout (MGC) trench contact (TCN) cutout plug structures. It should be understood that, unless otherwise specified, references to nanowires herein may refer to nanowires, nanoribbons, or nanosheets. One or more embodiments described herein relate to a FinFET structure fabricated using multiple common and extended metal gate cutout (MGC) trench contact (TCN) cutout plug structures. In embodiments, the associated channel structure is pyramidal, such as a pyramidal arrangement of a full-around gate (GAA) structure (e.g., nanowires, nanoribbons, or nanosheets) or pyramidal fins.

[0030] To provide background, it may be advantageous to simplify trench contact and polysilicon notch (gate notch) processes, for example, to improve device performance and reduce process variations.

[0031] According to one or more embodiments of this disclosure, a metal gate process is performed, and a trench contact process is performed without the need for plugs. A single, "infinitely" long grid is then used to generate all possible trench contact plugs and gate cutout plugs. The resulting structure may be referred to as a pixel structure. The pixel structure may then undergo partial plug removal to effectively reconnect or re-connect the cutout gate portions and / or reconnect the cutout contact portions.

[0032] As an example processing scheme, Figures 1A-1D Angled cross-sectional and plan views are shown of various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cutouts, according to embodiments of the present disclosure.

[0033] refer to Figure 1A A start-up structure 100 is shown prior to the nanowire release and gate replacement process. The start-up structure 100 includes sub-fins 104 extending from a substrate 102, such as silicon sub-fins extending from a silicon substrate. The sub-fins 104 extend through a shallow trench isolation (STI) structure 106, such as a silicon oxide or silicon dioxide trench isolation structure. One or more stacks of horizontal nanowires 108 (e.g., stacks of horizontal silicon nanowires) lie on the corresponding sub-fins 104. At this stage, a sacrificial intermediary layer 110 (e.g., a sacrificial silicon-germanium intermediary layer) alternates with the horizontal nanowires 108 in the nanowire stacks. A sacrificial gate oxide 112 (e.g., a silicon oxide or silicon dioxide sacrificial gate oxide) lies on the stacks of horizontal silicon nanowires 108. A sacrificial gate structure 114 (e.g., a polysilicon sacrificial gate structure) lies on the sacrificial gate oxide 112 and on the channel regions of the stacks of horizontal nanowires 108. As depicted, a hard mask layer 116 (e.g., a silicon nitride hard mask layer) may be included on the sacrificial gate structure 114. A gate spacer forming material 118 (e.g., a silicon nitride gate spacer forming material 118) is included on the sacrificial gate structure 114 and along the sidewalls of the sacrificial gate structure 114.

[0034] Refer again Figure 1AThe epitaxial source or drain structure 120 (e.g., epitaxial silicon or epitaxial silicon-germanium source or drain structure) is located at the end of the stack of horizontal nanowires 108 between adjacent sacrificial gate structures 114. An internal gate spacer 126 (e.g., an internal silicon nitride internal gate spacer 126) can be formed by recessing the sacrificial intercalary layer 110 and depositing the internal gate spacer material prior to forming the epitaxial source or drain structure 120. The epitaxial source or drain structure 120 can be formed on top of the lower spacer recess filler 122 (e.g., a silicon nitride spacer filler), which can be formed simultaneously with the internal gate spacer 126 and / or the gate spacer forming material 118. A contact insulator structure 128 (e.g., a silicon oxide or silicon dioxide structure) is included on top of the epitaxial source or drain structure 120 and can occupy the location where the conductive trench contact is ultimately formed.

[0035] refer to Figure 1B The initial structure 100 undergoes a replacement gate and nanowire release process. Specifically, structure 100 is planarized and / or etched to expose the sacrificial gate structure 114. Planarization may remove the hard mask layer 116, form the gate spacer 118A from the gate spacer forming material 118, and form a planarized contact insulator structure 128A. Selective etching is then used to remove the sacrificial gate structure 114 and the sacrificial gate oxide 112. Selective etching is then used to remove the sacrificial intermediary layer 110. A permanent gate dielectric structure 132 (e.g., a gate dielectric structure including a high-k dielectric layer) is then formed in the resulting trenches and cavities (including around the channel regions of each nanowire in the nanowires 108). A permanent gate electrode 134 (e.g., a gate electrode including a metal) is formed on top of the permanent gate dielectric structure 132 (including at locations around the channel regions of the nanowires 108). For example, a gate insulating capping layer 136 (e.g., a silicon nitride capping layer) can be formed by recessing the gate structure and backfilling it with a dielectric on the resulting permanent gate electrode structure 134.

[0036] refer to Figure 1C and Figure 1D The cross-sectional view of the exposed trench contact area is used. Figure 1C ) and cross-sectional view of the exposed gate structure ( Figure 1DThe pixel structure 149 is shown. The pixel structure 149 is formed by first replacing the planarized contact insulator structure 128A with a trench contact material. At this stage, the trench contact material is "infinite" along each contact trench, extending over all source / drain structures along a given trench contact line, effectively shorting all trench contacts along a single trench contact line. Similarly, at this stage, the gate electrode material is "infinite" along each gate trench, extending over all nanowire stack channel regions along a given gate line, effectively shorting all gates along a single gate line contact line. At this stage, the gate insulating cap layer 136 may have been removed.

[0037] Subsequently, non-selective cuts are made in a direction orthogonal to the gate and trench contact lines. These non-selective cuts effectively cut and isolate all trench contacts along a single trench contact line and cut and isolate all gate electrodes along a single gate line. The cuts are then filled with dielectric plugs 148 extending through all trench contact lines and all gate lines. The resulting “pixel” structure 149 includes multiple isolated / cut trench contact structures 140, which may include insulating caps 142 located thereon. The trench contact structures 140 may contact a silicide layer 146 located on the corresponding epitaxial source or drain structure 120 at locations exposed by the etch stop layer 144. The resulting “pixel” structure 149 also includes multiple isolated / cut gate structures, for example, structures including cut gate dielectrics 132A and 134A.

[0038] Refer again Figure 1C and Figure 1D According to embodiments of this disclosure, the integrated circuit structure 149 includes a vertical stack of horizontal nanowires 108. A gate electrode 134A is located on the vertical stack of horizontal nanowires 108. A conductive trench contact 140 is adjacent to the gate electrode 134A. A dielectric sidewall spacer 118A is located between the gate electrode 134A and the conductive trench contact 140. A first dielectric notch plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. A second dielectric notch plug structure 148 extends through the gate electrode 140, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. The second dielectric notch plug structure 148 is laterally spaced from and parallel to the first dielectric notch plug structure 148.

[0039] It should be understood that pixel structure 149 may then undergo selective reconnection or reconnection of the individual isolation / cut trench contact structures in isolation / cut trench contact structure 140, and / or selective reconnection or reconnection of the individual isolation / cut gate structures in isolation / cut gate structures 132A / 134A, for example, using selective etching to remove metal gate cut (MGC) trench contact (TCN) plugs. Such a processing scheme can be used to effectively remove metal gate cut (MGC) plugs added during trench contact (TCN) plug patterning to restore continuity in the gate metal.

[0040] In another aspect, a pyramidal GAA pixel barrel gate architecture is described.

[0041] For context, pixel barrel gate architectures can be implemented after HiK deposition and before metal gate metallization via metal gate cleavage (MGC). Pixel barrel gates can achieve dipole patterning without HiK damage using relaxable EPE immersion lithography instead of expensive tight EPE EUV lithography, enabling independent VT control on multi-VT devices with tight design rules for advanced nodes. However, due to the concave profile of the MGC and the floating end cap (EC) of the MGC, pixel barrel gate architectures can be prone to creating W-fill voids or other metal-fill voids between the nanoribbon (NR) stack and the MGC (especially for tight minimum EC < 6-8 nm), which can lead to device failure.

[0042] According to one or more embodiments of this disclosure, a pyramidal NR stack is implemented instead of a straight / vertical NR stack to move the minimum EC pinch-off point from the top NR to the bottom NR, and thus facilitate bottom-up W-fill. This embodiment can realize the benefits of metal gate patterning while making the barrel walls smooth and relatively easy to fabricate via MGC after HiK deposition. Embodiments can be implemented to utilize the end cap “dead” space that can be associated with the MGC recessed profile to build a useful LNR footprint by widening NR3-4Zwa, which in turn can improve transistor drive / performance at the same cell height.

[0043] According to one or more embodiments of this disclosure, the pixel barrel gate has recessed MGC walls that separate each device. A work function (WF) layer may serve as a liner for the MGC, indicating that the MGC has been completed prior to MG metallization. HiK may be absent on the MGC sidewalls. In embodiments, the NR stack has a pyramidal shape rather than a vertical / straight shape. In embodiments, the NR pyramid angle is greater than or equal to the MGC angle relative to a vertical reference line. The gate metal filler may be W, Mo, TiN, or TiAlC. It should be understood that metal gate patterning using a pyramidal pixel barrel gate architecture can also be applied to FinFET transistors.

[0044] To illustrate the above concepts, Figures 2A-2C A comparative cross-sectional view of an integrated circuit structure with a uniform grid metal gate and trench contact cutouts according to embodiments of the present disclosure is shown. It should be understood that although nanowires or nanoribbons are described and shown, finFET architectures (e.g., tapering outwards from top to bottom) may also be used.

[0045] refer to Figure 2A In part (a), structure 200 is shown as being cut through the channel and gate region (as a gate-centered fin cut) after the pixel or barrel structure fabrication process, in which the cut and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. Structure 200 includes a gate bottom 202 and a gate top 204. The NMOS barrel gate 206 and PMOS barrel gate 208 include corresponding nanowires 212 and gate stacks 210, and are defined by spaced dielectric plugs 214 formed at the cut location (metal gate cut, MGC). Since the cut is made after the gate replacement, a possible edge placement error (EPE) is shown, which may cause a variation in the dielectric plug position 214, for example, a floating end cap (floating EC). However, for the example of structure 200, the end cap edge placement error is normal (EPE=0). The nanowire stack 212 of structure 200 has a straight-edge profile 216, and the dielectric plug 214 has a concave profile 218. The arrangement of the structure may easily create voids (e.g., at location 219).

[0046] refer to Figure 2AIn contrast to part (a), structure 220 is shown as being cut through the channel and gate region (as a gate-centered fin cut) after the pixel or barrel structure fabrication process, in which the cut and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. Structure 220 includes a gate bottom 222 and a gate top 224. The NMOS barrel gate 226 and PMOS barrel gate 228 include corresponding nanowires 232 and gate stacks 230, and are defined by spaced dielectric plugs 234 formed at the cut location (metal gate cut, MGC). Since the cut is made after the gate replacement, a possible edge placement error (EPE) is shown, which may cause variations in the dielectric plug position 234, for example, a floating end cap (floating EC). However, for the example of structure 220, the end cap edge placement error is normal (EPE=0). Because the nanowires 232 gradually widen along the central axis 236 from top 224 to bottom 222, the nanowire stack 232 of structure 220 has a pyramidal profile. The dielectric plug 234 has a concave profile 238. However, the pyramidal profile of the nanowires can accommodate the concave profile of the dielectric plug 234 to suppress void formation during bottom-up gate filling in the direction of the arrow at position 239.

[0047] refer to Figure 2B In part (a), structure 240 is shown as being cut through the channel and gate region (as a gate-centered fin cut) after the pixel or barrel structure fabrication process, in which the cut and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. Structure 240 has the same characteristics as... Figure 2A The features of structure 200 in part (a) are similar, except that the end cap edge placement error is non-zero (EPE≠0). Specifically, the dielectric plug 214A is offset relative to the nanowire stack. This can result in a pinch-off of the metal gate filler between the top NR1 and the plug 214A, which in turn hinders the impending entry of the metal filler chemistry below the pinch-off position, resulting in a subsequent metal filler void at position 242, which could lead to a non-functional or affected device.

[0048] refer to Figure 2BIn contrast to part (a), structure 250 is shown as being cut through the channel and gate region (as a gate-centered fin cut) after the pixel or barrel structure fabrication process, in which the cut and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. Structure 250 has the same characteristics as... Figure 2A The features of structure 220 in part (b) are similar, except that the end cap edge placement error is non-zero (EPE ≠ 0). Specifically, the dielectric plug 234A is offset relative to the nanowire stack. However, the pyramidal profile of the nanowires can be accommodated by shifting the pinch position between the bottom NR4 and the plug 234A downwards to accommodate the concave profile of the dielectric plug 234A. The new pinch position provides access to the incoming metal fill chemistry throughout the end cap region and facilitates gapless bottom-up gate filling.

[0049] refer to Figure 2C Part (a) of the diagram, structure 260, is shown as being cut through the channel and gate region (as a gate-centered fin cut) after the pixel or barrel structure fabrication process, in which the cut and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. (See also...) Figure 2A Part (a) and Figure 2B As described in part (a), structure 260 includes a nanowire stack 212 having a straight edge profile laterally adjacent to a dielectric plug 214 having a concave profile. Such an arrangement structure effectively has unused "dead" end cap space 262.

[0050] refer to Figure 2C In contrast to part (a), structure 270 is shown as being cut through the channel and gate region (as a gate-centered fin cut) after the pixel or barrel structure fabrication process, in which the cut and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. (See also...) Figure 2A Part (b) and Figure 2B As described in part (b), structure 270 includes a nanowire stack 232 having a pyramidal profile laterally adjacent to a dielectric plug 234 having a concave profile. The concave profile of the dielectric plug 234 is... Figure 2C The portion (b) is referred to as the Metal Gate Cutter (MGC) corner. The pyramidal profile of the nanowire stack 232 is... Figure 2CThe portion (b) is referred to as the pyramid angle. The MGC angle is overlaid on the nanowire stack 232 for comparison purposes. In an embodiment, as depicted, the pyramid angle is larger than the MGC angle. In a particular embodiment, the resulting difference (e.g., 1 nm) between the bottommost nanowire and the dielectric plug 234 is smaller than the resulting difference between the topmost nanowire and the dielectric plug 234, and therefore, the difference at the bottom sets the tolerance (LNR) of the structural offset. Thus, the space between the nanowire stack 232 and the dielectric plug 234 is effectively open from bottom to top, thereby facilitating metal gate filling.

[0051] In other embodiments, the pyramid angle is the same as the MGC angle. In other embodiments, the pyramid angle is smaller than the MGC angle.

[0052] In another aspect, a pyramidal GAA pixel barrel source-drain architecture is described.

[0053] For background, because the EPI chemicals / precursors enter from the top and EPI growth is not vertical but angled, conventional straight nanoribbons (NR) promote cup-shaped EPIs. Bottom EPIs are typically narrower than top EPIs. This result may influence the bottom NR. A decrease in I has a negative impact, reducing the drive current through the bottom nanowire. Furthermore, a narrower bottom EPI may negatively affect the bottom contact resistance architecture.

[0054] According to one or more embodiments of this disclosure, a pyramidal NR stack is used instead of a straight / vertical NR stack to take advantage of the available / additional spacing provided by the pixel (MGC) barrel S / D architecture. The pyramidal NR enables a box-shaped EPI (wider bottom EPI), which reduces the bottom EPI resistance and increases the bottom drive current. It also increases the ZWA by between 6-15% for a 1nm LNR margin and an 89-degree MGC (pixel) angle, thereby improving overall transistor performance. Pixel walls prevent EPI-EPI shorting, thus improving yield.

[0055] Implementations can be devised to ensure that top-polarized NMOS devices are exposed to a minimum number of 0-1 dry etching cycles, just as bottom-polarized PMOS devices are exposed to the same level of etching. This uniquely enables high NMOS device reliability / leakage / performance for the CFET architecture. In embodiments, the barrel S / D may have recessed MGC walls that separate each device and prevent EPI-EPI shorting. In embodiments, the NR Si protrusions have a pyramidal shape rather than a vertical / straight shape. In embodiments, the NR pyramid angle is greater than or equal to the MGC angle relative to the vertical reference line. It should be understood that the pyramidal pixel barrel S / D architecture can also be applied to FinFET transistors.

[0056] To illustrate the above concepts, Figure 3 Cross-sectional and planar views illustrating comparative aspects of an integrated circuit structure having a uniform grid metal gate and trench contact cutouts according to embodiments of the present disclosure are shown. It should be understood that although nanowires or nanoribbons are described and shown, finFET architectures (e.g., tapering outwards from top to bottom) may also be used.

[0057] refer to Figure 3 In part (a), structure 300 is shown as being cut through the source or drain region (as an epitaxial notch centered on the source or drain region) after the pixel or barrel structure fabrication process, in which the notch and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. Structure 300 includes a source or drain bottom 302 and a source or drain top 304. Structure 300 includes an NMOS barrel source or drain region 306 and a PMOS barrel source or drain region 308, the NMOS barrel source or drain region 306 and the PMOS barrel source or drain region 308 respectively including an N-type epitaxial source or drain structure 316 and a P-type epitaxial source or drain structure 318 (where nanowires 312 entering the page are shown as dashed lines), and are defined by spaced dielectric plugs 314 formed at the notch location. Since the notch is made after epitaxial source or drain growth, edge placement error (EPE) may occur, which could cause the position 315 of the dielectric plug 314 to change due to displacement relative to the vertical central axis of the corresponding nanowire stack (which has a straight edge profile 317). As depicted, the result could be restricted epitaxial growth at the bottom 302, which could lead to increased resistance.

[0058] refer to Figure 3In contrast to part (a), structure 320 is shown as being cut through the source or drain region (as an epitaxial notch centered on the source or drain region) after the pixel or barrel structure fabrication process, in which the notch and subsequent dielectric plug formation are performed after both the epitaxial source or drain region growth process and the gate replacement process. Structure 320 includes a source or drain bottom 322 and a source or drain top 324. Structure 320 includes an NMOS barrel source or drain region 326 and a PMOS barrel source or drain region 328, the NMOS barrel source or drain region 326 and the PMOS barrel source or drain region 328 respectively including an N-type epitaxial source or drain structure 336 and a P-type epitaxial source or drain structure 338 (where the nanowire 332 entering the page is shown as a dashed line), and is defined by a spaced dielectric plug 334 formed at the notch location. Since the notch is made after epitaxial source or drain growth, potential edge placement errors (EPE) may occur, which could cause the position 335 of the dielectric plug 334 to change due to displacement relative to the vertical central axis of the corresponding nanowire stack (which has a pyramidal profile 333). As depicted, the result could be a relatively improved and unrestricted epitaxial growth at the bottom 322, which could lead to a reduced (i.e., improved) resistance.

[0059] According to one or more embodiments of this disclosure, in order to solve the above-mentioned problems, a metal gate dicing process is performed after the gate dielectric and work function metal deposition and patterning are completed. In any case, in the embodiments, a gate plug formed after the metal gate formation (“last plug”) and / or a gate plug formed before the metal gate formation (“first plug”) (both will be described below) can be used in combination above. Figures 1A-1D , Figures 2A-2C and / or Figure 3 The gate / contact plug described.

[0060] Advantages of implementing the methods described herein can include the so-called “last plug” approach, which results in no gate dielectric layer (e.g., a high-k gate dielectric layer) being deposited on the gate plug sidewalls, thereby effectively saving additional space for work function metal deposition. In contrast, during the so-called conventional “first plug” approach, the metal gate fill material can be sandwiched between the plug and the fin. Due to plug mismatch in the latter approach, the space for the metal filler can be narrower, potentially leading to voids during metal filling. In the embodiments described herein, using the “last plug” approach, work function metal deposition can be seamless (e.g., void-free).

[0061] A dielectric gate plug can be fabricated for a FinFET device. As a comparative example, Figure 4A A cross-sectional view of an integrated circuit structure having fins and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 4B A cross-sectional view of an integrated circuit structure having fins and a notched metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0062] refer to Figure 4A The integrated circuit structure 400 includes a fin 402 having a portion extending over a shallow trench isolation (STI) structure 404. A gate dielectric material layer 406 (e.g., a high-k gate dielectric layer) is located over the extended portion of the fin 402 and over the STI structure 404. It should be understood that, although not depicted, an oxide portion of the fin 402 may be located between the extended portion of the fin 402 and the gate dielectric material layer 406, and may be included together with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408 (e.g., a work function metal layer) is located over the gate dielectric material layer 406, and may be located directly on the gate dielectric material layer 406 as depicted. A conductive gate fill material 410 is located over the conductive gate layer 408, and may be located directly on the conductive gate layer 408 as depicted. A dielectric gate cap 412 is located on the conductive gate fill material 410. The dielectric gate plug 414 is laterally spaced from the fin 402 and is located on the STI structure 404. The gate dielectric material layer 406 and the conductive gate layer 408 are along the side of the dielectric gate plug 414.

[0063] refer to Figure 4B The integrated circuit structure 450 includes a fin 452 having a portion extending over a shallow trench isolation (STI) structure 454. A gate dielectric material layer 456 (e.g., a high-k gate dielectric layer) is located over the extended portion of the fin 452 and over the STI structure 454. It should be understood that, although not depicted, an oxide portion of the fin 452 may be located between the extended portion of the fin 452 and the gate dielectric material layer 456, and may be included together with the gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458 (e.g., a work function metal layer) is located over the gate dielectric material layer 456, and may be located directly on the gate dielectric material layer 456 as depicted. A conductive gate fill material 460 is located over the conductive gate layer 458, and may be located directly on the conductive gate layer 458 as depicted. A dielectric gate cap 462 is located on the conductive gate fill material 460.

[0064] In one embodiment, the dielectric gate plug 464 is laterally spaced from the fin 452 and is located on the STI structure 454 but does not penetrate the STI structure 454. As used throughout the disclosure, a dielectric plug referred to as "located on but not penetrating" the STI structure can refer to a dielectric plug landing on the top or uppermost surface of the STI, or it can refer to a plug extending into but not piercing the STI. In other embodiments, the plug described herein may extend entirely through or pierce the STI.

[0065] In this embodiment, the gate dielectric material layer 456 and the conductive gate layer 458 do not lie along the sides of the dielectric gate plug 464. Instead, the conductive gate fill material 460 contacts the sides of the dielectric gate plug 464. As a result, the region between the dielectric gate plug 464 and the fin 452 comprises only one layer of gate dielectric material layer 456 and only one layer of conductive gate layer 458, thereby alleviating the space constraints in this narrow region of structure 450. Alleviating space constraints can improve metal filling and / or facilitate the patterning of multiple VTs.

[0066] Refer again Figure 4B In one embodiment, a dielectric gate plug 464 is formed after the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate fill material 460 are formed. As a result, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along the sidewalls of the dielectric gate plug 464. In one embodiment, as depicted, the dielectric gate plug 464 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 462. In another embodiment not depicted, the dielectric gate cap 462 is not included, and the dielectric gate plug 464, for example along plane 480, has an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 460.

[0067] Dielectric gate plugs can be fabricated for nanowire devices. As a comparative example, Figure 5A A cross-sectional view of an integrated circuit structure having nanowires and a front metal gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 5B A cross-sectional view of an integrated circuit structure having nanowires and notched metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0068] refer to Figure 5AThe integrated circuit structure 500 includes a sub-fin 502 having a portion extending over a shallow trench isolation (STI) structure 504. A plurality of horizontally stacked nanowires 505 are located above the sub-fin 502. A gate dielectric material layer 506 (e.g., a high-k gate dielectric layer) is located above the extended portion of the sub-fin 502, above the STI structure 504, and surrounding the horizontally stacked nanowires 505. It should be understood that, although not depicted, oxidized portions of the sub-fin 502 and the horizontally stacked nanowires 505 may be located between the extended portion of the sub-fin 502 and the gate dielectric material layer 506, and between the horizontally stacked nanowires 505 and the gate dielectric material layer 506, and may be included together with the gate dielectric material layer 506 to form a gate dielectric structure. A conductive gate layer 508 (e.g., a work function metal layer) is located over the gate dielectric material layer 506 and may be located directly over the gate dielectric material layer 506 as depicted. A conductive gate fill material 510 is located over the conductive gate layer 508 and may be located directly over the conductive gate layer 508 as depicted. A dielectric gate cap 512 is located over the conductive gate fill material 510. A dielectric gate plug 514 is laterally spaced from the sub-fins 502 and a plurality of horizontally stacked nanowires 505 and is located on the STI structure 504. The gate dielectric material layer 506 and the conductive gate layer 508 are along the sidewalls of the dielectric gate plug 514.

[0069] refer to Figure 5BThe integrated circuit structure 550 includes a sub-fin 552 having a portion extending over a shallow trench isolation (STI) structure 554. A plurality of horizontally stacked nanowires 555 are located above the sub-fin 552. A gate dielectric material layer 556 (e.g., a high-k gate dielectric layer) is located above the extended portion of the sub-fin 552, above the STI structure 554, and surrounding the horizontally stacked nanowires 555. It should be understood that, although not depicted, oxidized portions of the sub-fin 552 may be located between the extended portion of the sub-fin 552 and the gate dielectric material layer 556, and between the horizontally stacked nanowires 555 and the dielectric material layer 556, and may be included together with the gate dielectric material layer 556 to form a gate dielectric structure. A conductive gate layer 558 (e.g., a work function metal layer) is located above the gate dielectric material layer 556 and may be located directly on the gate dielectric material layer 556 as depicted. A conductive gate filler 560 is located on top of the conductive gate layer 558 and may be located directly on the conductive gate layer 558 as depicted. A dielectric gate cap 562 is located on the conductive gate filler 560. A dielectric gate plug 564 is laterally spaced from the sub-fins 552 and the plurality of horizontally stacked nanowires 555 and is located on the STI structure 554 but does not penetrate the STI structure 554. However, the gate dielectric material layer 556 and the conductive gate layer 558 do not run along the sides of the dielectric gate plug 564. Instead, the conductive gate filler 560 contacts the sides of the dielectric gate plug 564. As a result, the region between the dielectric gate plug 564 and the combination of the sub-fins 552 and the plurality of horizontally stacked nanowires 555 comprises only one layer of gate dielectric material layer 556 and only one layer of conductive gate layer 558, thereby alleviating the space constraints in this narrow region of structure 550.

[0070] Refer again Figure 5B In one embodiment, a dielectric gate plug 564 is formed after the gate dielectric material layer 556, the conductive gate layer 558, and the conductive gate fill material 560 are formed. As a result, the gate dielectric material layer 556 and the conductive gate layer 558 are not formed along the sidewalls of the dielectric gate plug 564. In one embodiment, as depicted, the dielectric gate plug 564 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 562. In another embodiment not depicted, the dielectric gate cap 562 is not included, and the dielectric gate plug 564, for example along plane 580, has an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 560.

[0071] In another aspect, one or more embodiments described herein are directed to all-around gate subtractive or additive metal gate patterning using pixel or barrel gate architectures. One or more embodiments described herein are directed to all-around gate devices fabricated using subtractive or additive metal gate fabrication schemes. It should be understood that, unless otherwise specified, references to nanowires can refer to nanowires, nanoribbons, or even nanosheets. It should also be understood that the embodiments are also applicable to FinFET architectures.

[0072] To provide further background, dipoles can be used to set the threshold voltage and achieve a relatively thinner work function metal layer. Embodiments can be implemented to set the threshold voltage (VT) by using a thin layer of dipoles, thereby replacing the thicker work function metal used in scaled devices of the prior art. Embodiments can provide multi-VT solutions and also provide ultra-low VT with a relatively thinner work function metal.

[0073] As an example of a process flow Figures 6A-6D Cross-sectional views of various operations in a method for fabricating a full-around-gate integrated circuit structure having a subtractive metal gate structure with a barrel-shaped architecture are shown.

[0074] refer to Figure 6A The initial structure 600 includes P-type and N-type regions separated by NP boundaries on a substrate 602. The P-type region includes a low-VT P-type device (P-LVT) location 604A and a standard-VT P-type device (P-SVT) location 604B. Both device locations 604A and 604B include multiple horizontal nanowires or nanoribbons 608. The N-type region includes a low-VT N-type device (N-LVT) location 606A and a standard-VT N-type device (N-SVT) location 606B. Both device locations 606A and 606B include multiple horizontal nanowires or nanoribbons 610. Each device location among 604A, 604B, 606A, and 606B is separated from adjacent device locations by a dielectric wall 605 (e.g., a silicon oxide, silicon nitride, or silicon oxynitride wall). The resulting structure can define a barrel structure for each device location 604A, 604B, 606A, and 606B. At this stage, a high-k gate dielectric layer (e.g., a hafnium oxide layer) can be formed around each of the multiple horizontal nanowires or nanoribbons 608 and 610, and can be retained as one of the permanent gate dielectric layers in the final structure.

[0075] refer to Figure 6B A common layer or stack of layers 612 is formed in all device locations 604A, 604B, 606A, and 606B. The common layer or stack of layers 612 may include a work function metal (WFM) layer, a dipole layer, or both a work function metal (WFM) layer and a dipole layer.

[0076] refer to Figure 6C A sacrificial dielectric layer hard mask 614 (e.g., a metal oxide) is formed in all device locations 604A, 604B, 606A, and 606B. As depicted, a patterned mask 616 (e.g., a carbon hard mask) is formed over the hard mask 614 and subsequently patterned with openings using anisotropic dry etching to expose only one type of device location, e.g., to expose device location 604A. As depicted, the openings 618 may be made smaller than the device locations to accommodate edge placement errors (EPE). Etching of the patterned openings is designed to stop on the hard mask 614. As depicted, the sacrificial hard mask 614 is then selectively removed only from the exposed device locations (e.g., only from device location 604A) using wet etching. As depicted, a common layer or stack of layers 612 is then removed only from the exposed device locations (e.g., only from device location 604A) using wet etching.

[0077] refer to Figure 6D A first device-specific layer or stack of layers is then formed at the first exposed device location (e.g., device location 604A). The device-specific layer or stack of layers may include a work function metal (WFM) layer, a dipole layer, or both a WFM layer and a dipole layer. The next device location is then opened and the process is repeated, optionally retaining or removing the common layer 612 in each case, until a complete structure (e.g., integrated circuit structure 649) is achieved. In the example shown, integrated circuit structure 649 includes a WFM / dipole stack 613A at device location 606A, a WFM / dipole stack 613B at device location 606B, a WFM / dipole stack 613C at device location 604A, and a WFM / dipole stack 613D at device location 604B. As depicted, a common gate conductive gate fill 620 is then formed at each of locations 606A, 606B, 604A, and 604B. It should be understood that, as will be visible on or off the page, the integrated circuit structure 649 may also include corresponding epitaxial source or drain structure pairs at the first and second ends of each vertical arrangement structure in the vertical arrangement structure of the horizontal nanowires 608 or 610.

[0078] refer to Figure 6D The subtractive barrel gate method includes subtractive WFM / dipole patterning using stacked WFM / dipole layers. The resulting structure 649 can be associated with low collective VT control, high VT variability, and / or only very thin (2x WFM, 1x dipole type) layers.

[0079] As another exemplary process flow Figures 6E-6HCross-sectional views are shown of various operations in a method for fabricating a fully all-around gate integrated circuit structure having a barrel-shaped additive metal gate structure according to embodiments of the present disclosure.

[0080] refer to Figure 6E The initial structure 650 includes P-type and N-type regions separated by NP boundaries on a substrate 652. The P-type region includes a low-VT P-type device (P-LVT) location 654A and a standard-VT P-type device (P-SVT) location 654B. Both device locations 654A and 654B include multiple horizontal nanowires or nanoribbons 658. The N-type region includes a low-VT N-type device (N-LVT) location 656A and a standard-VT N-type device (N-SVT) location 656B. Both device locations 656A and 656B include multiple horizontal nanowires or nanoribbons 660. Each device location among 654A, 654B, 656A, and 656B is separated from adjacent device locations by a dielectric wall 655 (e.g., a silicon oxide, silicon nitride, or silicon oxynitride wall). The resulting structure can define a barrel structure for each device location 654A, 654B, 656A, and 656B. At this stage, a high-k gate dielectric layer (e.g., a hafnium oxide layer) can be formed around each of the multiple horizontal nanowires or nanoribbons 658 and 660, and can be retained in the final structure as one of the permanent gate dielectric layers.

[0081] refer to Figure 6F A sacrificial dielectric layer hard mask 664 (e.g., a metal oxide) is formed in all device locations 654A, 654B, 656A, and 656B. As depicted, a patterned mask 666 (e.g., a carbon hard mask) is formed over the hard mask 664 and subsequently patterned with openings using anisotropic dry etching to expose only one type of device location, e.g., to expose device location 654A. As depicted, the openings 668 may be made smaller than the device locations to accommodate edge placement errors (EPE). Etching of the patterned openings is designed to stop on the hard mask 664. As depicted, the sacrificial hard mask 664 is then selectively (e.g., wet etching through the openings 668) removed only from the exposed device locations (e.g., only from device location 654A).

[0082] refer to Figure 6G Device-specific layers or stacks of layers 663C are then formed at the first exposed device location (e.g., device location 654A). The device-specific layers or stacks of layers may include a work function metal (WFM) layer, a dipole layer, or both a work function metal (WFM) layer and a dipole layer.

[0083] refer to Figure 6HThe process is then repeated by opening the next device location and continuing until a complete structure (e.g., integrated circuit structure 699) is achieved. In the example shown, integrated circuit structure 699 includes a device-specific layer or stack of layers 663A at device location 656A, a device-specific layer or stack of layers 663B at device location 656B, a device-specific layer or stack of layers 663C at device location 654A, and a device-specific layer or stack of layers 663D at device location 654B. As depicted, a common gate conductive gate fill 670 is then formed at each of locations 656A, 656B, 654A, and 654B.

[0084] refer to Figure 6H The addition barrel gate method can include a single WFM / dipole layer (thickness and / or composition) without stacking. The resulting structure 699 can be associated with high and single VT control as well as low VT variability and / or an unlimited number of WFM / dipole-specific devices.

[0085] Refer again Figure 6H According to embodiments of this disclosure, the integrated circuit structure 699 includes a first vertical arrangement of horizontal nanowires 658 and a second vertical arrangement of horizontal nanowires 660. A P-type gate stack 663C or 663D is located above the first vertical arrangement of the horizontal nanowires 658. The P-type gate stack 663C or 663D has a P-type conductive layer located above a first gate dielectric including a first dipole material layer. An N-type gate stack 663A or 663B is located above the second vertical arrangement of the horizontal nanowires 660. The N-type gate stack 663A or 663B has an N-type conductive layer located above a second gate dielectric including a second dipole material layer.

[0086] In an embodiment, a dielectric wall 655 is located between and in contact with the P-type gate stack and the N-type gate stack (e.g., as depicted, the dielectric wall 655 is located between and in contact with the P-type gate stack 663C and the N-type gate stack 663B). In an embodiment, the second dipole layer (e.g., in terms of thickness or composition or both) differs from the first dipole layer. In an embodiment, the first or second dipole material layer comprises oxides of La, Mg, Y, Ba, or Sr. In an embodiment, the first or second dipole material layer comprises oxides of Al, Ti, Nb, or Ga. In an embodiment, the first or second dipole material layer has a thickness in the range of 1-3 angstroms. In an embodiment, the first or second dipole material layer has a thickness in the range of 4-6 angstroms.

[0087] Refer again Figure 6H According to another embodiment of this disclosure, the integrated circuit structure 699 includes a first vertical arrangement of horizontal nanowires 658 on the left and a second vertical arrangement of horizontal nanowires 658 on the right. A first P-type gate stack 663C is located above the first vertical arrangement of horizontal nanowires 658 on the left. The first P-type gate stack 663C has a first P-type conductive layer located above a first gate dielectric including a first dipole material layer. A second P-type gate stack 663D is located above the second vertical arrangement of horizontal nanowires 658 on the right. The second P-type gate stack 663D has a second P-type conductive layer located above a second gate dielectric including a second dipole material layer. The second P-type gate stack 663D (e.g., in composition, thickness, etc.) differs from the first P-type gate stack 663C.

[0088] In an embodiment, as depicted, a dielectric wall 655 is located between and contacts the first P-type gate stack 663C and the second P-type gate stack 663D. In an embodiment, the second P-type conductive layer (e.g., in terms of thickness, composition, or both) differs from the first P-type conductive layer. In an embodiment, the second dipole layer (e.g., in terms of thickness, composition, or both) differs from the first dipole layer. In an embodiment, the first or second dipole material layer comprises oxides of La, Mg, Y, Ba, or Sr. In an embodiment, the first or second dipole material layer comprises oxides of Al, Ti, Nb, or Ga. In an embodiment, the first or second dipole material layer has a thickness in the range of 1-3 angstroms. In an embodiment, the first or second dipole material layer has a thickness in the range of 4-6 angstroms.

[0089] Refer again Figure 6H According to another embodiment of this disclosure, the integrated circuit structure 699 includes a first vertical arrangement of horizontal nanowires 660 on the left and a second vertical arrangement of horizontal nanowires 660 on the right. A first N-type gate stack 663A is located above the first vertical arrangement of the horizontal nanowires 660 on the left. The first N-type gate stack 663A has a first N-type conductive layer located above a first gate dielectric including a first dipole material layer. A second N-type gate stack 663B is located above the second vertical arrangement of the horizontal nanowires 660 on the right. The second N-type gate stack 663B has a second N-type conductive layer located above a second gate dielectric including a second dipole material layer. The second N-type gate stack 663B differs from the first N-type gate stack 663A (e.g., in composition, thickness, etc.).

[0090] In an embodiment, as depicted, a dielectric wall 655 is located between and contacts the first N-type gate stack 663A and the second N-type gate stack 663B. In an embodiment, the second N-type conductive layer (e.g., in terms of thickness, composition, or both) differs from the first N-type conductive layer. In an embodiment, the second dipole layer (e.g., in terms of thickness, composition, or both) differs from the first dipole layer. In an embodiment, the first or second dipole material layer comprises oxides of La, Mg, Y, Ba, or Sr. In an embodiment, the first or second dipole material layer comprises oxides of Al, Ti, Nb, or Ga. In an embodiment, the first or second dipole material layer has a thickness in the range of 1-3 angstroms. In an embodiment, the first or second dipole material layer has a thickness in the range of 4-6 angstroms.

[0091] According to embodiments of this disclosure, as will be visible on or off page, the integrated circuit structure 699 further includes corresponding epitaxial source or drain structure pairs located at the first and second ends of each vertically arranged structure in the vertical arrangement of the horizontal nanowires 658 or 660, examples of which are described in more detail below. In one embodiment, one or more conductive contact structures are located on corresponding one or more epitaxial source or drain structures, examples of which are described in more detail below. In one embodiment, the epitaxial source or drain structure pair is a non-discrete epitaxial source or drain structure pair, examples of which are described in more detail below. In one embodiment, the epitaxial source or drain structure pair is a discrete epitaxial source or drain structure pair, examples of which are described in more detail below.

[0092] It should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials (including but not limited to Si, SiGe, and Ge). For example, group III-V materials may be used.

[0093] It should be understood that, in certain embodiments, nanowires or nanoribbons or sacrificial intercalary layers may be made of silicon. As used throughout, a silicon layer can be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and therefore may include very small percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Thus, the embodiments for silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances (e.g., Ge, C, or Sn). It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms (e.g., boron, phosphorus, or arsenic). Germanium (Ge) may be considered similarly.

[0094] It should be understood that, in certain embodiments, the nanowires or nanoribbons or sacrificial intercalary layer may be composed of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed of a majority (e.g., at least 5% of both) of silicon and germanium. In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon-germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises approximately 30% germanium and approximately 70% silicon (Si). 70 Ge 30 It should be understood that, in practice, 100% pure silicon germanium (generally referred to as SiGe) may be difficult to form, and therefore may include a very small percentage of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may “contaminate” SiGe during diffusion during post-deposition processing. Thus, the embodiments for silicon germanium layers described herein may include silicon germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms (e.g., boron, phosphorus, or arsenic).

[0095] The following describes various apparatuses and fabrication methods that can be used to fabricate devices that can be integrated with nicked metal gates. It should be understood that exemplary embodiments do not necessarily require all the features described, or may include more features than described. For example, nanowire release fabrication can be performed by replacing the gate trench. Examples of such release processes are described below. Additionally, in another aspect, back-side (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to achieve front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide methods for achieving relatively wider interconnect pitches. The result can be improved product performance and lower patterning costs. Embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0096] One or more embodiments described herein pertain to biepitaxy (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In these embodiments, the integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor that is partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. A deep trench is formed on one of the source or drain sides to enable direct contact with the back-side interconnect layer.

[0097] This is an exemplary process flow for fabricating a gate-all-around integrated circuit structure. Figures 7A-7J Cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure according to embodiments of the present disclosure are shown.

[0098] refer to Figure 7A A method for fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 704 and nanowires 706 above fins 702 (e.g., silicon fins). The nanowires 706 may be referred to as a vertically arranged nanowire structure. As depicted, a protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706. Also as depicted, a relaxation buffer layer 752 and a defect modification layer 750 may be formed beneath the alternating sacrificial layers 704 and nanowires 706.

[0099] refer to Figure 7B A gate stack 710 is formed on top of the vertically arranged structure of horizontal nanowires 706. For example... Figure 7C As depicted, the vertical arrangement of the horizontal nanowires 706 is then released by removing a portion of the sacrificial layer 704 to provide a recessed sacrificial layer 704' and a cavity 712.

[0100] It should be understood that this process can be completed without first performing the deep etching and asymmetric contact machining described below. Figure 7C The structure. In either case (e.g., with or without asymmetric contact processing), in the embodiments, the fabrication process involves using a process scheme that provides a fully all-around gate integrated circuit structure with epitaxial bumps, which can be vertically discrete source or drain structures.

[0101] refer to Figure 7D An upper gate spacer 714 is formed at the sidewall of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 located below the upper gate spacer 714. Optionally, deep trench contact etching is then performed to form a trench 718 and a recessed nanowire 706'. As depicted, a patterned relaxation buffer layer 752' and a patterned defect modification layer 750' may also be present.

[0102] like Figure 7E As depicted, sacrificial material 720 is then formed in trench 718. In other process options, an isolated trench bottom or a silicon trench bottom can be used.

[0103] refer to Figure 7F A first epitaxial source or drain structure (e.g., left-handed feature 722) is formed at the first end of the vertically arranged structure of the horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right-handed feature 722) is formed at the second end of the vertically arranged structure of the horizontal nanowire 706'. In embodiments, as depicted, the epitaxial source or drain structure 722 is a vertically discrete source or drain structure and may be referred to as an epitaxial bump.

[0104] like Figure 7G As depicted, an interlayer dielectric (ILD) material 724 is then formed on the side of the gate electrode 710 and adjacent to the source or drain structure 722. (See reference...) Figure 7H The gate replacement process is used to form the permanent gate dielectric 728 and the permanent gate electrode 726. For example... Figure 7I As depicted in the diagram, the ILD material 724 is then removed. The sacrificial material 720 is then removed from one of the source and drain locations (e.g., the right-hand side) to form the trench 732, but the sacrificial material 720 is not removed from the other source and drain location to form the trench 730.

[0105] refer to Figure 7JA first conductive contact structure 734 is formed coupled to a first epitaxial source or drain structure (e.g., left-handed feature 722). A second conductive contact structure 736 is formed coupled to a second epitaxial source or drain structure (e.g., right-handed feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although... Figure 7J Not depicted, but the method also includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, wherein examples may include Ti, Ni, Co (for the former, and W, Ru, Co for the latter).

[0106] In one embodiment, as depicted, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734. In one such embodiment, as depicted, the first conductive contact structure 734 is not along the fin 702. In another such embodiment not depicted, the first conductive contact structure 734 partially follows the fin 702.

[0107] In one embodiment, the second conductive contact structure 736 extends along the entire fin 702. In another embodiment, although not depicted, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 when the bottom of the fin 702 is exposed via a backside substrate removal process.

[0108] In an embodiment, Figure 7J The structure or Figures 7A-7J The relevant structures in the image can be formed using pixel structure notching methods as described above.

[0109] On the other hand, in order to access two conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using a back-side exposure fabrication method for front-side structures. In some exemplary embodiments, back-side exposure of transistors or other device structures requires wafer-level back-side processing. Compared to conventional TSV-type techniques, back-side exposure of transistors as described herein can be performed at device cell density and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove all donor substrates on which device layers are disposed during front-side device processing. Thus, micrometer-deep TSVs become unnecessary when the thickness of the semiconductor in the device cell may be only tens or hundreds of nanometers after back-side exposure of the transistor.

[0110] The exposure techniques described in this paper enable a shift from a "bottom-up" device fabrication model to a "center-out" fabrication model, where the "center" is any layer that is used in front-side fabrication, exposed from the back side, and reused in back-side fabrication. When relying primarily on front-side fabrication, fabricating both the front and exposed back sides of the device structure can address many of the challenges associated with 3D IC fabrication.

[0111] Exposing the back side of the transistor can be employed, for example, to remove at least a portion of the carrier layer and intercalary layer of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning the semiconductor can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0112] In some embodiments, prior to the steps described above, the carrier layer is cleaved along a fracture plane substantially parallel to the intercalary layer. Cleavage or fracture processes can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved away by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer at a desired uniform target depth with a fracture plane. After such a cleavage process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the absence of fracture in the carrier layer, grinding, polishing, and / or etching operations can be used to remove a carrier layer of greater thickness.

[0113] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point at which the back surface of the donor substrate has advanced to near the device layer. Any known endpoint detection technique suitable for detecting the transition between the materials used in the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on changes in light absorption or emission detected on the back surface of the donor substrate during polishing and / or etching. In some other embodiments, the endpoint criteria are associated with changes in light absorption or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary as a function of the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the material in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the change in mass can be related to the different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the frictional force between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0114] Since the inhomogeneity in the carrier removal process can be mitigated by the difference in etching rates between the carrier layer and the intermediate layer, the detection of the intermediate layer can be enhanced when the removal process is selective for the carrier layer relative to the intermediate layer. If the grinding, polishing, and / or etching operations remove the intermediate layer at a rate sufficiently lower than that of the carrier layer, the detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations of a predetermined fixed duration can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient for the selectivity of the etching. In some examples, the carrier etching rate:intermediate layer etching rate is 3:1 to 10:1 or greater.

[0115] After exposing the intercalary layer, at least a portion of the intercalary layer can be removed. For example, one or more component layers within the intercalary layer can be removed. The thickness of the intercalary layer can be uniformly removed, for example, by polishing. Alternatively, a mask or blanket etching process can be used to remove the thickness of the intercalary layer. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intercalary layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more favorable for the removal of the intercalary layer than for the removal of the device layer. When removing an intercalary layer thickness of less than a few hundred nanometers, the removal process can be relatively slow, optimized for uniformity across the entire wafer, and can be more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, use a paste that provides very high selectivity (e.g., 100:1-300:1 or greater) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) surrounding the device layer and embedded within the intercalary layer (e.g., as electrical isolation between adjacent device regions).

[0116] For embodiments in which the device layer is exposed by completely removing the intervening layer, backside processing can begin on the exposed backside of the device layer or on a specific device region therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and the device regions (e.g., source or drain regions) previously formed in the device layer.

[0117] In some embodiments where wet and / or plasma etching is used to recess the back side of the carrier layer, intermediary layer, or device layer, such etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back side surface of the device layer. As further described below, patterning can be performed within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediary layer is used as a hard mask for patterning the back side device layer. Therefore, the mask etching process can precede the corresponding mask device layer etching.

[0118] The fabrication scheme described above can produce a donor-host substrate assembly including an IC device that exposes the back side of the intermediary layer, the back side of the device layer, and / or the back side and / or front side metallization of one or more semiconductor regions within the device layer. Further back-side processing can then be performed on any of these exposed regions during downstream processing.

[0119] It should be understood that the structure produced by the above exemplary fabrication scheme can be used in the same or similar form for subsequent fabrication operations to complete the device fabrication (e.g., PMOS and / or NMOS device fabrication). As an example of the completed device, Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0120] refer to Figure 8 The semiconductor structure or device 800 includes a nonplanar active region (e.g., a fin structure including an extended fin portion 804 and a sub-fin region 805) located within a trench isolation region 806. In an embodiment, as shown by dashed lines, the nonplanar active region is partitioned into nanowires (e.g., nanowires 804A and 804B) above the sub-fin region 805 instead of a solid fin. In either case, for ease of description of the nonplanar integrated circuit structure 800, the nonplanar active region 804 is hereinafter referred to as the extended fin portion. In an embodiment, as depicted, the sub-fin region 805 also includes a relaxation buffer layer 842 and a defect modification layer 840.

[0121] Gate line 808 is disposed over an extension 804 of a non-planar active region (including, if applicable, surrounding nanowires 804A and 804B) and a portion of a trench isolation region 806. As shown, gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, gate line 808 may further include a dielectric capping layer 854. From this viewpoint, it can also be seen that gate contact 814 and overlying gate contact via 816, together with overlying metal interconnect 860, are all disposed within an interlayer dielectric stack or layer 870. Figure 8 From this perspective, it can also be seen that in one embodiment, the gate contact 814 is disposed above the trench isolation region 806, but not above the non-planar active region. In another embodiment, the gate contact 814 is located above the non-planar active region.

[0122] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0123] For example Figure 8As depicted, in an embodiment, interface 880 exists between the protruding fin portion 804 and the sub-fin region 805. Interface 880 may be a transition region located between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doped layer located at the sub-fin site. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0124] although Figure 8 Not depicted, but it should be understood that the source or drain region of the protruding fin portion 804, or the source or drain region adjacent to the protruding fin portion 804, is located on either side of the gate line 808, i.e., inside or outside the page. In one embodiment, the material in the source or drain location of the protruding fin portion 804 is removed and replaced by another semiconductor material (e.g., by epitaxial deposition) to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to embodiments of this disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 880) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, as described above... Figure 7J As described, the source and drain regions have associated asymmetric source and drain contact structures.

[0125] Refer again Figure 8 In the embodiments, the fins 804 / 805 (and possibly the nanowires 804A and 804B) are composed of a crystalline silicon-germanium layer that may be doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0126] In embodiments, trench isolation region 806 and trench isolation regions (trench isolation structures or trench isolation layers) as described throughout may be made of materials suitable for ultimately electrically isolating portions of the permanent gate structure from the underlying body substrate or contributing to the isolation of portions of the permanent gate structure from the underlying body substrate, or suitable for isolating active regions (e.g., isolation fin active regions) formed within the underlying body substrate. For example, in one embodiment, trench isolation region 806 is made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0127] Gate line 808 may be formed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is formed of a metal gate, and the gate dielectric layer is formed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is formed of, but is not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer 852 may include a layer of native oxide formed from the top layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 is formed of a top high-k portion and a lower portion formed of an oxide of semiconductor material. In one embodiment, the gate dielectric layer 852 is formed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0128] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function filling material formed above the metal work function setting layer. Depending on whether the transistor is a PMOS transistor or an NMOS transistor, the gate electrode layer 850 may be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer 850 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments of this disclosure, the gate electrode may consist of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0129] The spacer associated with the gate electrode stack can be made of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (e.g., self-aligned contacts) or contributing to the isolation of the permanent gate structure from adjacent conductive contacts. For example, in one embodiment, the spacer is made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0130] The gate contact 814 and the overlying gate contact via 816 may be made of a conductive material. In an embodiment, one or more of the contacts or vias may be made of a metallic material. The metallic material may be a pure metal (e.g., tungsten, nickel, or cobalt) or an alloy (e.g., a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0131] In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 808, while eliminating the use of photolithography steps with extremely tight registration budgets. In an embodiment, for example, combined with Figure 7J The described contact patterns are either vertically symmetrical or asymmetrical. In other embodiments, all contacts are front-connected and not asymmetrical. In one such embodiment, the self-aligned method enables the generation of contact openings using inherently highly selective wet etching (e.g., compared to conventional dry or plasma etching). In embodiments, the contact patterns are formed by utilizing existing gate patterns in conjunction with contact plug lithography operations. In one such embodiment, the method eliminates the need for additional critical lithography operations used in conventional methods for generating contact patterns. In embodiments, the trench contact grid is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid notching.

[0132] In an embodiment, providing structure 800 involves fabricating a gate stack body structure 808 using a gate replacement process. In such an approach, a dummy gate material (e.g., polysilicon or silicon nitride pillar material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, contrary to what is done in earlier fabrications. In an embodiment, the dummy gate is removed using a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including aqueous phosphoric acid.

[0133] Refer again Figure 8The arrangement of the semiconductor structure or device 800 places the gate contact over an isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that partially contacts the gate electrode formed over an active region (e.g., over fin 805) and located in the same layer as the trench contact via.

[0134] In an embodiment, Figure 8 The structure can be formed using pixel structure notching methods as described above.

[0135] It should be understood that not all aspects of the above-described processes are required to fall within the spirit and scope of the embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. A semiconductor device can be a transistor or similar device. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic cells or memory, or a bipolar transistor. Additionally, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessible dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0136] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises, or includes, layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0137] In embodiments, and as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed of several layers, including conductive substrates and filler layers. Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes referred to in the art as traces, wires, lines, metals, or simply as interconnects.

[0138] In embodiments, as used throughout this specification, the hard mask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials can be used in different regions to provide different growth or etching selectivity relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping, or plug layers known in the art may be used. The hard mask, capping, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0139] In this embodiment, as used throughout this specification, 193nm immersion lithography (i193), EUV, and / or EBDW lithography are used to perform the lithography operation. Positive or negative photoresist can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography mask portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the antireflective coating layer is a silicon ARC layer.

[0140] In another aspect, one or more embodiments target adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may target the integration of multi-width (multiple Wsi) nanowires and nanoribbons within a SAGE architecture and separated by SAGE walls. In embodiments, the nanowires / nanoribbons integrate multiple Wsi within a portion of the SAGE architecture in a front-end process flow. Such a process flow can involve the integration of nanowires and nanoribbons with different Wsi to provide robust functionality for next-generation transistors with low power and high performance. The associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowire and then performing source or drain (S / D) growth).

[0141] To provide further background, the advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, and specifically, scaling diffusion to the diffusion pitch. For illustrative comparison, Figure 9 A cross-sectional view through nanowires and fins is shown of a non-end cap architecture (left-hand side (a)) according to an embodiment of the present disclosure relative to a self-aligned gate end cap (SAGE) architecture (right-hand side (b)).

[0142] refer to Figure 9 On the left-hand side (a), the integrated circuit structure 900 includes a substrate 902 with fins 904 extending an amount 906 above an isolation structure 908 laterally surrounding the lower portion of the fins 904. As depicted, the upper portion of the fins may include a relaxation buffer layer 922 and a defect modification layer 920. Corresponding nanowires 905 are located above the fins 904. A gate structure can be formed on the integrated circuit structure 900 to fabricate a device. However, breakpoints in such a gate structure can be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0143] In comparison, refer to Figure 9On the right-hand side (b), the integrated circuit structure 950 includes a substrate 952 having fins 954 that extend an amount 956 over an isolation structure 958 laterally surrounding the lower portion of the fins 954. As depicted, the upper portion of the fins may include a relaxation buffer layer 972 and a defect modification layer 970. Corresponding nanowires 955 are located above the fins 954. Isolation SAGE walls 960 (which may include a hard mask, as depicted) are included within the isolation structure 952 and between adjacent pairs of fins 954 / nanowires 955. The distance between the isolation SAGE wall 960 and the nearest pair of fins 954 / nanowires 955 defines the gate cap pitch 962. Gate structures may be formed on the integrated circuit structure 900 between the isolation SAGE walls to fabricate devices. Breakpoints in such a gate structure are caused by the isolation SAGE walls. Because the isolation SAGE wall 960 is self-aligned, limitations from conventional methods can be minimized to achieve more aggressive diffusion to the diffusion pitch. Furthermore, because the gate structure includes breakpoints at all locations, individual gate structure portions can be layered via local interconnects formed on the isolation SAGE wall 960. In embodiments, as depicted, each SAGE wall 960 includes a lower dielectric portion and a dielectric cap located on the lower dielectric portion. According to embodiments of this disclosure, for use with… Figure 9 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with epitaxial source or drain structures.

[0144] In an embodiment, Figure 9 The structure in part (a) can be formed using a pixel structure notching method as described above. In the embodiment, Figure 9 The structure in part (b) can be formed using pixel structure notching methods as described above.

[0145] The self-aligned gate end cap (SAGE) fabrication scheme involves forming a gate / trench contact end cap that is self-aligned to the fin without requiring additional length to accommodate mask mismatch. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0146] In an exemplary processing scheme for a structure having SAGE walls that separate adjacent devices, Figure 10 Cross-sectional views are shown illustrating various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a fully surrounding gate arrangement, according to embodiments of the present disclosure.

[0147] refer to Figure 10In part (a), the initial structure includes a nanowire patterned stack 1004 located above a substrate 1002. A photolithographic patterned stack 1006 is formed above the nanowire patterned stack 1004. As depicted, the nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be located above a relaxation buffer layer 1082 and a defect modification layer 1080. A protective mask 1014 is located between the nanowire patterned stack 1004 and the photolithographic patterned stack 1006. In one embodiment, the photolithographic patterned stack 1006 is a three-layer mask consisting of a topography mask portion 1020, an antireflective coating (ARC) 1022, and a photoresist layer 1024. In a particular such embodiment, the topography mask portion 1020 is a carbon hard mask (CHM) layer, and the antireflective coating 1022 is a silicon ARC layer.

[0148] refer to Figure 10 In part (b), the stack of part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trench 1030.

[0149] refer to Figure 10 The structures of parts (c) and (b) have an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave a patterned topographic mask layer 1020' as the exposed upper layer.

[0150] refer to Figure 10 In part (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002, for example, to define the protruding fin portion and to provide a trench isolation structure 1041 below the SAGE wall 1042.

[0151] refer to Figure 10 In part (e), at least in the channel region, the sacrificial layer 1010 is removed to release nanowires 1012A and 1012B. During the formation... Figure 10 Following the structure of portion (e), a gate stack can be formed around nanowires 1012B or 1012A, above the protruding fins of substrate 1002, and between SAGE walls 1042. In one embodiment, the remainder of protective mask 1014 is removed before forming the gate stack. In another embodiment, the remainder of protective mask 1014 is retained as an insulating fin cap, which serves as a residue of the processing method.

[0152] Refer again Figure 10Part (e) of the diagram should be understood to depict a channel view in which the source or drain regions are located inside or outside the page. In an embodiment, the channel region including nanowire 1012B has a smaller width than the channel region including nanowire 1012A. Therefore, in an embodiment, the integrated circuit structure includes nanowires of multiple widths (multiple Wsi). Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to as nanowires herein. It should also be understood that references or descriptions of fin / nanowire pairs throughout the text may refer to fins and one or more overlying nanowires (e.g., Figure 10 The structure of two overlying nanowires is shown. According to embodiments of this disclosure, it is used with... Figure 10 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with epitaxial source or drain structures.

[0153] In an embodiment, Figure 10 The structure in part (e) can be formed using pixel structure notching methods as described above.

[0154] In embodiments, as described throughout, the self-aligned gate end cap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from each other or contributing to the isolation of portions of the permanent gate structure from each other. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, and an upper portion of a material with a higher dielectric constant (e.g., hafnium oxide).

[0155] To highlight the exemplary integrated circuit structure with three vertically arranged nanowires, Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 11B It shows Figure 11A A cross-sectional view of the source or drain of a nanowire-based integrated circuit structure taken along the a-a' axis. Figure 11C It shows Figure 11A A cross-sectional channel view of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0156] refer to Figure 11AThe integrated circuit structure 1100 includes one or more vertically stacked nanowires (group 1104) located above a substrate 1102. In the depicted embodiments, as depicted, a relaxation buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102. For illustrative purposes, to emphasize the nanowire portion, optional fins located below the bottommost nanowire and formed by the substrate 1102 are not depicted. The embodiments herein pertain to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices having nanowires 1104A, 1104B, and 1104C are shown. For ease of description, nanowire 1104A is used as an example, wherein the description focuses on one nanowire among the nanowires. It should be understood that, in the case of describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire among the nanowires.

[0157] Each nanowire in nanowire 1104 includes a channel region 1106. The channel region 1106 has a length (L). Reference Figure 11C The channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 11A and Figure 11C Both, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region in the channel regions 1106. The gate electrode stack 1108 includes a gate electrode and a gate dielectric layer located between the channel regions 1106 and the gate electrode (not shown). In embodiments, the channel regions are discrete because they are completely surrounded by the gate electrode stack 1108 without any intervening material (e.g., a lower substrate material or an overlying channel fabrication material). Therefore, in embodiments with multiple nanowires 1104, the channel regions 1106 of the nanowires are also relatively discrete from each other.

[0158] refer to Figure 11A and Figure 11BBoth, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. This pair of non-discrete source or drain regions 1110 / 1112 is located on either side of a channel region 1106 of a plurality of vertically stacked nanowires 1104. Furthermore, this pair of non-discrete source or drain regions 1110 / 1112 is adjacent to the channel region 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment (not depicted), since epitaxial growth is performed on and between nanowire portions extending beyond the channel region 1106, this pair of non-discrete source or drain regions 1110 / 1112 is directly vertically adjacent to the channel region 1106, wherein the nanowire ends are shown as being within the source or drain structure. In another embodiment, as... Figure 11A As depicted, because they are formed at the ends of the nanowires rather than between the nanowires, this pair of non-discrete source or drain regions 1110 / 1112 are indirectly vertically adjacent to the channel region 1106.

[0159] In the embodiments, as depicted, since there is no single and discrete source or drain region for each channel region 1106 of the nanowire 1104, the source or drain regions 1110 / 1112 are non-discrete. Therefore, in embodiments with multiple nanowires 1104, contrary to the case where they are discrete for each nanowire, the source or drain regions 1110 / 1112 of the nanowires are global or uniform source or drain regions. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single uniform feature is used for the source or drain regions of multiple (in this case, three) nanowires 1104, and more specifically for the source or drain regions of more than one discrete channel region 1106. In one embodiment, viewed from a cross-sectional view orthogonal to the length of the discrete channel region 1106, as... Figure 11B As depicted, each of the pair of non-discrete source or drain regions 1110 / 1112 is generally rectangular in shape, with a bottom pyramidal portion and a top vertex portion. However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowire are relatively larger and discrete, non-vertically merged epitaxial structures, such as those combined with... Figures 7A-7J The described protrusion.

[0160] According to embodiments of this disclosure, and as Figure 11A and Figure 11BAs depicted, the integrated circuit structure 1100 also includes a pair of contacts 1114, each contact 1114 located on one of the source or drain regions 1110 / 1112 of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, vertically, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112. In another aspect, as... Figure 11B As depicted, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 may not be in contact with the contact portion 1114, and the contact portion 1114 therefore only partially surrounds the non-discrete source or drain regions 1110 / 1112. In a comparative embodiment not depicted, as truncated along the a-a' axis, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 is surrounded by the contact portion 1114.

[0161] Refer again Figure 11A In one embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, the outer portions of these spacers 1116 may partially overlap with non-discrete source or drain regions 1110 / 1112, thereby providing an "embedded" portion of the non-discrete source or drain regions 1110 / 1112 beneath these spacers 1116. Also as depicted, the embedded portion of the non-discrete source or drain regions 1110 / 1112 may not extend beneath the entirety of these spacers 1116.

[0162] Substrate 1102 may be made of a material suitable for fabricating integrated circuit structures. In one embodiment, substrate 1102 includes a lower body substrate made of a single-crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or III-V compound semiconductor materials. An upper insulating layer is located on the lower body substrate and may be made of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Therefore, structure 1100 can be fabricated from a semiconductor substrate on an insulator. Alternatively, structure 1100 is formed directly from the body substrate, and localized oxidation is used to form electrically insulating portions instead of the aforementioned upper insulating layer. In another alternative embodiment, structure 1100 is formed directly from the body substrate, and doping is used to form electrically isolated active regions (e.g., nanowires) thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an Ω-FET type structure.

[0163] In embodiments, the nanowire 1104 may be sized as a line or strip (as described below) and may have square or rounded corners. In embodiments, the nanowire 1104 is made of a material such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowire 1104, the single-crystal nanowire may be based on a (100) global orientation, for example, having […] in the z-direction. <100> Planar. Other orientations may also be considered, as described below. In embodiments, the nanowires 1104 are nanometer-sized when viewed from a cross-sectional perspective. For example, in a particular embodiment, the minimum size of the nanowires 1104 is less than approximately 20 nanometers. In embodiments, the nanowires 1104 are made of a strained material, particularly the strained material in the channel region 1106.

[0164] refer to Figure 11C In this embodiment, each channel region 1106 has a width (Wc) and a height (Hc), which are approximately the same. That is, in both cases, the cross-sectional profile of the channel region 1106 is square, or if it is rounded, the cross-sectional profile of the channel region 1106 is circular. In another aspect, for example, as described throughout for nanoribbons, the width and height of the channel regions do not need to be the same.

[0165] In embodiments, as described throughout, the integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device having one or more corresponding overlying nanowire structures. In such embodiments, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body, wherein one or more discrete nanowire channel portions are overlying the three-dimensional body. In one such embodiment, the gate structure surrounds at least the top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0166] In an embodiment, Figures 11A-11C The structure can be formed using pixel structure notching methods as described above.

[0167] In embodiments, as described throughout, the underlying substrate may be made of a semiconductor material capable of withstanding fabrication processes and in which charge can migrate. In embodiments, the substrate is a bulk substrate comprising a layer of crystalline silicon, silicon / germanium, or germanium doped with charge carriers to form active regions, such charge carriers being, for example, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate comprises an epitaxial layer grown on top of a different crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single-crystal substrate. The bulk substrate may alternatively be made of a Group III-V material. In embodiments, the bulk substrate is made of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is made of a group III-V material, and the charge carrier dopant impurity atoms are, for example, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0168] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. Integrated circuits can be coupled to buses and other components in a system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0169] Figure 12 A computing device 1200 according to one embodiment of the present disclosure is shown. The computing device 1200 houses a board 1202. The board 1202 may include multiple components, including but not limited to a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some embodiments, at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In a further embodiment, the communication chip 1206 is part of the processor 1204.

[0170] Depending on the application of computing device 1200, computing device 1200 may include other components that may or may not be physically coupled and electrically coupled to board 1202. These other components include, but are not limited to: volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (e.g., hard disk drive, optical disc (CD), digital versatile optical disc (DVD), etc.).

[0171] Communication chip 1206 enables wireless communication for transmitting data to and from computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain wires. Communication chip 1206 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocol designated as 3G, 4G, 5G, and higher. Computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 1206 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0172] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures constructed according to embodiments of the present disclosure, such as a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact cutouts. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0173] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures constructed according to embodiments of the present disclosure, such as a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact cutouts.

[0174] In a further embodiment, another component housed within the computing device 1200 may contain an integrated circuit die comprising one or more structures constructed according to embodiments of the present disclosure, such as a full-around-gate integrated circuit structure having a uniform grid metal gate and trench contact cutouts.

[0175] In various embodiments, the computing device 1200 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, the computing device 1200 may be any other electronic device that processes data.

[0176] Figure 13 An interposer 1300, comprising one or more embodiments of the present disclosure, is illustrated. The interposer 1300 is an intermediary substrate for bridging a first substrate 1302 to a second substrate 1304. For example, the first substrate 1302 may be an integrated circuit die. The second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1300 is to extend connections to a wider pitch or to rewire connections to different connections. For example, the interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which may then be coupled to the second substrate 1304. In some embodiments, the first substrate 1302 and the second substrate 1304 are attached to opposite sides of the interposer 1300. In other embodiments, the first substrate 1302 and the second substrate 1304 are attached to the same side of the interposer 1300. And in a further embodiment, three or more substrates are interconnected through the interposer 1300.

[0177] Intermediate layer 1300 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (e.g., polyimide). In other embodiments, intermediate layer 1300 may be formed of alternative rigid or flexible material, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials.

[0178] Interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. Interposer 1300 may also include embedded devices 1314, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1300. According to embodiments of this disclosure, the devices or processes disclosed herein may be used in the fabrication of interposer 1300 or in the fabrication of components included in interposer 1300.

[0179] Therefore, embodiments of this disclosure include an integrated circuit structure having a uniform grid metal gate and trench contact cuts, and a method for fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts.

[0180] The above description of the embodiments shown in this disclosure (including the description in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Although specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art.

[0181] These modifications may be made to this disclosure in light of the foregoing detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope of this disclosure is determined entirely by the appended claims, which shall be interpreted in accordance with established principles of claim interpretation.

[0182] Exemplary Example 1: An integrated circuit structure includes: a vertical stack of horizontal nanowires having a pyramidal profile with pyramidal angles. A gate electrode is located on the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A dielectric notch plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric notch plug structure has a concave profile with notch angles laterally spaced from the pyramidal angles of the pyramidal profile of the vertical stack of horizontal nanowires.

[0183] Exemplary Example 2: An integrated circuit structure according to Exemplary Example 1, wherein the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires is greater than the cut angle of the concave profile of the dielectric cut plug structure.

[0184] Exemplary Example 3: An integrated circuit structure according to Exemplary Example 1, wherein the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires is the same as the cut angle of the concave profile of the dielectric cut plug structure.

[0185] Exemplary Example 4: An integrated circuit structure according to Exemplary Example 1, wherein the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires is smaller than the cut angle of the concave profile of the dielectric cut plug structure.

[0186] Exemplary Example 5: The integrated circuit structure according to Exemplary Example 1, 2, 3 or 4 further includes a second dielectric notch plug structure, which extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion. The second dielectric notch plug structure is laterally spaced from and parallel to the first dielectric notch plug structure.

[0187] Exemplary Example 6: The integrated circuit structure according to Exemplary Example 1, 2, 3, 4 or 5 further includes an epitaxial source or drain structure located at the end of the vertical stack of horizontal nanowires and below the conductive trench contact.

[0188] Exemplary Example 7: The integrated circuit structure according to Exemplary Example 1, 2, 3, 4, 5 or 6 further includes a second gate electrode, which is adjacent to a conductive trench contact on a side opposite to the gate electrode, wherein a dielectric cut-out plug structure extends through the second gate electrode.

[0189] Exemplary Example 8: The integrated circuit structure according to Exemplary Example 1, 2, 3, 4, 5 or 6 further includes a second conductive trench contact portion, which is adjacent to the gate electrode on the side opposite to the conductive trench contact portion, wherein the dielectric cut-out plug structure extends through the second conductive trench contact portion.

[0190] Exemplary Example 9: The integrated circuit structure according to Exemplary Example 8 further includes a second gate electrode, which is adjacent to a second conductive trench contact on a side opposite to the gate electrode, wherein a dielectric cut-out plug structure extends through the second gate electrode.

[0191] Exemplary Example 10: An integrated circuit structure includes a fin having a pyramidal profile with pyramidal angles. A gate electrode is located on the fin. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A dielectric cut-out plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut-out plug structure has a concave profile with cut-out angles laterally spaced from the pyramidal angles of the fin's pyramidal profile.

[0192] Exemplary Example 11: An integrated circuit structure according to Exemplary Example 10, wherein the pyramid angle of the pyramidal profile of the fin is greater than the cut angle of the concave profile of the dielectric cut-out plug structure.

[0193] Exemplary Example 12: An integrated circuit structure according to Exemplary Example 10, wherein the pyramid angle of the pyramidal profile of the fin is the same as the cut angle of the concave profile of the dielectric cut-out plug structure.

[0194] Exemplary Example 13: An integrated circuit structure according to Exemplary Example 10, wherein the pyramid angle of the pyramidal profile of the fin is smaller than the cut angle of the concave profile of the dielectric cut plug structure.

[0195] Exemplary Example 14: The integrated circuit structure according to Exemplary Example 10, 11, 12 or 13 further includes a second dielectric notch plug structure, which extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact portion. The second dielectric notch plug structure is laterally spaced from and parallel to the first dielectric notch plug structure.

[0196] Exemplary Example 15: The integrated circuit structure according to Exemplary Example 10, 11, 12, 13 or 14 further includes an epitaxial source or drain structure located at the end of the fin and below the conductive trench contact portion.

[0197] Exemplary Example 16: The integrated circuit structure according to Exemplary Example 10, 11, 12, 13, 14 or 15 further includes a second gate electrode, which is adjacent to a conductive trench contact on a side opposite to the gate electrode, wherein a dielectric cut-out plug structure extends through the second gate electrode.

[0198] Exemplary Example 17: The integrated circuit structure according to Exemplary Example 10, 11, 12, 13, 14 or 15 further includes a second conductive trench contact portion, which is adjacent to the gate electrode on the side opposite to the conductive trench contact portion, wherein the dielectric cut-out plug structure extends through the second conductive trench contact portion.

[0199] Exemplary Example 18: The integrated circuit structure according to Exemplary Example 17 further includes a second gate electrode, which is adjacent to a second conductive trench contact on a side opposite to the gate electrode, wherein a dielectric cut-out plug structure extends through the second gate electrode.

[0200] Exemplary Example 19: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure comprising a vertical stack or fin of horizontal nanowires having a pyramidal profile with pyramidal angles. A gate electrode is located on the vertical stack or fin of the horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A dielectric slit plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric slit plug structure has a concave profile having slit angles laterally spaced from the pyramidal angles of the pyramidal profile of the vertical stack or fin of the horizontal nanowires.

[0201] Exemplary Example 20: A computing device according to Exemplary Example 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: A first nanowire stack having nanowires that gradually widen from top to bottom along a first central axis; The second nanowire stack is laterally spaced from the first nanowire stack, and the second nanowire stack has nanowires that gradually widen from top to bottom along a second central axis. A first gate stack is located on and around the first nanowire stack. A second gate stack is located on top of and around the second nanowire stack. as well as A dielectric plug is laterally located between the first gate stack and the second gate stack, extending from above and below the first and second gate stacks, the dielectric plug contacting the gates of the first and second gate stacks, and the dielectric plug having a concave profile.

2. The integrated circuit structure according to claim 1, wherein, The dielectric plug is a first dielectric plug, and the integrated circuit structure further includes: The second dielectric plug is laterally spaced from the first dielectric plug, wherein the first nanowire stack is laterally located between the second dielectric plug and the first dielectric plug.

3. The integrated circuit structure according to claim 2, wherein, The second dielectric plug contacts the gate of the first gate stack.

4. The integrated circuit structure according to claim 2, wherein, There are no additional nanowire stacks laterally between the first nanowire stack and the first dielectric plug, and there are no additional nanowire stacks laterally between the first nanowire stack and the second dielectric plug.

5. The integrated circuit structure according to claim 2, further comprising: A third dielectric plug is laterally spaced from the first dielectric plug, wherein the second nanowire stack is laterally located between the third dielectric plug and the first dielectric plug.

6. The integrated circuit structure according to claim 5, wherein, The third dielectric plug contacts the gate of the second gate stack.

7. The integrated circuit structure according to claim 5, wherein, There are no additional nanowire stacks laterally between the second nanowire stack and the first dielectric plug, and there are no additional nanowire stacks laterally between the second nanowire stack and the third dielectric plug.

8. An integrated circuit structure, comprising: A first nanowire stack having a first pyramidal profile; The second nanowire stack is laterally spaced from the first nanowire stack, and the second nanowire stack has a second pyramidal profile. A first gate stack is located on and around the first nanowire stack. A second gate stack is located on top of and around the second nanowire stack. as well as A dielectric structure is laterally located between a first gate stack and a second gate stack, extending from above the gates of the first gate stack and the second gate stack to below the gates of the first gate stack and the second gate stack, the dielectric structure being in contact with the gates of the first gate stack and the second gate stack, and the width of the dielectric structure at the top of the dielectric structure being greater than the width of the dielectric structure at the bottom of the dielectric structure.

9. The integrated circuit structure according to claim 8, wherein, The dielectric structure is a first dielectric structure, and the integrated circuit structure further includes: A second dielectric structure is laterally spaced from the first dielectric structure, wherein the first nanowire stack is laterally located between the second dielectric structure and the first dielectric structure.

10. The integrated circuit structure according to claim 9, wherein, The second dielectric structure is in contact with the gate of the first gate stack.

11. The integrated circuit structure according to claim 9, further comprising: A third dielectric structure is laterally spaced from the first dielectric structure, wherein the second nanowire stack is laterally located between the third dielectric structure and the first dielectric structure.

12. The integrated circuit structure according to claim 11, wherein, The third dielectric structure is in contact with the gate of the second gate stack.

13. The integrated circuit structure according to claim 11, wherein, There are no additional nanowire stacks laterally between the first nanowire stack and the first dielectric structure, and there are no additional nanowire stacks laterally between the first nanowire stack and the second dielectric structure, and there are no additional nanowire stacks laterally between the second nanowire stack and the first dielectric structure, and there are no additional nanowire stacks laterally between the second nanowire stack and the third dielectric structure.

14. A method for manufacturing an integrated circuit structure, the method comprising: A first nanowire stack is formed having nanowires that gradually widen from top to bottom along a first central axis; A second nanowire stack is formed that is laterally spaced from the first nanowire stack, the second nanowire stack having nanowires that gradually widen from top to bottom along a second central axis; A first gate stack is formed on and around the first nanowire stack. A second gate stack is formed on and around the second nanowire stack; as well as A dielectric plug is formed, the dielectric plug being laterally located between the first gate stack and the second gate stack, and the dielectric plug extending from above the first gate stack and the second gate stack to below the first gate stack and the second gate stack, the dielectric plug contacting the gate of the first gate stack and the gate of the second gate stack, and the dielectric plug having a concave profile.

15. The method according to claim 14, wherein, The dielectric plug is a first dielectric plug, and the method further includes: A second dielectric plug is formed that is laterally spaced from the first dielectric plug, wherein the first nanowire stack is laterally located between the second dielectric plug and the first dielectric plug.

16. The method according to claim 15, wherein, The second dielectric plug contacts the gate of the first gate stack.

17. The method according to claim 15, wherein, There are no additional nanowire stacks laterally between the first nanowire stack and the first dielectric plug, and there are no additional nanowire stacks laterally between the first nanowire stack and the second dielectric plug.

18. The method of claim 15, further comprising: A third dielectric plug is laterally spaced from the first dielectric plug, wherein the second nanowire stack is laterally located between the third dielectric plug and the first dielectric plug.

19. The method according to claim 18, wherein, The third dielectric plug contacts the gate of the second gate stack.

20. The method according to claim 18, wherein, There are no additional nanowire stacks laterally between the second nanowire stack and the first dielectric plug, and there are no additional nanowire stacks laterally between the second nanowire stack and the third dielectric plug.

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