Vertical field effect transistor and method for constructing a vertical field effect transistor

Abstract

A vertical field effect transistor (200) is provided having a drift region (206), a semiconductor fin (208) above or over the drift region (206), and a source / drain electrode (218) above or over the semiconductor fin (208), wherein the semiconductor fin (208) has at least one concavely shaped sidewall in a region between the drift region (206) and the source / drain electrode (218).

Description

Technical Field

[0001] The present invention relates to a vertical field-effect transistor and a method for constructing a vertical field-effect transistor. Background Technology

[0002] In the automotive sector, the continued development toward electric vehicles demands solutions for power semiconductors that can switch quickly and without loss. Here, the simultaneous trend from lateral to vertical components, and the shift from decades-old silicon technology toward so-called “wide bandgap” materials (i.e., semiconductor materials with wide band spacing), such as silicon carbide (SiC) or gallium nitride (GaN), has led to the development of new component concepts and manufacturing processes.

[0003] As the integration density of semiconductor structures increases, in vertical designs, the entire back surface of the component can be used. In some concepts utilizing band bending, such as "FinFETs" (Fin Field-Effect Transistors), the small contact area of ​​the semiconductor fins (Halbleiter-Finnen) for sufficiently low impedance contacts in power semiconductors becomes a problem due to established process sequences. The functional principle of FinFETs requires very thin, independent structures where current is conducted vertically (semiconductor fins). Therefore, semiconductor fins do not have a large area for front-side contacts. High integration density in vertical semiconductor components can result in extremely small front-side source contact areas. Figure 1A-1C A schematic diagram of the semiconductor fins of a conventional FinFET is shown. Figure 1A Showing the cross-sectional profile, Figure 1B A perspective view is shown, and Figure 1C An idealized view of the semiconductor fins of a FinFET is shown. In this case, frontal contacts, such as n+-doped connection regions 106 for source contacts, are constructed on the semiconductor fins 104 over the drift region 102. The semiconductor fins have a narrow shape that is rounded at the ends. A portion of the connection regions 106 is removed during fabrication, resulting in rounded, needle-like structures that extend laterally into the plane and must contact the source electrode at their apical upper sides.

[0004] Figure 1A The cross-section is shown relative to the initial grid (drawn as dashed lines; see [link]). Figure 1C Compared to the shape after the fin structure is formed. The removed n+ type doped connection region 106 can be retained by the implantation depth. However, the reliable contact area (in Figure 1B The loss (represented by three-dimensional depth) represents the undesirable drawback. Summary of the Invention

[0005] The objective of this invention is to provide a vertical field-effect transistor and a method for constructing it, which enables a vertical field-effect transistor with improved front contact.

[0006] According to one aspect of the invention, this task is solved by a vertical field-effect transistor (VFET). The VFET has: a drift region, a semiconductor fin on or above the drift region, and source / drain electrodes on or above the semiconductor fin, wherein the semiconductor fin has at least one concave sidewall in the region between the drift region and the source / drain electrodes. The concave sidewall of the semiconductor fin allows for a larger contact area on the semiconductor fin. This allows for a smaller contact resistance, for example, at the source contact portion on the semiconductor fin.

[0007] According to another aspect of the invention, this task is accomplished by a method for constructing a vertical field-effect transistor. The method comprises: constructing a drift region; constructing a semiconductor fin on or above the drift region; and constructing source / drain electrodes on or above the semiconductor fin, wherein the semiconductor fin has at least one concavely shaped sidewall constructed in the region between the drift region and the source / drain electrodes. Attached Figure Description

[0008] Extensions to these aspects are set forth in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and explained in more detail below. The drawings show: Figure 1A -C shows a schematic diagram of a conventional semiconductor fin; Figure 2 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown; Figure 3-14 Schematic diagrams are shown of method steps for manufacturing a vertical field-effect transistor according to different embodiments; and Figure 15 A flowchart illustrating a method for constructing a vertical field-effect transistor according to different implementations is shown. Detailed Implementation

[0009] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, and in which specific embodiments are shown for visual illustration, in which the invention can be applied. It is self-evident that other embodiments can be used and structural or logical changes can be made without departing from the scope of the invention. It is self-evident that features of the different embodiments described herein can be combined with each other, unless specifically otherwise indicated. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined by the supplementary claims. In the drawings, the same or similar elements are given the same reference numerals, provided that this is for the purpose.

[0010] Figure 2 A schematic cross-sectional view of a vertical field-effect transistor 200 according to different embodiments is shown. In different embodiments, the vertical field-effect transistor 200 has a drift region 206 on a semiconductor substrate 204, a semiconductor fin 208 with a connection region 210 on or above the drift region 206 (the longitudinal direction of the semiconductor fin extends perpendicular to the plane of the drawing), a first source / drain electrode (e.g., source electrode 218), and a second source / drain electrode (e.g., drain electrode 202). Hereinafter, it is exemplarily assumed that the first source / drain electrode 218 is the source electrode, and the second source / drain electrode 202 is the drain electrode. Furthermore, the vertical field-effect transistor 200 has a gate electrode 214 laterally adjacent to at least one sidewall of the semiconductor fin 208, wherein the gate electrode 214 is electrically insulated from the source electrode 218 by means of an insulator 216. A gate dielectric 212 is disposed between the gate electrode 214 and at least one sidewall of the semiconductor fin 208.

[0011] The semiconductor fin 208 has at least one concavely shaped sidewall in the region between the drift region 206 and the source / drain electrode 218. Figure 2 The text does not explain this intuitively; see [link / reference]. Figure 14 The semiconductor fin 208 may have a first sidewall and a second sidewall opposite to the first sidewall. The first and second sidewalls may be concave. Furthermore, the gate electrode 214 may be constructed adjacent to at least one concave sidewall of the semiconductor fin 208. The concave sidewalls are thus constructed such that the semiconductor fin 208 has a smaller lateral extension in the first section laterally arranged adjacent to the gate electrode 214 than in the second section contacting the drift region 206 and / or than in the third section contacting the source electrode 218. This allows for a significant increase in the contact area for carrying current on the front side of the substrate. Consequently, a significantly lower and more reliable ohmic contact region can be fabricated for vertical field-effect transistors.

[0012] Figure 2 A schematic cross-sectional view of a single FinFET cell according to different implementations is shown. Generally, hundreds to thousands of such cells are connected in parallel, and the structure extends into a plane in the third dimension. The combination of multiple cells creates a two-dimensionally extended field region of the FinFET cell. The vertical field-effect transistor can be a power semiconductor structure element. As an example, the semiconductor substrate 204 can be a GaN substrate 204 or a SiC substrate 204. A weakly n-type conductive semiconductor drift region 206, such as a GaN drift region 206 or a SiC drift region 206, can be formed (e.g., applied) on the semiconductor substrate 204. An n-type conductive semiconductor region in the form of a semiconductor fin 208, such as a GaN fin or a SiC fin 208, can be formed above the drift region 206.

[0013] For the vertical field-effect transistor 200 to function as a transistor or a switch, the semiconductor fin 208 has, for example, a lateral extension in the plane of the figures shown in the figure within the range of about 100 nm to about 200 nm and a vertical extension in the plane of the figures shown in the figure within the range of about 1 μm to about 3 μm.

[0014] By applying a positive voltage to the gate electrode 214, the complete electron gas can be filled with electrons and electrons can flow from the source electrode 218 through the semiconductor fin 208 to the bottom of the semiconductor fin 208 and from there through the drift region 206 and through the substrate 204 to the drain electrode 202.

[0015] Semiconductor fins 208 can be constructed, for example, within a predetermined, e.g., smallest possible, grid using trench structures (also called deep trenches) on the left and right sides of the semiconductor fin. In various embodiments, the method involves constructing the trench structures, for example, using a dry etching process, to construct semiconductor fins of a first width. Furthermore, the method may involve oxidizing and removing the semiconductor oxide formed by the oxidation to construct semiconductor fins of a second width smaller than the first width. This reduces the lateral structural extension of the semiconductor fins 208. The oxidation and removal of the newly formed oxide can be performed periodically and sequentially multiple times.

[0016] Figure 3 The drift region 206 on substrate 204 and the n+-type doped connection region 210 constructed in the drift region 206 by (ion) implantation are visually illustrated. Subsequently, in Figure 3 A layer stack having a first inorganic layer 402 (e.g., silicon nitride layer 402) and a second inorganic layer 404 (e.g., silicon oxide layer 404) can be deposited on the layer stack shown, as in Figure 4As intuitively illustrated in the diagram. The desired structuring depth of the view drift region 206 or the vertical extension of the semiconductor fin 208 (see...) Figure 5 The layer thicknesses for the first inorganic layer and the second inorganic layers 402, 404 are selected based on the expected oxidation time during the "fin formation process" ("fin forming"). The first inorganic layer 402 is configured as an etch stop layer for subsequent processes.

[0017] In the example of SiC as the semiconductor material for drift region 206, the silicon nitride layer 402 has a thickness ranging from approximately 100 nm to approximately 1 μm, and the silicon oxide layer 404 has a thickness ranging from approximately 800 nm to approximately 1500 nm. The combination of layer thicknesses consisting of silicon nitride and silicon oxide can be chosen such that the silicon oxide in the silicon oxide layer 404 is completely consumed during the structuring process of drift region 206. Alternatively, it is possible to completely omit the second inorganic layer 404 made of silicon oxide, since the silicon nitride layer 402 alone is sufficient for the development of the process flow. The layer stack having the first inorganic layer and the second inorganic layers 402, 404 can be used as a mask during the structuring of the semiconductor material for drift region 206 and can be produced accordingly prior to structuring by means of suitable photolithography and structuring processes. Photoresist 406 for exposure and development is disposed on the second inorganic layer 404. The photoresist 406 has openings, and then trench structures of adjacent semiconductor fins are formed below the openings.

[0018] Figure 5 The structuring 208 / 502 of the drift region 206, accomplished using silicon oxide-silicon nitride masks 404 / 402 (hereinafter referred to as oxide-nitride masks), is visually illustrated. Here, the photoresist 406 is consumed or its remainder is removed after structuring with the oxide-nitride masks 404 / 402. The thickness of the silicon oxide layer 404 is partially reduced during trench structure 502 formation. The remainder of the silicon oxide layer 404 on the silicon nitride layer 402 can be retained. The remainder of the silicon oxide layer 404 can then be removed by wet chemical removal, wherein the silicon nitride layer 402 acts as an etch stop mask. Subsequently, the lateral extension of the semiconductor fin 208 (in the plane of the illustrated figures) can be reduced by one or more periodically repeated processes, such as in... Figure 6 As illustrated intuitively in the text.

[0019] Figure 6 It is divided into 4 regions ("A", "B", "C" and "SdT"). Region A shows the initial state before fin formation ( Figure 5Regions B and C illustrate the state following different advancements in the reduction of the lateral extension of the semiconductor fin, with C being more technologically advanced than B. The semiconductor fin 208, visually illustrated in regions B and C, can be constructed by removing semiconductor material from the sidewalls (region A) of the semiconductor fin 208 in one step (region B) or multiple steps (region C). This allows for the construction of at least one concave sidewall of the semiconductor fin 208. The dashed lines in regions B and C, and in region SdT, schematically illustrate the outline of the semiconductor fin before its lateral thinning (as in region A). Figure 6 The rightmost semiconductor fin (region SdT) shown is a conventional semiconductor fin for comparison. The lateral extension of semiconductor fin 208 (in...) Figure 6 In the process, the thickness from region A to region B or region C can be reduced to a predetermined thickness by means of oxidation of the semiconductor material of the semiconductor fin and removal of the formed semiconductor oxide. For example, the lateral extension can be reduced from approximately 500 nm to an adjustable value in the range of 100 nm to approximately 200 nm. By means of the lateral extension of semiconductor fin 208, the threshold voltage of vertical field-effect transistor 200 can be adjusted to a predetermined value that varies depending on the application.

[0020] exist Figure 6 Region A in the diagram illustrates, for example, a structured trench 502 of drift region 206 prior to the first oxidation and / or etching, and a fin 208 with n+ type doped connection region 210 and a first inorganic layer 402, which is subsequently used as an etch stop mask. The re-oxidized silicon nitride (silicon oxynitride) can also be removed in an etch medium containing hydrofluoric acid. Therefore, during the oxidation of semiconductor materials, especially in the case of silicon carbide, the optimal state of mask consumption and semiconductor material oxidation is selected in terms of the oxidation behavior of the semiconductor material and the material of the etch stop mask. Thus, the layer thickness of the first inorganic layer 402 can be optimally adjusted according to the number of cycles and oxidation parameters (temperature, time, wet oxidation, or dry oxidation). For the oxidation of the semiconductor material of the semiconductor fins, commercially available oxidation furnaces commonly used in the semiconductor industry can be used.

[0021] exist Figure 6 Region B shows the shape change after the continued process compared to the initial shape (delineated in dashed lines). The already concave sidewalls of the semiconductor fin 208 and the reduced lateral extension of the n+ type doped connection region 210 and the first inorganic layer 402, resulting from oxidation and oxide removal, can be seen.

[0022] exist Figure 6In region C, the fin forming process ends. The material of the first inorganic layer 402 (e.g., a silicon nitride layer) is almost completely or completely depleted. However, the first inorganic layer 402 protects the semiconductor material near the connection region 210, and in particular protects the n+ type doped connection region 210 from oxidation and oxide removal. Therefore, the semiconductor fin 208 has a columnar structure in shape (with a column head or columnar protrusion or concave sidewalls). The connection region 210 constructed in this way differs from conventional needle-shaped semiconductor fins without the first inorganic layer 402 (in... Figure 6 (This is visually illustrated in the region SdT) compared to a source electrode that has a significantly more extended lateral and larger contact area for subsequent deposition.

[0023] In subsequent process steps, any remaining portion of the first inorganic layer 402 can be completely removed, as in... Figure 7 As visually illustrated in the diagram. This can be performed in a selective dry etching process or a wet etching process (not shown). Additional steps for constructing vertical field-effect transistors can be substantially the same as conventional steps.

[0024] For example, gate dielectric 810 (e.g., gate oxide) can be formed by oxidation or shape-locked deposition on a previously exposed surface. Gate dielectric 810 can cover not only channel region 812 but also all other surfaces, such as... Figure 8 The text is a direct and intuitive explanation.

[0025] exist Figure 9 The image shows a cross-sectional view of the formation progressing over time from region I to region II to region III after the subsequent deposition of polysilicon 902 to construct the gate electrode. In the case of in-situ doped chemical vapor deposition (LPCVD deposition) under low pressure, the gate polysilicon 902 can also be deposited in a largely homogeneous and shape-locked manner on the trench structure. Figure 5 The polysilicon 902 is deposited on the gate dielectric 810 in region A (502) or in the cavity 904 (also called the “bulging barrel region”) between adjacent semiconductor fins 208. Due to the very good “gap universality” of polysilicon, starting from region A, the inlet opening 904 closes in region B (906) as deposition progresses, so that in region C, with the closure of the inlet 908, further deposition of polysilicon in the barrel region 904 from the surface is not possible. Further deposition results in the complete closure of the opening 910 and results in the desired thickening and planarization of the surface of the deposited polysilicon 902. After the polysilicon deposition is completed, the profile of the polysilicon 902 above all the “barrels” 904 is as follows: Figure 10 This is explained intuitively.

[0026] In different implementations, the cavity 904 (barrel) surrounded by two adjacent semiconductor fins 208 can be used as a cooling structure or configured, for example, as a so-called "heat pipe", for example, for pressure-type self-convection or forced external convection.

[0027] The gate polysilicon layer 1002 can be homogeneously constructed over the entire gate dielectric region 810 and form a flat or planarized homogeneous layer on the exposed surface.

[0028] In the subsequent process (the result of which is) Figure 11 In the intuitive illustration, the gate polysilicon 1002 can be removed, for example, in a dry structuring step, in the region where the source contact should be constructed. Barrel region 904 (see...) Figure 9 ) and channel area 812 or in channel area 812 (see Figure 8 The gate dielectric on top can remain completely covered by the remaining polysilicon 1102. For example, protruding areas of the exposed polysilicon layer 1002 can also be preserved in previous photolithography steps (not shown visually).

[0029] In the subsequent process (the result of which is) Figure 12 In the illustration, the surface of the structured polysilicon layer 1102 can be thinly oxidized, for example, by thermal oxidation. The resulting oxide layer 1202 can be sufficiently thin, ranging from approximately 50 nm to approximately 150 nm. The surface of the structured polysilicon layer 1102 before oxidation is shown by the dashed line 1204 (see [link to illustration]). Figure 11 Alternatively, due to oxidation and its increased volume, the newly generated openings can also be closed here by structuring the polycrystalline silicon 1002 (see...). Figure 11 The opening on the right side of the middle is 1104 to Figure 12 (Opening 1206 in the middle).

[0030] In the subsequent process (the result of which is) Figure 13 (As illustrated in the diagram), the semiconductor oxide layer 1300 to be covered can be deposited flatly, for example by means of LPCVD deposition. Figure 13 The deposited semiconductor oxide layer 1300 and the photoresist layer 1302 are shown, the photoresist layer forming the corresponding source contacts by means of photolithography (see...). Figure 14 ) Prepared for use in semiconductor oxide layer 1300 structured 1304.

[0031] Figure 14 The structured semiconductor oxide layer 1406 is shown, with a contact region 1402 opening towards the n+ type connection region 210. Furthermore, Figure 14The deposited contact metal portion is shown, which forms an ohmic contact (source electrode 218) with a corresponding n+ type connection region 210 in the region of the opened semiconductor oxide layer 1404. The contact metal portion, or alternatively, may also have a suitable semiconductor material that has a significantly larger surface contact than conventional rounded semiconductor fins, thus creating a much larger extended source contact area.

[0032] Alternatively, for the concave sidewalls of semiconductor fins, which can be constructed using oxidation, isotropic dry or wet etching processes can be used in the same manner. For example, in semiconductor materials where thermal oxides cannot be constructed, such as gallium nitride (GaN), gallium oxide (GaOx), aluminum nitride (AlN), and diamond, isotropic etching processes can provide the possibility of achieving the in-situ construction of semiconductor fins. Figure 7 The shape shown is analogous to that of thermal oxidation. The masking of the semiconductor fins can be chosen such that it has resistance to subsequent isotropic etching. With suitable isotropic etching, the achievable profile of the semiconductor fins has a shape comparable to that produced by oxidation. For gallium nitride, gallium oxide, and aluminum nitride, dry etching, for example, in a chlorine-containing plasma can be used. For diamond, comparable etching in an oxygen-containing plasma can be used. Wet chemical etching processes for gallium nitride are possible, for example, in potassium hydroxide (KOH) or methylammonium hydroxide (TMAH) at varying concentrations and temperatures. Nitrogen compounds and / or oxygen compounds can be used as masking materials.

[0033] Figure 15 A flowchart of a method 1500 for constructing a vertical field-effect transistor (VFET) according to different embodiments is shown. Method 1500 includes: constructing a drift region 1510; constructing a semiconductor fin on or above the drift region; and constructing source / drain electrodes 1530 on or above the semiconductor fin, wherein the semiconductor fin has at least one concavely shaped sidewall in the region between the drift region and the source / drain electrodes. This achieves safe and reliable process control during the frontal contact of the VFET. Furthermore, a flat surface for subsequent processes can be achieved using this method. A thinner layer thickness can be achieved using a flat surface. This enables a deposition process that is shorter in time and more economical. In the correspondingly selected process control, embedded cooling channels between adjacent semiconductor fins for self-convection or external convection can be used for cooling. To manufacture a VFET, more cost-effective facilities can be utilized compared to other designs in terms of investment and operating costs.

[0034] At least one concave sidewall of a semiconductor fin can be constructed using an etch stop mask, wherein the etch stop mask is constructed on or above the semiconductor fin. The etch stop mask may have a nitride compound. At least one concave sidewall of a semiconductor fin can be constructed by oxidizing the semiconductor material of the semiconductor fin and removing the formed oxide semiconductor material. Constructing at least one concave sidewall of a semiconductor fin may involve repeatedly oxidizing the semiconductor material of the semiconductor fin and then removing the formed oxide semiconductor material. Alternatively, at least one concave sidewall of a semiconductor fin can be constructed by isotropic etching of the semiconductor material of the semiconductor fin.

[0035] The highly doped connection region can electrically connect the semiconductor fin to the source electrode. The source electrode can be additionally constructed laterally next to at least one sidewall of the semiconductor fin above or above the drift region.

[0036] The described and illustrated embodiments are merely examples. Different embodiments may be implemented entirely or in combination with respect to individual features. One embodiment may also be complemented by features of another. Furthermore, the described method steps may be performed repeatedly and in a different order than that described. In particular, the invention is not limited to the indicated methods.

Claims

1. A vertical field-effect transistor, having: Drift area; Semiconductor fins above or above the drift region, and The source / drain electrodes are located on or above the semiconductor fin. The semiconductor fin has at least one concave sidewall in the region between the drift region and the source / drain electrodes. A gate electrode, which is laterally configured adjacent to at least one sidewall of the semiconductor fin. The at least one concave sidewall is constructed such that the semiconductor fin has a smaller lateral extension in a first section laterally arranged next to the gate electrode than in a second section contacting the drift region and / or than in a third region contacting the source / drain electrodes. in, The at least one concave sidewall faces the gate electrode laterally and defines a reduced lateral width of the semiconductor fin in a central region located between the upper and lower regions of the semiconductor fin, such that the semiconductor fin is narrower in the central region than in the upper region adjacent to the source / drain electrode and in the lower region adjacent to the drift region.

2. The vertical field-effect transistor according to claim 1, in, The drift region and the semiconductor fin are formed of silicon carbide or gallium nitride.

3. The vertical field-effect transistor according to claim 1, in, The semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall, and the first sidewall and the second sidewall are concavely constructed.

4. The vertical field-effect transistor according to claim 1, wherein, The at least one concave sidewall is defined by a reduced lateral width at the central region relative to the upper and lower regions of the semiconductor fin. The reduced lateral width is constructed by oxidation and removal of the semiconductor material at the sidewall of the fin, and the upper region of the semiconductor fin is protected from oxidation by an etch stop mask constructed on or above the semiconductor fin.

5. A method for constructing a vertical field-effect transistor, the method comprising: Construct drift regions; Semiconductor fins are constructed on or above the drift region. Source / drain electrodes are constructed on or above the semiconductor fin. The semiconductor fin has at least one concave sidewall constructed in the region between the drift region and the source / drain electrodes. in, A gate electrode is constructed laterally adjacent to at least one sidewall of the semiconductor fin, the at least one concave sidewall being constructed such that the semiconductor fin has a smaller lateral extension in a first segment laterally disposed adjacent to the gate electrode than in a second segment contacting the drift region and / or than in a third region contacting the source / drain electrode. The at least one concave sidewall faces the gate electrode laterally and defines a reduced lateral width of the semiconductor fin in a central region located between the upper and lower regions of the semiconductor fin, such that the semiconductor fin is narrower in the central region than in the upper region adjacent to the source / drain electrode and in the lower region adjacent to the drift region.

6. The method according to claim 5, wherein, At least one concave sidewall of the semiconductor fin is constructed by using an etch stop mask, which is constructed on or above the semiconductor fin.

7. The method according to claim 6, wherein, The etching stop mask contains nitrogen compounds.

8. The method according to claim 5, wherein, At least one concave sidewall of the semiconductor fin is constructed by means of oxidation of the semiconductor material of the semiconductor fin and removal of the resulting oxide semiconductor material.

9. The method according to claim 8, wherein, The construction of at least one concave sidewall of the semiconductor fin involves a repeated process of oxidation of the semiconductor material of the semiconductor fin and subsequent removal of the resulting oxide semiconductor material.

10. The method according to claim 5, wherein, The concave sidewalls of the semiconductor fin are formed by isotropic etching of the semiconductor material of the semiconductor fin.

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