Semiconductor device and method of manufacturing the same, semiconductor package structure, electronic device

Abstract

The embodiment of the present application provides a semiconductor device and a preparation method thereof, a semiconductor packaging structure and an electronic device. The device comprises a substrate and a vertical channel transistor, the vertical channel transistor is arranged on the substrate, and the vertical channel transistor comprises a source, a drain, a gate and a channel layer. The gate comprises at least a first work function metal layer and a second work function metal layer. The channel layer extends in a direction perpendicular to the substrate, and the source and the drain are arranged at two ends of the channel layer in the extending direction. In a direction parallel to the substrate, the first work function metal layer is arranged around the channel layer, the second work function metal layer is arranged around the channel layer, and the absolute value of the work function difference between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold value. The embodiment of the present application can reduce the source or drain leakage current of the transistor during operation and improve the performance of the transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a semiconductor packaging structure, and an electronic device. Background Technology

[0002] With the development of technology, Vertical Transport Field Effect Transistors (VTFETs) define the critical dimensions of transistors in the vertical direction, decoupling the limitations of contact gate spacing on transistor size, thereby significantly reducing the parasitic capacitance of transistors, and thus improving chip performance and reducing chip power consumption.

[0003] However, in vertical transmission field-effect transistors (VT-IN), due to the tunneling mechanism, when a voltage difference (electric field) exists between the gate and drain of the transistor—for example, when a high voltage is applied to the drain during transistor operation—tunneling occurs, causing gate-induced drain leakage current (GIDL). Similarly, when a voltage difference exists between the gate and source—for example, when a high voltage is applied to the source during transistor operation—tunneling also occurs, causing gate-induced source leakage current (GISL). Since it is unavoidable to apply voltage to the source and / or drain (excluding the gate) during operation, leakage current at the source or drain terminals is unavoidable. This leakage current has a significant impact on transistor performance and power consumption.

[0004] Therefore, how to reduce leakage current in transistors during operation is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, a semiconductor packaging structure, and an electronic device, which can reduce the source or drain leakage current of transistors during operation and improve transistor performance.

[0006] In a first aspect, embodiments of this application provide a semiconductor device including a substrate and a vertical channel transistor (VCT). The VCT is disposed on the substrate and includes a source, a drain, a gate, and a channel layer. The gate includes at least a first work function metal layer and a second work function metal layer. The channel layer extends in a direction perpendicular to the substrate, and the source and drain are respectively disposed at opposite ends in the extension direction of the channel layer. In a direction parallel to the substrate, the first work function metal layer surrounds the channel layer, and the second work function metal layer surrounds the channel layer. The absolute value of the difference in work function between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold.

[0007] Currently, when a high voltage is applied to the gate, source, and / or drain of a vertical-channel transistor (also known as a vertical transmission field-effect transistor), the tunneling effect causes a continuous leakage current during operation, affecting device performance. To address this, this application provides a semiconductor device in which the gate of the vertical-channel transistor is composed of at least two different work function metal layers, and the difference in their work functions exceeds a first threshold. Specifically, the gate is composed of at least a first work function metal layer and a second work function metal layer, and the absolute value of the difference between the work functions of the first and second work function metal layers is greater than or equal to the first threshold, which can be 0.1 electron volts. For example, the work function of the first work function metal layer can be greater than that of the second work function metal layer, or vice versa. When the difference exceeds 0.1 eV, the work function metal layer closer to the source or drain (such as the first work function metal layer) can effectively regulate the BTBT (Band-to-Band Tunneling) bandwidth near the source or drain during operation. This reduces the electric field strength from the source or drain to the channel extension region during continuous transistor operation, decreasing band bending and thus reducing GIDL or GISL current, improving transistor performance, and lowering the static power consumption during operation. Additionally, another work function metal layer farther from the source or drain (such as the second work function metal layer) can perform gate control to turn the transistor on or off.

[0008] In one possible implementation, the gate further includes a third work function metal layer disposed around the channel layer; the first work function metal layer, the second work function metal layer, and the third work function metal layer are stacked in a direction perpendicular to the substrate, and the second work function metal layer is disposed between the first work function metal layer and the third work function metal layer; the absolute value of the work function difference between the third work function metal layer and the second work function metal layer is greater than or equal to the first threshold.

[0009] In this embodiment, in addition to two different work function metal layers, the gate also has a third different work function metal layer, and the absolute value of the work function difference between the third work function metal layer and the second work function metal layer is greater than or equal to the first threshold. Therefore, the gate can also adjust the drain or source on the side away from the first work function metal layer through the third work function metal layer. This method of setting different work function metal layers on both sides of the second work function metal layer near the source and drain can simultaneously reduce GIDL and GISL. Moreover, during transistor operation, not only can the source or drain be voltaged separately or together, but the leakage current at the source or drain can also be reduced during operation when the top and bottom source and drain are interchanged, thereby improving transistor performance and making the semiconductor device in this embodiment more flexible. In addition, the work function of the third work function metal layer can be the same as or different from the work function of the first work function metal layer, and this embodiment does not specifically limit this.

[0010] In one possible implementation, when the channel layer is N-type doped, the work functions of both the first work function metal layer and the third work function metal layer are smaller than the work function of the second work function metal layer; when the channel layer is P-type doped, the work functions of both the first work function metal layer and the third work function metal layer are larger than the work function of the second work function metal layer.

[0011] In this embodiment, the relationship between the work functions of the first and third work function metal layers used for adjusting the electric field and the second work function metal layer used for gate control varies depending on the doping type of the channel. For example, when the channel layer is N-type doped, the work functions of the first and third work function metal layers need to be smaller than the work function of the second work function metal layer; when the channel layer is P-type doped, the work functions of the first and third work function metal layers need to be larger than the work function of the second work function metal layer, and the difference between the two still exceeds a first threshold. This setting can flexibly adapt to different types of transistors, adjusting the BTBT bandwidth near the source or drain without affecting other electrical parameters, reducing the leakage current at the source or drain during transistor operation, improving transistor performance, and reducing its corresponding static power consumption.

[0012] In one possible implementation, the thickness of the first work function metal layer is between one-tenth and one-third of the total gate thickness in a direction perpendicular to the substrate; the thickness of the third work function metal layer is between one-tenth and one-third of the total gate thickness.

[0013] In the embodiments of this application, the thickness of the first work function metal layer and the third work function metal layer is generally between one-tenth and one-third of the total gate thickness. This allows for adjustment of the BTBT bandwidth near the source or drain without affecting the normal gate control of the transistor. It also reduces the leakage current at the source or drain during transistor operation, thereby improving transistor performance and reducing its corresponding static power consumption.

[0014] In one possible implementation, the vertical channel transistor further includes a first spacer layer disposed between the source and the gate; the first work function metal layer includes a first portion and a second portion interconnected; wherein the first portion extends in a direction perpendicular to the substrate and surrounds the second work function metal layer and the channel layer in a direction parallel to the substrate; the second portion extends in a direction parallel to the substrate and is stacked on the first spacer layer in a direction perpendicular to the substrate.

[0015] In this embodiment, the gate comprises two different work function metal layers. A first portion of the first work function metal layer, extending perpendicular to the substrate, can be used to adjust the BTBT bandwidth near the drain, reducing leakage current, and can also assist the second work function metal layer in gate control of the transistor. Furthermore, this L-shaped gate configuration can enhance control over the channel region without increasing the horizontal footprint, thereby improving the gate's electrostatic control capability over the channel and simultaneously reducing leakage current at the source or drain of the transistor during operation.

[0016] In one possible implementation, when the channel layer is N-type doped, the work function of the first work function metal layer is less than the work function of the second work function metal layer; when the channel layer is P-type doped, the work function of the first work function metal layer is greater than the work function of the second work function metal layer.

[0017] In this embodiment, depending on the doping type of the channel, the work function of the first work function metal layer used to adjust the electric field and the second work function metal layer used for gate control have different relationships. This arrangement allows adjustment of the BTBT bandwidth corresponding to the source or drain near the first part of the gate without affecting other electrical parameters, reducing the leakage current at the source or drain during transistor operation, improving transistor performance, and reducing its corresponding static power consumption.

[0018] In one possible implementation, in the direction perpendicular to the substrate, the thickness of the second work function metal layer is between one-tenth and one-half of the thickness of the first portion of the first work function metal layer; and in the direction parallel to the substrate, the width of the second work function metal layer is between one-third and one-third of the width of the first portion.

[0019] In this embodiment, the thickness of the second work function metal layer is between one-tenth and one-half the thickness of the first part, and the width is between one-third and one-third the width of the first part. This setting can reduce the leakage current at the source or drain of the transistor during operation while adjusting the BTBT bandwidth near the source or drain, without affecting the normal gate control of the transistor, thus improving the transistor performance and reducing its corresponding static power consumption.

[0020] In one possible implementation, the channel layer includes a first semiconductor layer doped with an N-type or P-type material, the first semiconductor layer extending in a direction perpendicular to the substrate; or, the channel layer includes at least one nanosheet stacked in a direction perpendicular to the substrate.

[0021] In the embodiments of this application, the channel can be a doped cuboid or pillar, nanosheet, or other different structures, which can be flexibly adapted to different circuit structures.

[0022] In one possible implementation, the vertical channel transistor further includes a first dielectric layer, the channel layer including a second semiconductor layer doped with an N-type or P-type material; wherein the first dielectric layer extends in a direction perpendicular to the substrate and contacts the drain at one end in the direction of extension of the first dielectric layer; in a direction parallel to the substrate, the second semiconductor layer is disposed around the first dielectric layer and also around the drain; in a direction perpendicular to the substrate, the second semiconductor layer is also disposed between the other end in the direction of extension of the first dielectric layer and the source.

[0023] In the embodiments of this application, the channel can adopt a core-shell structure, that is, a core (first dielectric layer) and shell (second semiconductor layer) structure. This design will further optimize the electrical performance and reliability of the device, and achieve better carrier control and higher performance.

[0024] In one possible implementation, the source and drain may have the same or different doping types as the channel layer.

[0025] In the embodiments of this application, the vertical channel transistors involved can be junctionless transistors or junction transistors, which can be flexibly adapted to different circuit structures.

[0026] In a second aspect, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: providing a substrate; fabricating a vertical channel transistor on the substrate, wherein the vertical channel transistor includes a source, a drain, a gate, and a channel layer; the gate includes at least a first work function metal layer and a second work function metal layer; the channel layer extends in a direction perpendicular to the substrate, and the source and the drain are respectively disposed at both ends in the extension direction of the channel layer; in a direction parallel to the substrate, the first work function metal layer is disposed around the channel layer, the second work function metal layer is disposed around the channel layer, and the absolute value of the difference in work function between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold.

[0027] Thirdly, embodiments of this application provide a semiconductor packaging structure, which includes a packaging substrate and a semiconductor device according to any one of the first aspects, wherein the packaging substrate is electrically connected to the semiconductor device.

[0028] Fourthly, embodiments of this application provide an electronic device, the electronic device including a circuit board and the semiconductor package structure provided according to the third aspect, wherein the circuit board is electrically connected to the semiconductor package structure.

[0029] It should be understood that the method for preparing the semiconductor device provided in the second aspect of this application and the electronic device provided in the third aspect are consistent with the technical solution of the first aspect of this application. Their specific contents and beneficial effects can be referred to the semiconductor device provided in the first aspect above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0031] Figure 1 This is a schematic diagram of the structure of a set of semiconductor devices provided in the embodiments of this application.

[0032] Figure 2 This is a cross-sectional view of a semiconductor device provided in an embodiment of this application.

[0033] Figure 3 This is a cross-sectional view of another semiconductor device provided in an embodiment of this application.

[0034] Figure 4 This is a cross-sectional view of another semiconductor device provided in the embodiments of this application.

[0035] Figure 5 This is a schematic diagram of a process for fabricating a semiconductor device provided in an embodiment of this application.

[0036] Figures 6-10 This is a cross-sectional schematic diagram of a set of semiconductor fabrication devices provided in the embodiments of this application.

[0037] Figure 11 This is a schematic diagram of another process for fabricating a semiconductor device provided in an embodiment of this application.

[0038] Figures 12-14 This is a cross-sectional schematic diagram of another set of semiconductor fabrication devices provided in the embodiments of this application.

[0039] Figure 15 This is a schematic diagram of another semiconductor fabrication device provided in the embodiments of this application.

[0040] Figures 16-22 This is a cross-sectional schematic diagram of another set of semiconductor fabrication devices provided in the embodiments of this application.

[0041] Figure label:

[0042] 10 substrates, 20 vertical channel transistors;

[0043] 101 Source, 102 Drain, 103 Gate, 104 Channel layer, 105 First spacer layer, 106 Second spacer layer, 107 Gate dielectric layer, 108 Third spacer layer;

[0044] 1031 First work function metal layer, 1032 Second work function metal layer, 1033 Third work function metal layer;

[0045] 1131 First part, 1231 Second part; 1041 First dielectric layer, 1042 Second semiconductor layer. Detailed Implementation

[0046] The embodiments of this application will now be described with reference to the accompanying drawings.

[0047] The terms "first" and "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0048] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0049] For ease of description, embodiments of this application may use spatial relation terms such as "below," "below," "lower than," "below," "above," "upper," etc., to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of an element described as "below," "below," or "below" other elements or features will change to "above" said other elements or features. Thus, the exemplary terms "below" and "below" can encompass both up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0050] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0051] First, to facilitate understanding of the embodiments of this application, the following detailed analysis addresses the technical problems to be solved and the applicable application scenarios of the embodiments of this application.

[0052] With the advent of the artificial intelligence era, the demand for chip computing power is becoming more urgent. Traditional planar devices are constrained by factors such as photolithography precision and the quantum tunneling limit. Therefore, vertical channel transistors (VSTs) have received more attention. VSTs can be used in logic chips or memory chips.

[0053] In logic chip applications, vertical channel transistors can increase vertical degrees of freedom, decouple the contradiction between device feature size reduction and channel length, and have low parasitic capacitance and low dynamic power consumption, which can avoid reliability problems between metal interconnects in device miniaturization. In memory chip applications, using vertical channel transistors as gates can further reduce the area of ​​memory cells and improve the integration of memory chips.

[0054] However, for current vertical channel transistors, when there is a voltage difference (electric field) between the gate and drain of the transistor, or a voltage difference between the gate and source, the presence of the tunneling mechanism will cause GIDL or GISL leakage. For example, this leakage current may affect the retention time of the memory cell in the memory chip, and may also increase the power consumption performance of the memory chip and logic chip.

[0055] To address this issue and reduce leakage current in the GIDL or GISL adjustment of vertical channel transistors, this application proposes a semiconductor device that uses different metal work functions to adjust the BTBT bandwidth near the gate, source, or drain, thereby reducing GIDL or GISL leakage. For example, the device includes a substrate and a vertical channel transistor disposed on the substrate. The vertical channel transistor includes a source, a drain, a gate, and a channel layer. The gate includes at least a first work function metal layer and a second work function metal layer. The channel layer extends perpendicular to the substrate, and the source and drain are respectively disposed at opposite ends of the channel layer's extension direction. Parallel to the substrate, the first work function metal layer surrounds the channel layer, and the second work function metal layer surrounds the channel layer. The absolute value of the difference between the work functions of the first and second work function metal layers is greater than or equal to a first threshold. The structural configuration of this semiconductor device can also be referenced in the following embodiments.

[0056] Secondly, based on the technical problems mentioned above, and in order to facilitate understanding of the embodiments of this application, several semiconductor devices on which the embodiments of this application are based will be described below.

[0057] This application provides a semiconductor device including a substrate and a vertical channel transistor (VCT). The VCT is disposed on the substrate and includes a source, a drain, a gate, and a channel layer. The gate includes at least a first work function metal layer and a second work function metal layer. The channel layer extends in a direction perpendicular to the substrate, and the source and drain are respectively disposed at opposite ends in the extension direction of the channel layer. In a direction parallel to the substrate, the first work function metal layer surrounds the channel layer, and the second work function metal layer surrounds the channel layer. The absolute value of the difference in work function between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold.

[0058] Please refer to the attached document. Figure 1 , Figure 1 This is a schematic diagram of the structure of a set of semiconductor devices provided in the embodiments of this application.

[0059] like Figure 1The diagram shows a front view of a semiconductor device, which includes a substrate 10 and a vertical channel transistor 20. The vertical channel transistor 20, also referred to as a vertical transmission field-effect transistor, can be directly disposed on the substrate 10 and in contact with it; alternatively, it can be indirectly disposed on the substrate 10 by connecting to other structures (such as capacitors, other semiconductor devices, etc.) without direct contact with the substrate 10. This embodiment does not specifically limit the specific placement of the transistor in this application.

[0060] like Figure 1 The cross-sectional view of the semiconductor device shown shows that the vertical channel transistor 20 includes a source 101, a drain 102, a gate 103, and a channel layer 104. The gate 103 includes at least a first work function metal layer 1031 and a second work function metal layer 1032.

[0061] The channel layer 104 extends in a direction perpendicular to the substrate, and the source electrode 101 and the drain electrode 102 are respectively disposed at both ends in the extension direction of the channel layer; in a direction parallel to the substrate, the first work function metal layer 1031 is disposed around the channel layer 104, and the second work function metal layer 1032 is disposed around the channel layer 104.

[0062] It should be noted that in the embodiments of this application and the following related embodiments, the plane parallel to the surface of the substrate 10 and parallel to the plane parallel to the surface of the substrate 10 is as follows. Figure 1 The left-right direction shown is the X-axis direction. The Y-axis direction is the direction parallel to the surface of substrate 10 and perpendicular to the X-axis direction, i.e., as shown... Figure 1 The front-to-back direction is shown. The Z-axis direction is defined as the direction perpendicular to the surface of substrate 10, i.e., as shown... Figure 1 The vertical direction is shown. The X-axis, Y-axis, and Z-axis are all perpendicular to each other.

[0063] It should also be noted that the embodiments of this application only illustrate a portion of the structure of the vertical channel transistor 20, and the embodiments of this application do not impose specific limitations on the specific structure of the vertical channel transistor. For example, the vertical channel transistor may also have a spacer layer (not shown) between the gate and the source / drain, a gate dielectric layer (not shown) between the gate and the channel layer, and the source and / or drain may also be connected to a contact electrode (not shown), etc.

[0064] It should also be noted that, as mentioned above Figure 1 In the structure shown, the positions of the source 101 and the drain 102 can be interchanged in the embodiments of this application and any of the related embodiments below. For example, the source is located at the end away from the substrate, and the drain is located at the end closer to the substrate. This application does not limit this aspect.

[0065] Furthermore, the relative positions of the first work function metal layer 1031 and the second work function metal layer 1032 are not specifically limited in this embodiment. Figure 1 As shown, the first work function metal layer 1031 is closer to the source 101 than the second work function metal layer 1032. In other embodiments, the first work function metal layer 1031 may be closer to the drain 102 than the second work function metal layer 1032. The work functions of the first work function metal layer 1031 and the second work function metal layer 1032 are different. The difference between the work function of the first work function metal layer 1031 and the work function of the second work function metal layer 1032 exceeds a first threshold. That is, the work function of the first work function metal layer 1031 may be greater than the work function of the second work function metal layer 1032, or the work function of the first work function metal layer 1031 may be less than the work function of the second work function metal layer 1032, and the absolute value of the difference between the two is greater than the first threshold.

[0066] It is understandable that, taking a first threshold of 0.1 eV as an example, the difference between the work function of the first work function metal layer 1031 and the work function of the second work function metal layer 1032 exceeds 0.1 eV. However, this application embodiment does not specifically limit the magnitude of the first threshold and can adaptively adjust it according to the electrical characteristics of the vertical transistor, etc. For example, the first threshold could be 0.08 eV.

[0067] Correspondingly, the first work function metal layer 1031 can be used to effectively adjust the BTBT bandwidth (Band-to-Band Tunneling) near the gate and the source or drain, thereby reducing the electric field strength from the source or drain to the channel extension region when a high voltage is applied to the source or drain during transistor operation, reducing band bending, thereby reducing GIDL or GISL current, improving transistor performance, and reducing its corresponding static power consumption. Figure 1 As shown, the first work function metal layer 1031 is disposed near the source 101, which can increase the tunneling bandwidth near the source 101, reduce the electric field strength from the source 101 to the channel extension region, reduce band bending, and thus reduce the GISL current of the transistor during operation.

[0068] The second work function metal layer 1032 can be mainly used for gate control to control the on or off state of the vertical channel transistor. Furthermore, the effective work function of the gate 103 can be adjusted to regulate the threshold voltage.

[0069] Furthermore, for N-channel devices, the smaller the work function of the first work function metal layer 1031 compared to the second work function metal layer 1032, the larger the tunneling bandwidth and the smaller the leakage current at the source or drain of the transistor during operation; for P-channel devices, the larger the work function of the first work function metal layer 1031 compared to the second work function metal layer 1032, the larger the tunneling bandwidth and the smaller the leakage current at the source or drain of the transistor during operation.

[0070] The materials forming the first work function metal layer 1031 and the second work function metal layer 1032 can be at least one of the following materials, including but not limited to: tungsten (W), N-type or P-type polycrystalline silicon, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbon (TiAlC), titanium aluminum (TiAl), etc. It is understood that the selection of the material of the first work function metal layer 1031 needs to be coordinated with the doping type of the channel or the type of transistor, as well as the material of the second work function metal layer 1032. For example, for an N-type transistor, the material of the second work function metal layer 1032 can be W, and the material of the first work function metal layer 1031 can be n-type polycrystalline silicon. This application does not specifically limit this aspect.

[0071] Additionally, the substrate 10 can be made of at least one of the following materials: suitable elemental semiconductors such as silicon, diamond, or germanium; suitable alloy or compound semiconductors such as group IV compound semiconductors, for example, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn, etc.; and group III-V compound semiconductors, for example, suitable alloys or compound semiconductors such as gallium arsenide, indium gallium arsenide, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide. Insulating materials such as glass can also be used as the substrate, etc.

[0072] The source 101 and drain 102 can each be composed of heavily doped semiconductor layers. The source 101 or drain 102 can also include multiple different heavily doped regions or a stepped doping structure; this embodiment does not specifically limit the specific doping method. For example, the drain 102 has multiple doped regions, wherein the doping concentration of the doped regions closer to the gate 103 is lower than the doping concentration of the doped regions farther from the gate 103.

[0073] Understandably, the heavy doping range of source 101 and drain 102 can be 1×10⁻⁶. 20 cm -3 Up to 5×10 21 cm -3 The embodiments of this application do not impose specific limitations on this.

[0074] In addition, in some embodiments, the channel layer 104 can be a lightly doped or undoped semiconductor layer. When the channel layer 104 is lightly doped, the range of light doping can be 5 × 10⁻⁶.19 cm -3 The embodiments of this application are not specifically limited below.

[0075] The width of the channel layer 104 can be between tens of nanometers and micrometers, and the thickness can be between several nanometers and tens of nanometers. It can be a nanosheet, cuboid, cylinder, or core-shell structure, and more details can be found in the following embodiments.

[0076] In some embodiments, the gate further includes a third work function metal layer disposed around the channel layer; in a direction perpendicular to the substrate, the first work function metal layer, the second work function metal layer, and the third work function metal layer are stacked, and the second work function metal layer is disposed between the first work function metal layer and the third work function metal layer; the absolute value of the work function difference between the third work function metal layer and the second work function metal layer is greater than or equal to the first threshold.

[0077] Please refer to the attached document. Figure 2 , Figure 2 This is a cross-sectional view of a semiconductor device provided in an embodiment of this application. Figure 2 As shown, the gate 103 also includes a third work function metal layer 1033, which is disposed around the channel layer 104; in the direction perpendicular to the substrate, the first work function metal layer 1031, the second work function metal layer 1032 and the third work function metal layer 1033 are stacked, and the second work function metal layer 1032 is disposed between the first work function metal layer 1031 and the third work function metal layer 1033.

[0078] In addition to two different work function metal layers, the gate 103 also has a third different work function metal layer 1033. This third work function metal layer 1033 can be used to adjust the drain 102, which is far away from the first work function metal layer 1031, and reduce the leakage current induced by the gate 103 in the drain 102. This arrangement of work function metal layers with different work functions on both sides of the intermediate work function metal layer (second work function metal layer 1032) along the direction perpendicular to the substrate can reduce the electric field strength from the source 101 and drain 102 to the channel layer 104 extension region during transistor operation, i.e., when a high voltage is simultaneously applied to the source 101 and drain 102, thereby reducing band bending, decreasing GIDL or GISL current, improving transistor performance, and reducing its corresponding static power consumption. In addition, in applications where the top and bottom source-drain are interchanged or where the top and bottom parasitic resistance and capacitance of the vertical channel transistor are asymmetrical, adjustable bandwidth work function metal layers are provided on both sides of the second work function metal layer 1032. This can suppress leakage current effects and reduce GIDL or GISL currents, making the semiconductor device in this embodiment more flexible in circuit setup.

[0079] It should be noted that in some embodiments, as described above... Figure 2 As shown, the vertical channel transistor may also include a first spacer layer 105 and a second spacer layer 106. The first spacer layer 105 is disposed around the channel layer 104 and between the gate 103 and the source 101, for insulating the direct connection between the gate 103 and the source 101. The second spacer layer 106 is disposed around the channel layer 104 and between the gate 103 and the drain 102, for insulating the direct connection between the gate 103 and the drain 102.

[0080] It is understood that the first spacer layer 105 and the second spacer layer 106 may be insulating materials, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.

[0081] In some embodiments, the vertical channel transistor may further include a gate dielectric layer 107 disposed between the gate 103 and the channel layer 104. The material forming the gate dielectric layer 107 may include, but is not limited to, silicon oxynitride (SiON), silicon oxide (SiO), or silicon dioxide (SiO2).

[0082] In some embodiments, a high-dielectric-constant dielectric layer (not shown) may be disposed between the gate dielectric layer 107 and the gate 103. The gate structure formed by the gate and the gate 103 can be a high-k metal gate (HKMG), which is not specifically limited in this embodiment. The material forming the high-dielectric-constant dielectric layer can be a high-dielectric-constant material, such as including but not limited to: hafnium dioxide (HfO2) or hafnium silicon oxynitride (HfSiON).

[0083] In addition, the above Figure 1 The first spacer layer 105, the second spacer layer 106, and the gate dielectric layer 107 are not shown.

[0084] In some embodiments, when the channel layer is N-type doped, the work functions of the first work function metal layer and the third work function metal layer are both less than the work function of the second work function metal layer; when the channel layer is P-type doped, the work functions of the first work function metal layer and the third work function metal layer are both greater than the work function of the second work function metal layer.

[0085] It is understood that the channel layer in the embodiments of this application is often composed of a lightly doped or undoped semiconductor layer, such as lightly doped silicon. When the channel layer 104 is N-type doped, in order to increase the tunneling bandwidth, it is necessary to set work function metal layers with smaller work functions on both sides of the second work function metal layer 1032. Therefore, when the channel layer is N-type doped, the work functions of the first work function metal layer and the third work function metal layer can be smaller than the work function of the second work function metal layer. For example, when the material of the second work function metal layer 1032 is W, the first work function metal layer 1031 and the third work function metal layer 1033 can be n-type polycrystalline silicon or TiAl alloy with different doping concentrations, so that the work functions of the first work function metal layer 1031 and the third work function metal layer 1033 are more than 0.1 eV smaller than the work function of the second work function metal layer 1032.

[0086] When the channel layer 104 is P-type doped, the vertical channel transistor is a P-type transistor. In this case, to increase the tunneling bandwidth, it is necessary to set work function metal layers with larger work functions on both sides of the second work function metal layer 1032. Therefore, when the channel layer is P-type doped, the work functions of the first work function metal layer and the third work function metal layer can be greater than the work function of the second work function metal layer. For example, when the material of the second work function metal layer 1032 is W, the first work function metal layer 1031 and the third work function metal layer 1033 can be p-type polysilicon, TiN, or TaN with different doping concentrations, so that the work functions of the first work function metal layer 1031 and the third work function metal layer 1033 are greater than the work function of the second work function metal layer 1032 by more than 0.1 eV.

[0087] Therefore, depending on the doping type of the channel layer 104, in order to increase the tunneling bandwidth and reduce the leakage current at the source or drain during transistor operation, the work function relationships between the first work function metal layer and the third work function metal layer, and the second work function metal layer used for gate control, are adjusted differently. This configuration can flexibly adapt to different types of transistors and, without affecting other electrical parameters, adjust the BTBT bandwidth near the source or drain, thereby improving transistor performance and reducing the corresponding static power consumption during transistor operation.

[0088] In other embodiments, when the channel layer 104 is undoped, the relationship between the work function metal layers can be determined based on the type of the vertical channel transistor. For example, when the vertical channel transistor is an N-type transistor, the work functions of both the first and third work function metal layers are smaller than the work function of the second work function metal layer; when the vertical channel transistor is a P-type transistor, the work functions of both the first and third work function metal layers are larger than the work function of the second work function metal layer. This application does not impose specific limitations on this aspect.

[0089] In some embodiments, in a direction perpendicular to the substrate, the thickness of the first work function metal layer is between one-tenth and one-third of the total gate thickness; the thickness of the third work function metal layer is between one-tenth and one-third of the total gate thickness.

[0090] As mentioned above Figure 2As shown, the thicknesses of the first work function metal layer 1031 and the third work function metal layer 1033 are generally between one-tenth and one-third of the total thickness of the gate 103. For example, in the direction perpendicular to the substrate, the thickness of the first work function metal layer 1031 accounts for one-tenth of the total thickness of the gate 103, the thickness of the third work function metal layer 1033 accounts for one-tenth of the total thickness of the gate 103, and the remaining eight-tenths are the second work function metal layer 1032. Another example: in the direction perpendicular to the substrate, the thicknesses of the first work function metal layer 1031, the second work function metal layer 1032, and the third work function metal layer 1033 each account for one-third of the total thickness of the gate 103. This allows for adjustment of the BTBT bandwidth near the source or drain without affecting the normal gate control of the transistor, improving transistor performance and reducing the static power consumption during transistor operation.

[0091] It is understood that the thicknesses of the first work function metal layer 1031 and the third work function metal layer 1033 may be the same or different in the direction perpendicular to the substrate, and this embodiment does not specifically limit this.

[0092] In some embodiments, the vertical channel transistor further includes a first spacer layer disposed between the source and the gate; the first work function metal layer includes a first portion and a second portion interconnected; wherein the first portion extends in a direction perpendicular to the substrate and surrounds the second work function metal layer and the channel layer in a direction parallel to the substrate; the second portion extends in a direction parallel to the substrate and is stacked on the first spacer layer in a direction perpendicular to the substrate.

[0093] Please refer to the attached document. Figure 3 , Figure 3 This is a cross-sectional view of another semiconductor device provided in an embodiment of this application.

[0094] like Figure 3 As shown, the vertical channel transistor further includes a first spacer layer 105 disposed between the source 101 and the gate 103; the first work function metal layer 1031 includes a first portion 1131 and a second portion 1231 interconnected; wherein, the first portion 1131 extends in a direction perpendicular to the substrate, and in a direction parallel to the substrate, the first portion 1131 surrounds the second work function metal layer 1032 and the channel layer 104; the second portion 1231 extends in a direction parallel to the substrate, and in a direction perpendicular to the substrate, the second portion 1231 is stacked on the first spacer layer 105.

[0095] The gate 103 includes two different work function metal layers, which form an L-shaped gate configuration. The portion of the first portion 1131 extending perpendicular to the substrate that covers the second work function metal layer 1032 assists in gate control of the transistor. The remaining portion of the first portion 1131 not covering the second work function metal layer 1032 can be used to adjust the BTBT bandwidth near the drain 102, reducing the leakage current of the drain 102. Furthermore, this L-shaped gate configuration enhances control over the channel region without increasing the horizontal gate footprint, thereby improving the gate's electrostatic control capability over the channel and further reducing leakage current during transistor operation.

[0096] It is understandable that, such as Figure 3 The first spacer layer 105 shown is equivalent to the above. Figure 2 The first spacer layer shown is used to isolate the gate 103 and the source 101. Accordingly, as described above. Figure 3 As shown, the vertical channel transistor also includes a third spacer layer 108, which may be disposed around the gate 103 and a portion of the channel layer 104 to protect and insulate the gate 103 and the drain 102. This embodiment does not specifically limit this aspect.

[0097] In some embodiments, when the channel layer is N-type doped, the work function of the first work function metal layer is less than the work function of the second work function metal layer; when the channel layer is P-type doped, the work function of the first work function metal layer is greater than the work function of the second work function metal layer.

[0098] Depending on the doping type of the channel layer, the relationship between the work functions of the first work function metal layer used for adjusting the electric field and the second work function metal layer used for gate control varies. For example, when the channel layer is N-type doped, the work function of the first work function metal layer (including the first part 1131 and the second part 1231) is smaller than that of the second work function metal layer; when the channel layer is P-type doped, the work function of the first work function metal layer is larger than that of the second work function metal layer. This configuration allows adjustment of the BBT bandwidth corresponding to the drain 102 near the first part 1131 without affecting other electrical parameters, thereby improving transistor performance and reducing static power consumption during transistor operation. Other relevant descriptions regarding the work function can be found above. Figure 2 The descriptions of the work functions between metal layers with different work functions in the previous embodiments are not repeated here.

[0099] In some embodiments, in the direction perpendicular to the substrate, the thickness of the second work function metal layer is between one-tenth and one-half of the thickness of the first portion of the first work function metal layer; in the direction parallel to the substrate, the width of the second work function metal layer is between one-third and one-third of the width of the first portion.

[0100] As mentioned above Figure 3 As shown, in the direction perpendicular to the substrate, the thickness H1 of the second work function metal layer 1032 is between one-tenth and one-half of the thickness H2 of the first portion 1131; in the direction parallel to the substrate, the width K1 of the second work function metal layer 1032 is between one-third and one-third of the width K2 of the first portion 1131.

[0101] For example, H1 is greater than or equal to 0.1H2 and less than or equal to 0.5H2; K1 is greater than or equal to 0.3K2 and less than or equal to K2. That is, the width of the second work function metal layer 1032 can be the same as the width of the first part 1131. This setting can adjust the BTBT bandwidth near the drain without affecting the normal gate control of the transistor, thereby improving the transistor performance and reducing the static power consumption during transistor operation.

[0102] It should be noted that, in this embodiment, the width K2 of the first part 1131 is the width of the portion covering the surface of the second work function metal layer 1032. The width of the portion not covering the surface of the second work function metal layer 1032 and located near the channel layer 104 may be appropriately greater than or equal to the width K2 due to process influences. This embodiment does not specifically limit this aspect.

[0103] It should also be noted that the dimensions of the second part 1231 are not specifically limited in the embodiments of this application, and can be adaptively adjusted according to the electrical characteristics.

[0104] In some embodiments, the channel layer includes a first semiconductor layer doped with an N-type or P-type material, the first semiconductor layer extending in a direction perpendicular to the substrate; or, the channel layer includes at least one nanosheet stacked in a direction perpendicular to the substrate.

[0105] Understandably, as mentioned above Figure 2 and Figure 3 As shown, the channel layer 104 can be in the form of a cuboid or a prism, and is composed of a first semiconductor layer doped with N-type or P-type material. The first semiconductor layer extends in a direction perpendicular to the substrate and contacts the source and the drain in the extension direction, respectively.

[0106] The channel layer 104 can also be composed of at least one stacked nanosheet, which can be N-type or P-type doped. The channel layer of the nanosheet is not illustrated. Different channel structures can be flexibly adapted to different circuits, increasing the flexibility of the device.

[0107] In some embodiments, the vertical channel transistor further includes a first dielectric layer, the channel layer including a second semiconductor layer doped with an N-type or P-type material; wherein the first dielectric layer extends in a direction perpendicular to the substrate and contacts the drain at one end in the direction of extension of the first dielectric layer; in a direction parallel to the substrate, the second semiconductor layer is disposed around the first dielectric layer and also around the drain; in a direction perpendicular to the substrate, the second semiconductor layer is also disposed between the other end in the direction of extension of the first dielectric layer and the source.

[0108] Based on the above Figure 2 For example, please refer to the attached diagram for the gate structure shown. Figure 4 , Figure 4 This is a cross-sectional view of another semiconductor device provided in the embodiments of this application.

[0109] like Figure 4 As shown, the vertical channel transistor further includes a first dielectric layer 1041, and the channel layer 104 includes a second semiconductor layer 1042 doped with N-type or P-type material; wherein, the first dielectric layer 1041 extends in a direction perpendicular to the substrate, and one end of the first dielectric layer in the extension direction contacts the drain 102, and the other end contacts the second semiconductor layer 1042; in a direction parallel to the substrate, the second semiconductor layer 1042 is disposed around the first dielectric layer 1041, and also around the drain 102; in a direction perpendicular to the substrate, the second semiconductor layer 1042 is also disposed between the other end of the first dielectric layer 1041 in the extension direction and the source 101.

[0110] Thus, the first dielectric layer 1041 and the second semiconductor layer 1042 constitute a core-shell structure, namely a core (first dielectric layer 1041) shell (second semiconductor layer 1042) structure. This design will further optimize the electrical performance and reliability of the device, and achieve better carrier control and higher performance.

[0111] It is understandable that the gate structure can also be as described above. Figure 3 The L-shaped structure shown is not specifically limited in this embodiment of the application.

[0112] In some embodiments, the source and drain may have the same or different doping types as the channel layer.

[0113] It is understood that the doping type of the source 101 and drain 102 may be the same as or different from that of the channel layer 104. For example, when the channel layer 104 is N-type doped, the source 101 and drain 102 may also be N-type doped to form a junctionless transistor; when the channel layer 104 is N-type doped, the source 101 and drain 102 may also be P-type doped to form a junction transistor. This can be flexibly adapted according to different application scenarios, and the embodiments of this application do not make specific limitations in this regard.

[0114] Secondly, this application provides a method for fabricating a semiconductor device, which can be used to manufacture the semiconductor device mentioned in the above embodiments.

[0115] The method includes: providing a substrate; forming a vertical channel transistor on the substrate, wherein the vertical channel transistor includes a source, a drain, a gate, and a channel layer; the gate includes at least a first work function metal layer and a second work function metal layer; the channel layer extends in a direction perpendicular to the substrate, and the source and the drain are respectively disposed at both ends in the extension direction of the channel layer; in a direction parallel to the substrate, the first work function metal layer is disposed around the channel layer, the second work function metal layer is disposed around the channel layer, and the absolute value of the difference in work function between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold.

[0116] When fabricating a vertical channel transistor on the substrate, the fabrication process can be divided into different fabrication flows, such as channel first or channel later, depending on the different fabrication processes.

[0117] In response, regarding the channel-first fabrication process, based on the above method flow and the above... Figure 2 The semiconductor device shown is described in the appendix. Figures 5-10 , Figure 5 This is a schematic diagram of a process for fabricating a semiconductor device provided in an embodiment of this application; Figures 6-10 This is a cross-sectional schematic diagram of a set of semiconductor fabrication devices provided in the embodiments of this application.

[0118] Among them, such as Figure 5 As shown:

[0119] Step S11: Provide a substrate, and deposit a source, a channel layer and a drain on the substrate to obtain a first semiconductor structure.

[0120] like Figure 6As shown, a source electrode 101 is formed on a substrate 10 by means of ion implantation or vapor deposition; after depositing semiconductor material on the surface of the source electrode 101, a channel layer 104 and a drain electrode 102 are formed by means of etching to obtain a first semiconductor structure. The channel layer 104 extends in a direction perpendicular to the substrate, and the source electrode 101 and the drain electrode 102 are respectively disposed at both ends in the extension direction of the channel layer.

[0121] Step S12: A first spacer layer is deposited on the source surface of the first semiconductor structure to obtain the second semiconductor structure.

[0122] like Figure 7 As shown, a first spacer layer 105 is deposited on the remaining surface of the source electrode 101 that is not covered in the first semiconductor structure to obtain a second semiconductor structure. The first spacer layer 105 is disposed around the channel layer 104 and is in direct contact with the source electrode 101.

[0123] Step S13: Deposit and prepare a gate dielectric layer on the channel layer and drain surface of the second semiconductor structure to obtain the third semiconductor structure.

[0124] like Figure 8 As shown, in the second semiconductor structure, a gate oxide dielectric material is deposited on the peripheral surface of the channel layer 104 and the peripheral surface of the drain 102 to form a gate dielectric layer 107, thereby obtaining a third semiconductor structure.

[0125] Step S14: In the third semiconductor structure, a first work function metal layer, a second work function metal layer and a third work function metal layer are sequentially formed on the surface of the first spacer layer to obtain the gate.

[0126] like Figure 9 As shown, in the third semiconductor structure, different work function metal materials are deposited on the surface of the first spacer layer to sequentially form a first work function metal layer 1031, a second work function metal layer 1032, and a third work function metal layer 1033, thereby obtaining a gate 103. Specifically, in the direction perpendicular to the substrate, the first work function metal layer 1031, the second work function metal layer 1032, and the third work function metal layer 1033 are stacked, with the second work function metal layer 1032 disposed between the first work function metal layer 1031 and the third work function metal layer 1033. In the direction parallel to the substrate, the first work function metal layer 1031, the second work function metal layer 1032, and the third work function metal layer 1033 are all disposed around the channel layer 104.

[0127] In some embodiments, such as Figure 10 As shown, after the fabrication of the multilayer work function metal, the excess gate dielectric layer 107 can be etched away, leaving only the gate dielectric layer 107 between the gate 103 and the channel layer 104.

[0128] Step S15: Fabricate a second spacer layer to obtain a vertical channel transistor.

[0129] A second spacer layer 106 can be deposited on the surface of the etched fourth semiconductor structure to obtain the above-described result. Figure 2 The vertical channel transistor shown is an example. A second spacer layer 106 is disposed around the channel layer 104 and between the gate 103 and the drain 102, serving to insulate the direct connection between the gate 103 and the drain 102.

[0130] In other embodiments, a contact electrode may be provided on top of the exposed drain 102 to connect to other circuit structures.

[0131] It should be noted that the above refers to Figures 6-10 The specific fabrication process of the semiconductor device shown is merely an exemplary method, and the embodiments of this application do not specifically limit the specific fabrication process.

[0132] In other embodiments, for the channel-first fabrication process, based on the above method flow and the above... Figure 3 The semiconductor device shown is described in the appendix. Figures 11-14 , Figure 11 This is a schematic diagram of another process for fabricating a semiconductor device provided in an embodiment of this application; Figures 12-14 This is a cross-sectional schematic diagram of another set of semiconductor fabrication devices provided in the embodiments of this application.

[0133] Among them, such as Figure 11 As shown:

[0134] Step S21: Provide a substrate, and deposit a source, a channel layer and a drain on the substrate to obtain a first semiconductor structure.

[0135] Step S22: A first spacer layer is deposited on the source surface of the first semiconductor structure to obtain the second semiconductor structure.

[0136] Step S23: Deposit and prepare a gate dielectric layer on the channel layer and drain surface of the second semiconductor structure to obtain the third semiconductor structure.

[0137] For the descriptions of steps S21 to S23 above, please refer to the descriptions of steps S11 to S13 in the above embodiments. The embodiments of this application will not repeat them here.

[0138] Step S24: Deposit different work function metal layers on the surface of the first spacer layer in the third semiconductor structure to obtain the fourth semiconductor structure, so as to prepare and form the second work function metal layer and the first work function metal layer.

[0139] like Figure 12As shown, in the third semiconductor structure, a second work function metal layer 1032 is formed by depositing a work function metal material around the channel layer 104 on the surface of the first spacer layer 105. The second work function metal layer 1032 is disposed around a portion of the channel layer 104.

[0140] like Figure 13 As shown, different functional metal materials are deposited on the surface of the first spacer layer 105 and around the remaining portion of the channel layer 104 and the second work function metal layer 1032 to prepare and form the first work function metal layer 1031, thereby obtaining a fourth semiconductor structure.

[0141] The first work function metal layer 1031 includes a first portion 1131 and a second portion 1231 that are interconnected. The first portion 1131 extends in a direction perpendicular to the substrate and surrounds the second work function metal layer 1032 and the channel layer 104 in a direction parallel to the substrate. The first portion 1131 of the first work function metal layer 1031 also covers the surface of the gate dielectric layer 107. The second portion 1231 extends in a direction parallel to the substrate and is stacked on top of the first spacer layer 105 in a direction perpendicular to the substrate.

[0142] Step S25: Deposit insulating material on the surface of the fourth semiconductor structure to prepare and form the third spacer layer, thereby obtaining the fifth semiconductor structure.

[0143] like Figure 14 As shown, an insulating material is deposited on the surface of the fourth semiconductor structure to prepare and form the third spacer layer 108, thereby obtaining the fifth semiconductor structure.

[0144] Step S26: Etch the surface of the fifth semiconductor structure to expose the drain and obtain a vertical channel transistor.

[0145] After depositing the insulating material, excess deposited insulating material, part of the work function metal material, and part of the gate dielectric layer can be etched away, that is, the surface of the fifth semiconductor structure is etched to expose the drain 102, forming the third spacer layer 108 and the gate 103, thus obtaining the above-described... Figure 3 The vertical channel transistor shown.

[0146] In other embodiments, a contact electrode may be provided on top of the exposed drain 102 to connect to other circuit structures.

[0147] It should be noted that the above refers to Figures 12-14 The specific fabrication process of the semiconductor device shown is merely an exemplary method, and the embodiments of this application do not specifically limit the specific fabrication process.

[0148] For the fabrication process where the channel is downstream, based on the above method flow and the above... Figure 4 The semiconductor device shown is described in the appendix. Figures 15-22 , Figure 15 This is a schematic diagram of another semiconductor fabrication device provided in the embodiments of this application; Figures 16-22 This is a cross-sectional schematic diagram of another set of semiconductor fabrication devices provided in the embodiments of this application.

[0149] Among them, such as Figure 15 As shown:

[0150] Step S31: Provide a substrate, and sequentially deposit a source, a first spacer layer, a gate, and a second spacer layer on the substrate to obtain a sixth semiconductor structure.

[0151] like Figure 16 As shown, by means of vapor deposition, the corresponding materials are sequentially deposited on the substrate 10 to prepare the source 101, the first spacer layer 105, the gate 103 and the second spacer layer 106.

[0152] Step S32: Etch the surface of the sixth semiconductor structure to form the first opening.

[0153] like Figure 17 As shown, a first opening is etched on the surface of the sixth semiconductor structure to define a channel region. A first spacer layer 105 is exposed at the bottom of the first opening.

[0154] Step S33: A gate dielectric layer and a second semiconductor layer are sequentially deposited inside the first opening.

[0155] like Figure 18 As shown, a gate oxide dielectric material is deposited inside the first opening (including the sidewalls and bottom of the first opening) to form a gate dielectric layer 107, and a channel material doped with N-type or P-type is deposited to form a second semiconductor layer 1042.

[0156] Step S34: Etch the first opening after deposition to form the second opening.

[0157] like Figure 19 As shown, the first opening after deposition is etched to form a second opening, the bottom of which exposes the source electrode 101.

[0158] Step S35: A second semiconductor layer, a first dielectric layer, and a drain are sequentially deposited inside the second opening to obtain a vertical channel transistor.

[0159] like Figure 20 As shown, the same channel material as in step S33 above is deposited inside the second opening to form a second semiconductor layer 1042, wherein the second semiconductor layer 1042 directly contacts the source electrode 101. Figure 21 As shown, the remaining portion of the second opening is filled with insulating material to form a first dielectric layer 1041, constituting a channel layer 104. Figure 22 As shown, a groove is formed by etching the surface of the first dielectric layer 1041 inside the second opening to define the drain region. A drain electrode 102 is deposited inside the groove to obtain the result described above. Figure 4 The vertical channel transistor shown.

[0160] In other embodiments, a contact electrode may be provided on top of the exposed drain 102 to connect to other circuit structures.

[0161] It should be noted that the above refers to Figures 16-22 The specific fabrication process of the semiconductor device shown is merely an exemplary method, and the embodiments of this application do not specifically limit the specific fabrication process.

[0162] This application also provides a semiconductor packaging structure, which includes a packaging substrate and the semiconductor device involved in the above embodiments, wherein the packaging substrate is electrically connected to the semiconductor device.

[0163] This application also provides an electronic device, which includes a circuit board and the semiconductor packaging structure involved in the above embodiments, wherein the circuit board is electrically connected to the semiconductor packaging structure.

[0164] It should be understood that the semiconductor device fabrication method, packaging structure, and electronic device provided in this application can be consistent with the semiconductor device technical solution provided in this application, and their specific contents and beneficial effects can be referred to the above. Figures 1-4 The semiconductor devices mentioned in the illustrated embodiments will not be described in detail here.

[0165] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0166] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, The device includes a substrate and a vertical-channel transistor, the vertical-channel transistor being disposed on the substrate, the vertical-channel transistor including a source, a drain, a gate, and a channel layer; the gate including at least a first work function metal layer and a second work function metal layer; The channel layer extends in a direction perpendicular to the substrate, and the source and the drain are respectively disposed at both ends in the extension direction of the channel layer; In a direction parallel to the substrate, the first work function metal layer is disposed around the channel layer, the second work function metal layer is disposed around the channel layer, and the absolute value of the work function difference between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold.

2. The apparatus according to claim 1, characterized in that, The gate also includes a third work function metal layer, which is disposed around the channel layer; In a direction perpendicular to the substrate, the first work function metal layer, the second work function metal layer, and the third work function metal layer are stacked, and the second work function metal layer is disposed between the first work function metal layer and the third work function metal layer; The absolute value of the difference between the work function of the third work function metal layer and the second work function metal layer is greater than or equal to the first threshold.

3. The apparatus according to claim 2, characterized in that, When the channel layer is N-type doped, the work function of the first work function metal layer and the work function of the third work function metal layer are both smaller than the work function of the second work function metal layer. When the channel layer is P-type doped, the work function of the first work function metal layer and the work function of the third work function metal layer are both greater than the work function of the second work function metal layer.

4. The apparatus according to claim 2 or 3, characterized in that, In the direction perpendicular to the substrate, the thickness of the first work function metal layer is between one-tenth and one-third of the total gate thickness; The thickness of the third work function metal layer is between one-tenth and one-third of the total thickness of the gate.

5. The apparatus according to claim 1, characterized in that, The vertical channel transistor further includes a first spacer layer disposed between the source and the gate; the first work function metal layer includes a first portion and a second portion that are interconnected. Wherein, the first portion extends in a direction perpendicular to the substrate, and in a direction parallel to the substrate, the first portion surrounds the second work function metal layer and the channel layer; The second portion extends in a direction parallel to the substrate, and in a direction perpendicular to the substrate, the second portion is stacked on top of the first spacer layer.

6. The apparatus according to claim 5, characterized in that, When the channel layer is N-type doped, the work function of the first work function metal layer is less than the work function of the second work function metal layer. When the channel layer is P-type doped, the work function of the first work function metal layer is greater than the work function of the second work function metal layer.

7. The apparatus according to claim 5, characterized in that, In the direction perpendicular to the substrate, the thickness of the second work function metal layer is between one-tenth and one-half of the thickness of the first portion of the first work function metal layer; In the direction parallel to the substrate, the width of the second work function metal layer is between one-third and one-third of the width of the first portion.

8. The apparatus according to any one of claims 1-7, characterized in that, The channel layer includes a first semiconductor layer doped with N-type or P-type material, the first semiconductor layer extending in a direction perpendicular to the substrate; or... The channel layer includes at least one nanosheet stacked in a direction perpendicular to the substrate.

9. The apparatus according to any one of claims 1-7, characterized in that, The vertical channel transistor further includes a first dielectric layer, the channel layer including a second semiconductor layer doped with N-type or P-type material; wherein the first dielectric layer extends in a direction perpendicular to the substrate, and one end of the first dielectric layer in the extension direction is in contact with the drain. In a direction parallel to the substrate, the second semiconductor layer is disposed around the first dielectric layer and also around the drain electrode; In a direction perpendicular to the substrate, the second semiconductor layer is also disposed between the other end of the first dielectric layer extending in the same direction and the source electrode.

10. The apparatus according to claim 1, characterized in that, The source and drain may have the same or different doping types as the channel layer.

11. A method for fabricating a semiconductor device, characterized in that, The method includes: Provide substrate; A vertical channel transistor is formed on the substrate, wherein the vertical channel transistor includes a source, a drain, a gate, and a channel layer; the gate includes at least a first work function metal layer and a second work function metal layer; the channel layer extends in a direction perpendicular to the substrate, and the source and the drain are respectively disposed at both ends in the extension direction of the channel layer; in a direction parallel to the substrate, the first work function metal layer is disposed around the channel layer, the second work function metal layer is disposed around the channel layer, and the absolute value of the difference in work function between the first work function metal layer and the second work function metal layer is greater than or equal to a first threshold.

12. A semiconductor packaging structure, characterized in that, It includes a packaging substrate and a semiconductor device as described in any one of claims 1-10, wherein the packaging substrate is electrically connected to the semiconductor device.

13. An electronic device, characterized in that, It includes a circuit board and a semiconductor package structure as described in claim 12 above, wherein the circuit board is electrically connected to the semiconductor package structure.

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