An SGT device and a method of making the same

Abstract

The application provides an SGT device and a preparation method thereof. The SGT device comprises a gate and a shielding gate which is spaced from the gate by an oxide layer. A groove is formed on one side of the shielding gate close to the gate. The oxide layer comprises a first oxide layer arranged in the groove and a second oxide layer extended from the first oxide layer towards the gate. Specifically, the width of the gate polysilicon at the position above the shielding gate is reduced, and this part of the width is replaced by the oxide layer. The overlapping area of the shielding gate and the gate is reduced, the parasitic capacitance Cgs is reduced, the input capacitance Ciss is reduced, and the sidewall above the shielding gate retains the shielding gate polysilicon, so that the lateral auxiliary depletion of the shielding gate is not affected.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device manufacturing, and in particular to an SGT device and its fabrication method. Background Technology

[0002] In power semiconductor devices, shielded gate trench MOSFETs (SGT MOS) are widely used in high-frequency switching power supplies and motor drives due to their advantages such as low on-resistance and low gate-drain capacitance. Switching losses are the main factor restricting their high-frequency development, and the size of the input capacitance Ciss (Ciss = Cgs + Cgd) directly determines the switching speed and drive losses.

[0003] Traditional SGT structures effectively shield the coupling between the gate and drain by introducing a shielding electrode with a source potential at the bottom of the trench, significantly reducing the gate-drain capacitance Cgd. However, the overall input capacitance Ciss remains relatively large. This is mainly due to the large overlap area between the gate polysilicon and the N+ source region, forming a considerable gate-source capacitance Cgs. Simultaneously, the gate polysilicon and the underlying shielding polysilicon are isolated only by a thin inter-electrode dielectric layer, resulting in parasitic capacitances that are also connected in parallel across the gate and source, further increasing the total Ciss. During high-frequency switching, a higher Ciss requires the drive circuit to provide a larger peak current for charging and discharging, which not only increases drive losses but also exacerbates the Miller effect, limiting switching speed and reducing system efficiency.

[0004] As requirements for on-resistance, current carrying capacity, and heat dissipation increase, chip area grows, and parasitic capacitance further increases. Therefore, there is an urgent need to develop a novel SGT MOS structure that can effectively reduce input capacitance while maintaining the advantages of a shielded gate, thereby reducing switching losses and meeting the demands of high-frequency, high-efficiency power conversion. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide an SGT device and its fabrication method, which aims to effectively reduce the input capacitance while maintaining the advantages of the shielded gate.

[0006] An SGT device according to an embodiment of the present invention includes a gate and a shielding gate spaced apart from the gate by an oxide layer; The shielding gate has a groove on the side near the gate, and the oxide layer includes a first oxide layer disposed in the groove and a second oxide layer extending from the first oxide layer toward the gate.

[0007] Preferably, the width of the groove is 0.1μm to 0.3μm.

[0008] Preferably, the depth of the groove is 0.5μm to 2μm.

[0009] Preferably, the thickness of the second oxide layer is 2000 Å to 5000 Å.

[0010] Preferably, it further includes an epitaxial layer with a trench, the gate and the shielding gate disposed in the trench, and a P-type layer and an N-type layer sequentially doped on the side of the epitaxial layer away from the bottom of the trench, wherein the upper edge of the gate is flush with the upper edge of the trench, and the trench is filled with oxide except for the area where the gate and the shielding gate are located.

[0011] Preferably, the thickness of the third oxide layer between the trench and the shielding grid is 5600 Å to 6500 Å.

[0012] Preferably, the upper edge of the shielding grid is 1 μm to 1.5 μm away from the upper edge of the trench.

[0013] Preferably, the thickness of the fourth oxide layer between the gate and the trench sidewall is 400 Å to 600 Å.

[0014] Preferably, both the gate and the shielding gate are polycrystalline silicon.

[0015] According to an embodiment of the present invention, a method for fabricating an SGT device is provided for fabricating the aforementioned SGT device, the method comprising: An epitaxial layer with trenches is provided, and thermal oxidation is performed in the trenches to obtain a first initial oxide layer; An initial shielding gate is deposited in the trenches formed by the first initial oxide layer, and the initial shielding gate is etched back as a whole. Based on the overall re-etched shielding grid, the middle area of ​​the shielding grid is re-etched to a preset depth to form the groove; An oxide layer is deposited on the shielding gate to obtain a second initial oxide layer; The second initial oxide layer is etched back to obtain the first oxide layer and the second oxide layer, and then subjected to thermal oxidation to obtain the fourth oxide layer; Polysilicon is deposited in the trench formed by the second oxide layer and the fourth oxide layer to form a gate.

[0016] This invention provides an SGT device and its fabrication method, which involves setting a gate and a shielding gate separated from the gate by an oxide layer. The shielding gate has a groove on the side near the gate. The oxide layer includes a first oxide layer disposed within the groove and a second oxide layer extending from the first oxide layer toward the gate. Specifically, by reducing the width of the gate polysilicon above the shielding gate (this width is replaced by the oxide layer), the overlap area between the shielding gate and the gate is reduced, the parasitic capacitance Cgs is reduced, and thus the input capacitance Ciss is reduced. Furthermore, the sidewall above the shielding gate retains the shielding gate polysilicon, which does not affect the lateral auxiliary depletion of the shielding gate. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an SGT device provided in an embodiment of the present invention; Figure 2 A flowchart illustrating the implementation of an SGT device fabrication method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the process flow of an SGT device provided in an embodiment of the present invention.

[0018] Explanation of key component symbols:

[0019] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0021] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] refer to Figure 1 , Figure 1 This is a schematic diagram of an SGT device provided in an embodiment of the present invention. Specifically, the SGT device includes an epitaxial layer 1 with a trench 2, a gate 3 and a shielding gate 4 disposed within the trench 2, and a P-type layer 5 and an N-type layer 6 sequentially doped on the side of the epitaxial layer 1 away from the bottom of the trench 2. The gate 3 and the shielding gate 4 are both polysilicon. The upper edge of the gate 3 is flush with the upper edge of the trench 2. The trench 2, except for the area where the gate 3 and the shielding gate 4 are located, is filled with oxide. In this embodiment of the present invention, the thickness of the third oxide layer 7 between the trench 2 and the shielding gate 4 is 5600 Å to 6500 Å. For example, the third oxide layer 7 between the trench 2 and the shielding gate 4... The thickness is 5600Å, 5800Å, 6000Å, 6200Å, or 6500Å, etc., but not limited to these; the upper edge of the shielding gate 4 is 1μm to 1.5μm away from the upper edge of the trench 2. For example, the upper edge of the shielding gate 4 is 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, or 1.5μm away from the upper edge of the trench 2, but not limited to these; the thickness of the fourth oxide layer 8 between the gate 3 and the sidewall of the trench 2 is 400Å to 600Å. For example, the thickness of the fourth oxide layer 8 between the gate 3 and the sidewall of the trench 2 is 400Å, 450Å, 500Å, 550Å, or 600Å, etc., but not limited to these.

[0024] It should be noted that the epitaxial layer 1 includes a substrate, and an oxide layer (not shown), a silicon nitride layer (not shown), and another oxide layer (not shown) deposited on the substrate, forming a Hard Mask ONO structure.

[0025] More specifically, an oxide layer is spaced between the gate 3 and the shielding gate 4. A groove 9 is formed on the side of the shielding gate 4 near the gate 3. The oxide layer includes a first oxide layer 10 disposed in the groove 9 and a second oxide layer 11 extending from the first oxide layer 10 toward the gate 3. The width of the groove 9 is 0.1μm to 0.3μm, and the depth of the groove 9 is 0.5μm to 2μm, that is, the thickness of the first oxide layer 10 is 0.5μm to 2μm. For example, the width of the groove 9 is 0.1μm, 0.2μm, or 0.3μm, etc., but is not limited thereto; the depth of the groove 9 is 0.5μm, 1μm, 1.5μm, or 2μm, etc., but is not limited thereto. In addition, the thickness of the second oxide layer 11 is 2000Å to 5000Å. For example, the thickness of the second oxide layer 11 is 2000Å, 3000Å, 4000Å or 5000Å, etc., but is not limited to this. It can be understood that the thickness of the second oxide layer 11 can be understood as the distance between the gate 3 and the shield gate 4.

[0026] refer to Figure 2 and Figure 3 , Figure 2 This is a flowchart illustrating the fabrication method of an SGT device according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the process flow for an SGT device provided in an embodiment of the present invention. The fabrication method specifically includes the following steps: S100: Provide an epitaxial layer with trenches, and perform thermal oxidation treatment in the trenches to obtain a first initial oxide layer.

[0027] Specifically, the epitaxial layer includes substrate 1, and an oxide layer (not shown), a silicon nitride layer (not shown), and another oxide layer (not shown) deposited on the substrate to form a Hard Mask ONO (oxide-nitride-oxide) structure. Then, the Hard Mask in the trench portion is etched away using a trench photomask. The purpose is that the deeper the trench, the thicker the photoresist required for etching. However, if the photoresist is too thick, it is easy to collapse after exposure. Therefore, a Hard Mask is needed to replace the photoresist to reduce the photoresist thickness. Silicon nitride has a high selectivity to oxide. In addition to etching trenches, it can also be used as a barrier layer in subsequent CMP (chemical mechanical polishing) and HDP (high density plasma deposition) processes to protect the substrate surface from damage.

[0028] After etching trench 2, a thermal oxidation process is performed, which involves introducing oxygen at a high temperature of 800℃~1100℃ to form a first initial oxide layer 12 in the trench, serving as a dielectric layer with a thickness of 5600Å~6500Å. It should be noted that a high-quality oxide layer grown by thermal oxidation is crucial for the subsequent isolation effect between the shielding gate 4 and the epitaxial layer 1; the better the quality of the oxide layer, the better the isolation effect.

[0029] S200: Deposit an initial shielding gate in the trench formed by the first initial oxide layer, and then etch back the initial shielding gate as a whole.

[0030] Polycrystalline silicon is deposited in the trench formed by the first initial oxide layer 12 to obtain an initial shielding gate. The initial shielding gate is then etched back as a whole, with an etching depth of 1 μm to 1.5 μm.

[0031] S300: Based on the overall re-etched shielding grid, the middle area of ​​the shielding grid is re-etched to a preset depth to form the groove.

[0032] Understandably, the width of the groove 9 is 0.1μm~0.3μm, and the depth of the groove 9 is 0.5μm~2μm. The purpose of setting the groove 9 is to reduce the width above the shielding gate 4, reduce its effective overlap area with the subsequent gate 3, reduce the capacitance Cgs, and the shielding gate 4 retained on the sidewall still serves as a lateral auxiliary depletion.

[0033] S400: An oxide layer is deposited on the shielding gate to obtain a second initial oxide layer.

[0034] Specifically, the first initial oxide layer 12 located on the sidewall of the trench 2 is first etched to obtain the third oxide layer 7, and then the oxide is filled until the trench 2 is filled to obtain the second initial oxide layer, wherein the groove 9 contains the first oxide layer 10.

[0035] S500: The second initial oxide layer is etched back to obtain the first oxide layer and the second oxide layer, and then thermal oxidation is performed to obtain the fourth oxide layer.

[0036] In this process, the CMP is ground down to the nitride layer, then the Hard Mask layer is removed, and finally etched back to make the thickness of the second oxide layer 11 above the shield gate 4 2000Å~5000Å. Further, a fourth oxide layer 8 with a thickness of 400Å~600Å is generated by thermal oxidation to form the gate oxide of the MOS.

[0037] S600: Polysilicon is deposited in the trench formed by the second oxide layer and the fourth oxide layer to form a gate.

[0038] Finally, the region near the gate 3 in the epitaxial layer 1 is doped to obtain the P-type layer 5 and the N-type layer 6.

[0039] The present invention will be further described below with reference to specific embodiments: Example 1 Embodiment 1 of the present invention provides an SGT device, specifically including an epitaxial layer with a trench, a gate and a shielding gate disposed in the trench, and a P-type layer and an N-type layer sequentially doped on the side of the epitaxial layer away from the bottom of the trench, wherein the upper edge of the gate is flush with the upper edge of the trench, and the trench is filled with oxide except for the area where the gate and the shielding gate are located; The gate and the shielding gate are separated by an oxide layer, and a groove is formed on the side of the shielding gate near the gate. The oxide layer includes a first oxide layer disposed in the groove and a second oxide layer extending from the first oxide layer toward the gate. In this embodiment of the invention, the width of the groove is 0.1 μm, the depth of the groove is 0.5 μm, the thickness of the second oxide layer is 4000 Å, the thickness of the third oxide layer between the trench and the shielding gate is 6000 Å, the upper edge of the shielding gate is 1 μm away from the upper edge of the trench, and the thickness of the fourth oxide layer between the gate and the sidewall of the trench is 500 Å.

[0040] Example 2 Embodiment 2 of the present invention provides an SGT device, which differs from the SGT device in Embodiment 1 of the present invention in that the depth of the groove is 1μm.

[0041] Example 3 Embodiment 3 of the present invention provides an SGT device, which differs from the SGT device in Embodiment 1 of the present invention in that the depth of the groove is 2μm.

[0042] Example 4 Embodiment 4 of the present invention provides an SGT device, which differs from the SGT device in Embodiment 1 of the present invention in that the width of the groove is 0.2 μm.

[0043] Example 5 Embodiment 5 of the present invention provides an SGT device, which differs from the SGT device in Embodiment 1 of the present invention in that the width of the groove is 0.3 μm.

[0044] Example 6 Embodiment 6 of the present invention provides an SGT device, which differs from the SGT device in Embodiment 1 of the present invention in that the width of the groove is 0.2 μm and the depth of the groove is 1 μm.

[0045] Comparative Example 1 Comparative Example 1 provides an SGT device, which differs from the SGT device in Embodiment 1 of the present invention in that the shielding gate does not have a groove.

[0046] The SGT devices of Examples 1 to 6 and Comparative Example 1 were tested under the same conditions, wherein the input capacitance decrease rate is relative to Comparative Example 1. The specific results are as follows:

[0047] As can be seen from the above, the SGT device in the embodiments of the present invention effectively reduces the input capacitance. Specifically, the groove width has a significantly greater impact on the input capacitance reduction rate than the groove depth: when the groove width is fixed at 0.1 μm, increasing the depth from 0.5 μm to 2 μm only slightly increases the input capacitance reduction rate from 2.10% to 2.12% before saturating, indicating that the depth change has a limited effect on improving capacitance. However, when the groove depth is fixed at 0.5 μm, increasing the width from 0.1 μm to 0.2 μm and then to 0.3 μm results in an approximately linear increase in the input capacitance reduction rate, from 2.10% to 4.20% and 6.30%, respectively, with a significant and regular increase. Furthermore, comparing Embodiments 4 and 6, it can be seen that with a width of 0.2 μm, increasing the depth from 0.5 μm to 1 μm can increase the capacitance reduction rate from 4.20% to 4.80%, indicating that further increasing the depth on top of a larger width can bring additional benefits.

[0048] In summary, the SGT device and its fabrication method in this embodiment of the invention, by setting a gate and a shielding gate separated from the gate by an oxide layer, wherein a groove is formed on the side of the shielding gate near the gate, and the oxide layer includes a first oxide layer disposed in the groove and a second oxide layer extending from the first oxide layer toward the gate, specifically, by reducing the width of the gate polysilicon above the shielding gate, this portion of the width is replaced by the oxide layer, thereby reducing the overlap area between the shielding gate and the gate, reducing the parasitic capacitance Cgs, and thus reducing the input capacitance Ciss, and the sidewall above the shielding gate retains the shielding gate polysilicon, which does not affect the lateral auxiliary depletion of the shielding gate.

[0049] The SGT device and its fabrication method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0050] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0051] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An SGT device, characterized in that, Includes a gate and a shielding gate spaced apart from the gate by an oxide layer; The shielding gate has a groove on the side near the gate, and the oxide layer includes a first oxide layer disposed in the groove and a second oxide layer extending from the first oxide layer toward the gate.

2. The SGT device according to claim 1, characterized in that, The width of the groove is 0.1μm to 0.3μm.

3. The SGT device according to claim 2, characterized in that, The depth of the groove is 0.5μm~2μm.

4. The SGT device according to claim 3, characterized in that, The thickness of the second oxide layer is 2000 Å to 5000 Å.

5. The SGT device according to any one of claims 1 to 4, characterized in that, It also includes an epitaxial layer with a trench, the gate and the shielding gate disposed in the trench, and a P-type layer and an N-type layer sequentially doped on the side of the epitaxial layer away from the bottom of the trench, wherein the upper edge of the gate is flush with the upper edge of the trench, and the trench is filled with oxide except for the area where the gate and the shielding gate are located.

6. The SGT device according to claim 5, characterized in that, The thickness of the third oxide layer between the trench and the shielding grid is 5600 Å to 6500 Å.

7. The SGT device according to claim 6, characterized in that, The upper edge of the shielding grid is 1μm to 1.5μm away from the upper edge of the trench.

8. The SGT device according to claim 7, characterized in that, The thickness of the fourth oxide layer between the gate and the trench sidewall is 400 Å to 600 Å.

9. The SGT device according to claim 8, characterized in that, Both the gate and the shielding gate are polycrystalline silicon.

10. A method for fabricating an SGT device, characterized in that, The method for preparing the SGT device according to any one of claims 1 to 9 comprises: An epitaxial layer with trenches is provided, and thermal oxidation is performed in the trenches to obtain a first initial oxide layer; An initial shielding gate is deposited in the trenches formed by the first initial oxide layer, and the initial shielding gate is etched back as a whole. Based on the overall re-etched shielding grid, the middle area of ​​the shielding grid is re-etched to a preset depth to form the groove; An oxide layer is deposited on the shielding gate to obtain a second initial oxide layer; The second initial oxide layer is etched back to obtain the first oxide layer and the second oxide layer, and then subjected to thermal oxidation to obtain the fourth oxide layer; Polysilicon is deposited in the trench formed by the second oxide layer and the fourth oxide layer to form a gate.

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