High voltage semiconductor device

Abstract

A high voltage semiconductor device includes a semiconductor substrate, a p-type drift region, an n-type doped region, and an isolation structure. The p-type drift region is disposed in the semiconductor substrate, the n-type doped region is disposed in the p-type drift region, and a bottom of the n-type doped region is connected to a bottom of the p-type drift region. The isolation structure is disposed at least partially in the n-type doped region, the p-type drift region includes a first side, and the n-type doped region includes a second side that is located between the first side and the isolation structure in a horizontal direction. A distance between the second side and the isolation structure in the horizontal direction is less than a distance between the first side and the isolation structure in the horizontal direction.

Description

Technical Field

[0001] This invention relates to a high-voltage semiconductor device, and more particularly to a high-voltage semiconductor device comprising a p-type drift region and an n-type doped region. Background Technology

[0002] In power devices with high-voltage handling capabilities, double-diffused MOS (DMOS) transistors continue to receive significant attention. Common DMOS transistors include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. LDMOS transistors, due to their high operating bandwidth and efficiency, as well as their planar structure that facilitates integration with other integrated circuits, are widely used in high-voltage operating environments, such as CPU power supplies, power management systems, AC / DC converters, and high-power or high-frequency power amplifiers. A key feature of LDMOS transistors is the use of a laterally diffused drift region with low doping concentration to mitigate the high voltage between the source and drain terminals, thus enabling them to achieve a high breakdown voltage. However, as product requirements become increasingly stringent, improving the electrical performance, breakdown voltage, and / or reliability of high-voltage semiconductor devices through structural and / or fabrication process design adjustments remains a continuous area of ​​research for those in the field. Summary of the Invention

[0003] This invention provides a high-voltage semiconductor device that improves the electrical performance of the high-voltage semiconductor device and reduces the negative impact on reliability by setting an n-type doped region in the p-type drift region and controlling the range of the n-type doped region.

[0004] An embodiment of the present invention provides a high-voltage semiconductor device, including a semiconductor substrate, a p-type drift region, an n-type doped region, and an isolation structure. The p-type drift region is disposed in the semiconductor substrate, and the n-type doped region is disposed in the p-type drift region, with the bottom of the n-type doped region connected to the bottom of the p-type drift region. The isolation structure is at least partially disposed in the n-type doped region. The p-type drift region includes a first side surface, and the n-type doped region includes a second side surface located in a horizontal direction between the first side surface and the isolation structure. The horizontal distance between the second side surface and the isolation structure is less than the horizontal distance between the first side surface and the isolation structure. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a high-voltage semiconductor device according to the first embodiment of the present invention;

[0006] Figure 2 This is a partial flowchart illustrating a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention;

[0007] Figures 3 to 5 This is a schematic diagram of a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention, wherein...

[0008] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0009] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0010] Figure 6 This is a schematic diagram of a high-voltage semiconductor device according to a second embodiment of the present invention;

[0011] Figure 7 This is a schematic diagram of the collision ionization distribution of a high-voltage semiconductor device according to a second embodiment of the present invention;

[0012] Figure 8 This is a schematic diagram of the collision ionization distribution of the high-voltage semiconductor device according to the first embodiment of the present invention;

[0013] Figure 9 This is a schematic diagram of the current distribution of the high-voltage semiconductor device according to the second embodiment of the present invention;

[0014] Figure 10 This is a schematic diagram of the current distribution of the high-voltage semiconductor device according to the first embodiment of the present invention.

[0015] Symbol explanation:

[0016] 22: Semiconductor substrate

[0017] 24A: Isolation Structure

[0018] 24B: Isolation Structure

[0019] 24C: Isolation structure

[0020] 24D: Isolation Structure

[0021] 26: n-type doped deep well region

[0022] 26BS: Bottom surface

[0023] 28: P-type drift zone

[0024] 28BS: Bottom surface

[0025] 30: n-type doped region

[0026] 30BS: Bottom surface

[0027] 32A: n-type doped well region

[0028] 32B: n-type doped well region

[0029] 34: p-type heavily doped region

[0030] 36A: p-type heavily doped region

[0031] 36B: p-type heavily doped region

[0032] 38A: n-type heavily doped region

[0033] 38B: n-type heavily doped region

[0034] 101: High Voltage Semiconductor Device

[0035] 102: High-voltage semiconductor devices

[0036] BS: Bottom surface

[0037] D1: Vertical direction

[0038] D2: Horizontal direction

[0039] DP1: Depth

[0040] DP2: Depth

[0041] DS1: Distance

[0042] DS2: Distance

[0043] E1: Side view

[0044] E2: Side

[0045] E3: Side view

[0046] E4: Side view

[0047] GS1: Gate Structure

[0048] GS2: Gate Structure

[0049] SS1: Steps

[0050] SS2: Steps

[0051] SS3: Steps

[0052] SS4: Steps

[0053] T1: Endpoint

[0054] T2: Endpoint

[0055] T3: Endpoint

[0056] T4: Endpoint

[0057] W1: Width

[0058] W2: Width Detailed Implementation

[0059] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0060] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0061] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0062] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0063] The terms “forming” or “setting” are used below to describe the act of applying a layer of material to a substrate or forming a doped region in a substrate. These terms are intended to describe any feasible layer forming technique or doped region forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, ion implantation, etc.

[0064] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a high-voltage semiconductor device 101 according to a first embodiment of the present invention. Figure 1As shown, the high-voltage semiconductor device 101 includes a semiconductor substrate 22, a p-type drift region 28, an n-type doped region 30, and an isolation structure 24A. The p-type drift region 28 is disposed in the semiconductor substrate 22, and the n-type doped region 30 is disposed within the p-type drift region 28, with the bottom of the n-type doped region 30 (e.g., but not limited to the bottom surface 30BS) directly connected to the bottom of the p-type drift region 28 (e.g., but not limited to the bottom surface 28BS). The isolation structure 24A is at least partially disposed within the n-type doped region 30. The p-type drift region 28 includes a first side surface (e.g., side surface E1), and the n-type doped region 30 includes a second side surface (e.g., side surface E2) located in a horizontal direction D2 between side surface E1 and the isolation structure 24A. The distance DS2 between side surface E2 and the isolation structure 24A in the horizontal direction D2 is less than the distance DS1 between side surface E1 and the isolation structure 24A in the horizontal direction D2. By setting an n-type doped region 30 in the p-type drift region 28 and controlling the range of the n-type doped region 30, the electrical performance of the high-voltage semiconductor device 101 can be improved (e.g., but not limited to improving the breakdown voltage) and the negative impact on reliability can be reduced.

[0065] In some embodiments, a vertical direction D1 can be considered as the thickness direction of the semiconductor substrate 22. The semiconductor substrate 22 may have an upper surface and a bottom surface BS opposite each other in the vertical direction D1, and the p-type drift region 28 and the n-type doped region 30 may be adjacent to the upper surface. Horizontal directions that are substantially orthogonal to the vertical direction D1 (e.g., horizontal direction D2 and other directions orthogonal to the vertical direction D1) may be substantially parallel to the upper surface and / or the bottom surface BS of the semiconductor substrate 22, but are not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position and / or component and the bottom surface BS of the semiconductor substrate 22 may be greater than the distance in the vertical direction D1 between a relatively low position and / or component and the bottom surface BS of the semiconductor substrate 22. The lower part or bottom of each component may be closer to the bottom surface BS of the semiconductor substrate 22 in the vertical direction D1 than the upper part or top of that component. Another component above a certain component may be considered relatively far from the bottom surface BS of the semiconductor substrate 22 in the vertical direction D1, and another component below a certain component may be considered relatively close to the bottom surface BS of the semiconductor substrate 22 in the vertical direction D1. The upper surface and upper part of a specific component may respectively include the topmost surface and the uppermost part of that component in the vertical direction D1, while the bottom surface and bottom of a specific component may respectively include the bottommost surface and the bottommost part of that component in the vertical direction D1. The situation in which a particular component is positioned between two other objects in a certain direction, as described herein, may include, but is not limited to, the situation in which the component is sandwiched between the two objects in that direction.

[0066] In some embodiments, the high-voltage semiconductor device 101 may further include an n-type doped deep well region 26, a gate structure GS1, an n-type doped well region 32A, a first p-type heavily doped region (e.g., p-type heavily doped region 34), a second p-type heavily doped region (e.g., p-type heavily doped region 36A), an n-type heavily doped region 38A, and an isolation structure 24C. The n-type doped deep well region 26 and the n-type doped well region 32A are disposed in the semiconductor substrate 22, while the gate structure GS1 is disposed on the semiconductor substrate 22. A portion of the n-type doped well region 32A and a portion of the p-type drift region 28 are respectively located on opposite sides of the gate structure GS1 in the horizontal direction D2, and another portion of the n-type doped well region 32A and another portion of the p-type drift region 28 are located below the gate structure GS1 in the vertical direction D1. A portion of the n-type doped deep well region 26 is located below the p-type drift region 28 and the n-type doped region 30 in the vertical direction D1, and another portion of the n-type doped deep well region 26 is located below the n-type doped well region 32A in the vertical direction D1. The p-type heavily doped region 34 is disposed in the p-type drift region 28 and located in the n-type doped region 30, and the p-type heavily doped region 36A is disposed in the n-type doped well region 32A. The p-type heavily doped regions 34 and 36A are located on opposite sides of the gate structure GS1 in the horizontal direction D2. In some embodiments, the p-type heavily doped region 34 may be a drain doped region, the p-type heavily doped region 36A may be a source doped region, and the gate structure GS1, p-type drift region 28, n-type doped region 30, n-type doped well region 32A, p-type heavily doped region 34, p-type heavily doped region 36A, and n-type doped deep well region 26 may form a p-type lateral double-diffused metal-oxide-semiconductor (PLDMOS) transistor structure, but are not limited thereto. Furthermore, the isolation structure 24C and the n-type heavily doped region 38A may be disposed in the n-type doped well region 32A, at least a portion of the p-type heavily doped region 36A may be located between the gate structure GS1 and the isolation structure 24C in the horizontal direction D2, and the n-type heavily doped region 38A and the p-type heavily doped region 36A may be located on opposite sides of the isolation structure 24C in the horizontal direction D2.

[0067] In some embodiments, the gate structure GS1 may include a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer. The gate dielectric layer may include an oxide dielectric material (e.g., but not limited to silicon oxide), a high-k dielectric material, or other suitable dielectric material, while the gate electrode may include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate formed by stacking a work function layer and a low-resistance layer, but is not limited thereto. The isolation structures 24A and 24C may include single or multiple layers of insulating material, such as oxide insulating material or other suitable insulating material, and the isolation structures 24A and 24C may be considered as trench isolation structures, but are not limited thereto. In some embodiments, the semiconductor substrate 22 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. The aforementioned drift region, each doped region, and each doped well region can be formed by performing a suitable doping fabrication process (e.g., implantation process or other doping method) on the semiconductor substrate 22. For example, an n-type doped region or an n-type doped well region can be formed by doping a portion of the semiconductor substrate 22 with an n-type doped material, and a p-type doped region, a p-type doped well region, or a p-type drift region can be formed by doping a portion of the semiconductor substrate 22 with a p-type doped material. The doping dose of the heavily doped region can be relatively high, but this is not a limitation.

[0068] The aforementioned n-type dopant may include phosphorus (P), arsenic (As), or other suitable n-type dopant materials, while the aforementioned p-type dopant may include boron (B), gallium (Ga), or other suitable p-type dopant materials. In some embodiments, the p-type drift region 28 may include multiple p-type dopants (e.g., but not limited to boron), and the n-type doped region 30 may include multiple n-type dopants (e.g., but not limited to phosphorus) and a portion of the multiple p-type dopants in the p-type drift region 28. In other words, the n-type doped region 30 can be considered as a region formed by counter-doping a portion of the p-type drift region 28, and overall, the n-type doped region 30 still possesses the characteristics of a p-type semiconductor. Furthermore, in some embodiments, the n-type doped region 30 and the n-type doped well region 32A may be formed together using the same fabrication process and have the same n-type dopant. For example, the n-type doped region 30 includes a plurality of first n-type dopants, and the n-type doped well region 32A includes a plurality of second n-type dopants, and each first n-type dopant is the same as each second n-type dopant (e.g., but not limited to, both being phosphorus).

[0069] In some embodiments, at least a portion of the isolation structure 24A may be disposed below the gate structure GS1 in the vertical direction D1, and the side surfaces E1 and E2 may be located below the gate structure GS1 in the vertical direction D1. The side surface E1 of the n-type doped region 30 and the p-type heavily doped region 34 may be located on opposite sides of the isolation structure 24A in the horizontal direction D2, and a portion of the n-type doped region 30 and the p-type heavily doped region 34 may be located on opposite sides of the isolation structure 24A in the horizontal direction D2. The side surface E1 of the p-type drift region 28 and the p-type heavily doped region 34 may be located on opposite sides of the isolation structure 24A in the horizontal direction D2, and a portion of the p-type drift region 28 and the p-type heavily doped region 34 may be located on opposite sides of the isolation structure 24A in the horizontal direction D2. Furthermore, a portion of the n-type doped region 30 may be located between the isolation structure 24A and the n-type doped deep well region 26 in the vertical direction D1. The n-type doped region 30 may be directly connected to the n-type doped deep well region 26 located below the n-type doped region 30 in the vertical direction D1, and the p-type drift region 28 may be directly connected to the n-type doped deep well region 26 located below the p-type drift region 28 in the vertical direction D1, but this is not a limitation.

[0070] In some embodiments, the bottom surface 30BS of the n-type doped region 30 and the bottom surface 28BS of the p-type drift region 28 may be substantially coplanar, and the bottom surfaces 30BS and 28BS may be directly connected to the n-type doped deep well region 26, but this is not a limitation. The depth DP2 of the n-type doped region 30 in the vertical direction D1 (which can also be regarded as the length in the vertical direction D1) may be substantially equal to the depth DP1 of the p-type drift region 28 in the vertical direction D1 (which can also be regarded as the length in the vertical direction D1), and the length of the n-type doped region 30 in the horizontal direction D2 is less than the length of the p-type drift region 28 in the horizontal direction D2. The n-type doped region 30 is disposed in the p-type drift region 28 and does not exceed the range of the p-type drift region 28. In some embodiments, the p-type drift region 28 and the n-type doped region 30 may extend along another horizontal direction (e.g., but not limited to another horizontal direction orthogonal to the horizontal direction D2). The width W1 of the p-type drift region 28 and the width W2 of the n-type doped region 30 may be respectively regarded as the length of the p-type drift region 28 in the horizontal direction D2 and the length of the n-type doped region 30 in the horizontal direction D2, and the width W2 is smaller than the width W1. In some embodiments, the distance DS2 between the side surface E2 and the isolation structure 24A in the horizontal direction D2 may be greater than or equal to 0.16 times the distance DS1 between the side surface E1 and the isolation structure 24A in the horizontal direction D2, and the distance DS2 may be less than or equal to 0.5 times the distance DS1, but is not limited thereto. For example, the distance DS1 may be approximately 0.3 micrometers, and the distance DS2 may be between 0.05 micrometers and 0.15 micrometers, but is not limited thereto.

[0071] In some embodiments, the high-voltage semiconductor device 101 may further include a gate structure GS2, an n-type doped well region 32B, a p-type heavily doped region 36A, an n-type heavily doped region 38B, an isolation structure 24B, and an isolation structure 24D. The n-type doped well region 32B, the p-type heavily doped region 36A, and the n-type heavily doped region 38B are disposed in the semiconductor substrate 22, while the gate structure GS2 is disposed on the semiconductor substrate 22. The isolation structure 24B is at least partially disposed in the n-type doped region 30, and the isolation structure 24D is at least partially disposed in the n-type doped well region 32B. The n-type doped well regions 32A and 32B are located on opposite sides of the p-type drift region 28 in the horizontal direction D2, the isolation structures 24A and 24B are located on opposite sides of the p-type heavily doped region 34 in the horizontal direction D2, and the gate structures GS1 and GS2 are located on opposite sides of the p-type heavily doped region 34 in the horizontal direction D2. A portion of the n-type doped well region 32B and a portion of the p-type drift region 28 are located on opposite sides of the gate structure GS2 in the horizontal direction D2, and another portion of the n-type doped well region 32B and another portion of the p-type drift region 28 are located below the gate structure GS2 in the vertical direction D1. A portion of the n-type doped deep well region 26 is located below the n-type doped well region 32B in the vertical direction D1 and is directly connected to the n-type doped well region 32B. The p-type heavily doped region 36B is disposed in the n-type doped well region 32B, and the p-type heavily doped region 34 and the p-type heavily doped region 36B are located on opposite sides of the gate structure GS2 in the horizontal direction D2. Furthermore, the isolation structure 24D and the n-type heavily doped region 38B can be disposed in the n-type doped well region 32B, and at least a portion of the p-type heavily doped region 36B can be located between the gate structure GS2 and the isolation structure 24D in the horizontal direction D2, while the n-type heavily doped region 38B and the p-type heavily doped region 36B can be located on opposite sides of the isolation structure 24D in the horizontal direction D2.

[0072] In some embodiments, the p-type heavily doped region 34 can be a drain doped region, the p-type heavily doped region 36B can be a source doped region, and the gate structure GS2, p-type drift region 28, n-type doped region 30, n-type doped well region 32B, p-type heavily doped region 34, p-type heavily doped region 36B, and n-type doped deep well region 26 can form another p-type lateral double-diffused metal-oxide-semiconductor (PLDMOS) transistor structure. The PLDMOS transistor structures corresponding to gate structure GS1 and gate structure GS2 can share a drain (e.g., the p-type heavily doped region 34), but are not limited thereto. In some embodiments, gate structure GS1 and gate structure GS2 can be electrically connected to terminal T1, p-type heavily doped regions 36A and 36B can be electrically connected to terminal T2, p-type heavily doped region 34 can be electrically connected to terminal T3, and n-type heavily doped regions 38A and 38B can be electrically connected to terminal T4. Terminal T1 may include a gate terminal, terminal T2 may include a source terminal, terminal T3 may include a drain terminal, and terminal T4 may be used to adjust the potential of n-type doped well regions 32A and 32B through n-type heavily doped regions 38A and 38B respectively, but is not limited thereto. Gate structures GS1 and GS2 are separate from each other, and gate structures GS1 and GS2 may be formed together using the same fabrication process and have the same material composition. Isolation structures 24A, 24B, 24C, and 24D may be formed together using the same fabrication process and have the same material composition. n-type doped well regions 32A and 32B may be formed together using the same fabrication process and have the same material composition. p-type heavily doped regions 36A and 36B may be formed together using the same fabrication process and have the same material composition, but is not limited thereto.

[0073] In some embodiments, the p-type drift region 28 may have opposing sides E1 and a third side (e.g., side E3) in the horizontal direction D2, and the n-type doped region 30 may have opposing sides E2 and a fourth side (e.g., side E4) in the horizontal direction D2. Side E4 is located between side E3 and the isolation structure 24B in the horizontal direction D2. At least a portion of the isolation structure 24B may be disposed below the gate structure GS2 in the vertical direction D1, and sides E3 and E4 may be located below the gate structure GS2 in the vertical direction D1. Side E4 and the heavily doped p-type region 34 may be located on opposite sides of the isolation structure 24B in the horizontal direction D2, and a portion of the n-type doped region 30 and the heavily doped p-type region 34 may be located on opposite sides of the isolation structure 24B in the horizontal direction D2, respectively. Side E3 and p-type heavily doped region 34 may be located on opposite sides of isolation structure 24B in the horizontal direction D2, and a portion of p-type drift region 28 and p-type heavily doped region 34 may be located on opposite sides of isolation structure 24B in the horizontal direction D2. The distance between side E4 and isolation structure 24B in the horizontal direction D2 is less than the distance between side E3 and isolation structure 24B in the horizontal direction D2. In some embodiments, the distance between side E4 and isolation structure 24B in the horizontal direction D2 may be substantially equal to the distance DS2 mentioned above, and the distance between side E3 and isolation structure 24B in the horizontal direction D2 may be substantially equal to the distance DS1 mentioned above, but this is not a limitation.

[0074] Please see Figure 1 as well as Figures 2 to 5 . Figure 2 The diagram shown is a partial flowchart illustrating a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention. Figures 3 to 5 The illustration is a schematic diagram of a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention, wherein... Figure 4 It is illustrated Figure 3 The following is a diagram illustrating the situation, and Figure 5 It is illustrated Figure 4 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 5 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1As shown, the fabrication method of this embodiment includes the following steps. First, a semiconductor substrate 22 is provided, and an isolation structure 24 is formed in the semiconductor substrate 22. A p-type drift region 28 is formed in the semiconductor substrate 22, and an n-type doped region 30 is formed in the p-type drift region 28. The bottom of the n-type doped region 30 (e.g., but not limited to the bottom surface 30BS) is directly connected to the bottom of the p-type drift region 28 (e.g., but not limited to the bottom surface 28BS). The isolation structure 24A is at least partially located in the n-type doped region 30. The p-type drift region 28 includes a first side surface (e.g., side surface E1), and the n-type doped region 30 includes a second side surface (e.g., side surface E2) located between side surface E1 and the isolation structure 24A in the horizontal direction D2. The distance DS2 between side surface E2 and the isolation structure 24A in the horizontal direction D2 is less than the distance DS1 between side surface E1 and the isolation structure 24A in the horizontal direction D2.

[0075] To further explain, the manufacturing method of this embodiment may include, but is not limited to, the following steps. For example... Figure 2 and Figure 3 As shown, step SS1 can be performed first to form isolation structures (e.g., isolation structures 24A, 24B, 24C, and 24D) in the semiconductor substrate 22, followed by step SS2 to form a deep well region (e.g., an n-type doped deep well region 26). Then, as... Figure 2 and Figure 4 As shown, step SS3 can be performed to form a p-type drift region 28, and the bottom surface 28BS of the p-type drift region 28 is higher than the bottom surface 26BS of the n-type doped deep well region 26 in the vertical direction D1. Then, as... Figure 2 and Figure 5 As shown, step SS4 can be performed to form n-type doped region 30, n-type doped well region 32A, and n-type doped well region 32B. In some embodiments, n-type doped region 30, n-type doped well region 32A, and n-type doped well region 32B can be formed together using the same fabrication process (e.g., implantation process), therefore, n-type doped region 30, n-type doped well region 32A, and n-type doped well region 32B may include the same n-type dopant. Furthermore, a thermal fabrication process can be performed after step SS4 to activate the aforementioned doped regions, but this is not a limitation. Figure 5 and Figure 1 As shown, after the n-type doped region 30, the n-type doped well region 32A and the n-type doped well region 32B are formed, the above-mentioned gate structure GS1, gate structure GS2, p-type heavily doped region 34, p-type heavily doped region 36A, p-type heavily doped region 36B, n-type heavily doped region 38A and n-type heavily doped region 38B can be formed, thereby forming a high-voltage semiconductor device 101.

[0076] In some embodiments, the p-type drift region 28 may be formed together with p-type doped regions (e.g., but not limited to p-type doped well regions located in other regions of the semiconductor substrate 22) using the same fabrication process, while the n-type doped region 30, n-type doped well region 32A, and n-type doped well region 32B may be formed together with n-type doped regions (e.g., but not limited to n-type doped well regions located in other regions of the semiconductor substrate 22) using the same fabrication process. This simplifies the fabrication process and / or reduces production costs, but is not a limitation thereof. Therefore, by forming the n-type doped region 30 in the p-type drift region 28 and controlling the extent of the n-type doped region 30, the electrical performance of the high-voltage semiconductor device can be improved and the negative impact on reliability can be reduced without increasing additional fabrication process steps and / or production costs.

[0077] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0078] Please see Figure 6 . Figure 6 The illustration shows a schematic diagram of a high-voltage semiconductor device 102 according to a second embodiment of the present invention. Figure 6 As shown, in the high-voltage semiconductor device 102, the side surfaces E2 and E4 of the n-type doped region 30 may overlap or / and be aligned with the side surfaces E1 and E3 of the p-type drift region 28, respectively, and the n-type doped region 30 may be formed throughout the entire p-type drift region 28. In the high-voltage semiconductor device 102, the distance between side surface E2 and the isolation structure 24A in the horizontal direction D2 may be approximately equal to the distance between side surface E1 and the isolation structure 24A in the horizontal direction D2, and the distance between side surface E4 and the isolation structure 24B in the horizontal direction D2 may be approximately equal to the distance between side surface E3 and the isolation structure 24B in the horizontal direction D2.

[0079] Please see Figure 1 as well as Figures 6 to 10 . Figure 7 The diagram illustrates the impact ionization distribution of a high-voltage semiconductor device according to a second embodiment of the present invention. Figure 8 The diagram illustrates the collision ionization distribution of a high-voltage semiconductor device according to a first embodiment of the present invention. Figure 9 The diagram illustrates the current distribution of a high-voltage semiconductor device according to a second embodiment of the present invention. Figure 10 The diagram illustrates the current distribution of a high-voltage semiconductor device according to a first embodiment of the present invention. It is worth noting that... Figures 7 to 10 The distribution of the corresponding high-voltage semiconductor devices in a portion of the operating area is only shown in the diagram. Figures 7 to 10 The upper left part of the region can be the source region (e.g., the region corresponding to the p-type heavily doped region 36 Å), while Figures 7 to 10 The upper right part of the region can be the drain region (e.g., the region corresponding to p-type heavily doped region 34), but it is not limited to this. Figure 1 as well as Figures 6 to 8 As shown, by controlling the range of the n-type doped region 30 in the high-voltage semiconductor device 101 so that the width W2 of the n-type doped region 30 is smaller than the width W1 of the p-type drift region 28, the distribution of conflict ionization and / or electric field in the semiconductor substrate 22 can be changed, particularly reducing conflict ionization located below and near the isolation structure 24A. Figure 1 as well as Figures 6 to 10 As shown, by controlling the range of the n-type doped region 30 in the high-voltage semiconductor device 101, the distribution of collision ionization and / or electric field in the semiconductor substrate 22 can be altered, thereby reducing the impact of collision ionization on the current path (e.g., Figure 10 The current path in the process can be relatively wide, which can improve the reliability of high voltage semiconductor devices (for example, but not limited to improving the hot carrier injection (HCI) situation).

[0080] In summary, in the high-voltage semiconductor device and its fabrication method of the present invention, the electrical performance of the high-voltage semiconductor device (e.g., but not limited to increasing the breakdown voltage) can be improved by forming an n-type doped region in the p-type drift region and directly connecting the bottom of the n-type doped region to the bottom of the p-type drift region. Furthermore, the influence of conflict ionization on the current path can be reduced by controlling the lateral position of the n-type doped region, thereby improving reliability. In addition, the n-type doped region and other n-type doped well regions in the high-voltage semiconductor device can be formed together with n-type doped regions located in other regions of the semiconductor substrate using the same fabrication process, thereby simplifying the fabrication process and / or reducing production costs.

[0081] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high-voltage semiconductor device, comprising: Semiconductor substrate; A p-type drift region is disposed in the semiconductor substrate; An n-type doped region is disposed in the p-type drift region, wherein the bottom of the n-type doped region is connected to the bottom of the p-type drift region; as well as An isolation structure is at least partially disposed in the n-type doped region, wherein the p-type drift region includes a first side surface, and the n-type doped region includes a second side surface located in the horizontal direction between the first side surface and the isolation structure, and the distance between the second side surface and the isolation structure in the horizontal direction is less than the distance between the first side surface and the isolation structure in the horizontal direction.

2. The high-voltage semiconductor device of claim 1, wherein the bottom surface of the n-type doped region is coplanar with the bottom surface of the p-type drift region.

3. The high-voltage semiconductor device of claim 1, wherein the depth of the n-type doped region in the vertical direction is equal to the depth of the p-type drift region in the vertical direction.

4. The high-voltage semiconductor device of claim 1, wherein the distance between the second side and the isolation structure in the horizontal direction is greater than or equal to 0.16 times the distance between the first side and the isolation structure in the horizontal direction.

5. The high-voltage semiconductor device of claim 1, wherein the distance between the second side and the isolation structure in the horizontal direction is less than or equal to 0.5 times the distance between the first side and the isolation structure in the horizontal direction.

6. The high-voltage semiconductor device of claim 1, wherein the p-type drift region comprises a plurality of p-type dopants, and the n-type doped region comprises a plurality of n-type dopants and a portion of the plurality of p-type dopants in the p-type drift region.

7. The high-voltage semiconductor device as claimed in claim 1, further comprising: A gate structure is disposed on the semiconductor substrate, wherein at least a portion of the isolation structure is disposed below the gate structure in a vertical direction, and the first side and the second side are located below the gate structure in the vertical direction.

8. The high-voltage semiconductor device of claim 7, further comprising: A first p-type heavily doped region is disposed in the p-type drift region, wherein the first p-type heavily doped region is located in the n-type doped region, and the second side of the n-type doped region and the first p-type heavily doped region are respectively located on two opposite sides of the isolation structure in the horizontal direction.

9. The high-voltage semiconductor device of claim 8, wherein a portion of the n-type doped region and the first p-type heavily doped region are located on opposite sides of the isolation structure in the horizontal direction.

10. The high-voltage semiconductor device of claim 8, wherein the first side of the p-type drift region and the first p-type heavily doped region are respectively located on opposite sides of the isolation structure in the horizontal direction.

11. The high-voltage semiconductor device of claim 8, wherein a portion of the p-type drift region and the first p-type heavily doped region are located on opposite sides of the isolation structure in the horizontal direction.

12. The high-voltage semiconductor device of claim 8, further comprising: An n-type doped well region is disposed in the semiconductor substrate, wherein a portion of the n-type doped well region and a portion of the p-type drift region are respectively located on two opposite sides of the gate structure in the horizontal direction.

13. The high-voltage semiconductor device of claim 12, wherein the n-type doped region includes a plurality of first n-type dopants, the n-type doped well region includes a plurality of second n-type dopants, and each of the first n-type dopants is the same as each of the second n-type dopants.

14. The high-voltage semiconductor device of claim 12, further comprising: A second p-type heavily doped region is disposed in the n-type doped well region, wherein the first p-type heavily doped region and the second p-type heavily doped region are respectively located on two opposite sides of the gate structure in the horizontal direction.

15. The high-voltage semiconductor device of claim 14, wherein the first p-type heavily doped region is a drain doped region and the second p-type heavily doped region is a source doped region.

16. The high-voltage semiconductor device of claim 1, further comprising: An n-type doped deep well region is disposed in the semiconductor substrate, wherein a portion of the n-type doped deep well region is located below the p-type drift region and the n-type doped region in the vertical direction.

17. The high-voltage semiconductor device of claim 16, wherein a portion of the n-type doped region is located in the vertical direction between the isolation structure and the n-type doped deep well region.

18. The high-voltage semiconductor device of claim 16, wherein the n-type doped region is directly connected to the n-type doped deep well region located below the n-type doped region in the vertical direction.

19. The high-voltage semiconductor device of claim 16, wherein the p-type drift region is directly connected to the n-type doped deep well region located below the p-type drift region in the vertical direction.

20. The high-voltage semiconductor device of claim 1, wherein the length of the n-type doped region in the horizontal direction is less than the length of the p-type drift region in the horizontal direction.

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