An asymmetric HVCMOS device and a method of manufacturing the same

Abstract

The application discloses an asymmetric HVCMOS device and a preparation method thereof. The device comprises a semiconductor substrate, a drift region formed in the substrate, a gate structure, a source region and a drain region. A field plate is formed on the side surface of the side wall of the gate structure close to the source region, and the field plate is electrically connected with the source region. The field plate is composed of a dielectric material, and the electric field effect generated by the edge of the field plate can optimize the lateral electric field distribution on the surface of the drift region, thereby effectively improving the breakdown voltage of the device and reducing the surface leakage current. The key of the preparation method is that the process step of forming the field plate shares the same photoetching mask with the process step of forming the self-aligned silicide barrier layer, and the field plate is formed at the same time of defining the silicide barrier region through one-time photoetching and subsequent etching process. The application has the advantages of simple process, low cost and good compatibility with the existing production line.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a high-voltage complementary metal-oxide-semiconductor device, and more particularly to an asymmetric HVCMOS device with an optimized electric field distribution structure and its fabrication method. Background Technology

[0002] High-voltage complementary metal-oxide-semiconductor (HV-CMOS) technology is an extension of traditional CMOS technology into the high-voltage field. Compared with BCD technology, HV-CMOS technology has lower manufacturing costs, thus possessing significant market competitiveness in areas such as power management ICs, display drivers, automotive electronics, analog mixed-signal circuits, telecommunications networks, and medical devices.

[0003] However, the electrical performance of existing HVCMOS devices, especially their breakdown voltage, still has room for improvement. In high-voltage devices, the electric field is typically highly concentrated on the surface near the drift region at the gate edge, forming a "peak electric field." This becomes a major bottleneck limiting the device's withstand voltage and can lead to premature breakdown. Field plate structures are a commonly used technique to redistribute the surface electric field, alleviating localized strong electric field regions and thus improving the device's breakdown voltage. Traditional field plate structures may be located at the gate or drain, but their integration process can be complex or the optimization of the electric field distribution may not be ideal.

[0004] Therefore, there is a need in the field for an asymmetric HVCMOS device structure that is simple to integrate and can effectively improve voltage withstand performance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an asymmetric HVCMOS device and its fabrication method. The aim is to optimize the surface electric field distribution in the drift region through a source-end field plate structure with convenient process integration, thereby effectively improving the breakdown voltage of the device and reducing the surface leakage current.

[0006] In a first aspect, the present invention provides an asymmetric HVCMOS device, comprising: a substrate having a drift region and an isolation region therein; a polysilicon gate structure located on the substrate having sidewall structures formed on both sides thereon; a source region and a drain region formed in the substrate; further comprising: a single contact field plate formed between the sidewall surface near the source region and the source region; a silicide layer covering the polysilicon gate structure, the source region and the drain region; a dielectric layer covering the device; and contact holes formed through the dielectric layer and conductive material filling the contact holes.

[0007] In a second aspect, the present invention provides a method for fabricating the above-mentioned asymmetric HVCMOS device, comprising the following steps:

[0008] S1: Provide a substrate, and form a drift region and an isolation region within the substrate;

[0009] S2: Deposit a polysilicon layer on the substrate; etch the polysilicon layer to form a polysilicon gate structure; form sidewall structures on both sides of the polysilicon gate structure;

[0010] S3: A source region and a drain region are formed in the substrate; a single contact field plate is fabricated in a portion of the area between the source region and the sidewall surface near the source region.

[0011] S4: A silicide layer is formed on the polysilicon gate structure, source region, and drain region;

[0012] S5: Deposit a dielectric layer covering the device; form contact holes in the dielectric layer and fill the contact holes with conductive material.

[0013] The advantages of this invention are:

[0014] 1. Effectively Improves Breakdown Voltage: The field plate structure introduced in this invention at the source end generates a vertical electric field that can partially offset the lateral electric field peak near the drift region surface at the gate edge, resulting in a flatter surface electric field distribution. This effectively alleviates the electric field concentration phenomenon, improves the device's breakdown voltage, and enables the device to operate stably at higher voltages.

[0015] 2. Reduce surface leakage current: The vertical electric field applied by the source-end field plate can deplete the carriers on the surface of the drift region and block the formation of the inversion layer, thereby significantly reducing the surface leakage current of the device and improving the off-state characteristics of the device.

[0016] 3. Convenient process integration and low cost: The source-end field plate is fabricated using the same film structure as the self-aligned silicide barrier layer. This means that this field plate structure can be integrated into the existing HV-CMOS process flow without adding an additional photolithography mask step. This solution is simple to implement, does not increase additional process complexity or manufacturing costs, and is easy to implement on existing production lines. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure in step 301;

[0018] Figure 2 This is a schematic diagram of the structure in step 302;

[0019] Figure 3 This is a schematic diagram of the structure in step 303;

[0020] Figure 4 This is a schematic diagram of the structure in step 304;

[0021] Figure 5 This is a structural diagram of step 305. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0023] First Embodiment

[0024] refer to Figure 5 This embodiment provides an asymmetric high-voltage N-type metal-oxide-semiconductor device with a source-end contact field plate. This device structure is particularly suitable for realizing high-voltage laterally diffused MOSFETs or high-voltage LDMOS devices on the HV-CMOS process platform.

[0025] The device includes:

[0026] Semiconductor substrate 101. In this embodiment, the substrate 101 is a P-type single-crystal silicon substrate, and its resistivity can be selected according to the actual device requirements, for example, between 10 Ω·cm and 50 Ω·cm. Of course, the substrate 101 can also be a silicon-on-insulator (SOI) substrate, a strained silicon substrate, or other compound semiconductor substrates (such as SiC, GaN) to adapt to different application scenarios.

[0027] Drift region 102. The drift region 102 is formed within the surface region of the substrate 101. The conductivity type of the drift region 102 is the same as that of the source and drain regions, which is N-type in this embodiment. The drift region 102 is typically formed by ion implantation, such as implanting phosphorus (P) or arsenic (As) ions. Its doping concentration and junction depth are key parameters determining the device breakdown voltage and on-resistance (Ron,sp). Typically, the drift region 102 is lightly doped (e.g., doping concentration on the order of 1E16 cm⁻³ to 1E17 cm⁻³) and bears most of the applied high voltage by adjusting its length (L_drift). The terminal of the drift region 102 is connected to the drain region 107.

[0028] An isolation structure 103 is provided. The isolation structure 103 defines the active region and provides electrical isolation between devices. In this embodiment, the isolation structure 103 is preferably a shallow trench isolation (STI). Its formation process includes: depositing a hard mask layer (such as a silicon nitride / silicon oxide stack) on a substrate 101, photolithographically etching trenches, then growing or depositing an isolation dielectric (such as silicon dioxide) within the trenches, and finally planarizing the surface using a chemical mechanical polishing (CMP) process. The STI structure provides excellent surface planarization and isolation.

[0029] A polysilicon gate structure 104 is formed on a substrate 101, spanning the channel region and part of the drift region 102. Its fabrication process includes: sequentially growing a gate dielectric layer (such as a gate oxide layer with a thickness of 80-110 nm) on the substrate 101, followed by depositing a phosphorus-doped or boron-doped polysilicon layer (approximately 80-200 nm thick), and then patterning the polysilicon layer using photolithography and dry etching processes (such as reactive ion etching) to form the gate structure. The gate length and its coverage of the drift region are important factors affecting the device's threshold voltage and electric field distribution.

[0030] Sidewall structure 105. The sidewall structure 105 is formed on both sides of the polysilicon gate structure 104. It is typically a composite dielectric stack, for example, first depositing a thin silicon oxide pad layer (such as formed by thermal oxidation or chemical vapor deposition, with a thickness of about 5-15 nm), then depositing a thicker silicon nitride layer (with a thickness of about 30-80 nm), and finally removing the dielectric layer on the horizontal surface by an anisotropic dry etching (etch-back) process, leaving only the "sidewall" on the vertical sidewall. The sidewall 105 is used to achieve self-alignment of lightly doped drain (LDD) or extended region in subsequent source / drain implantation and serves as part of the silicide barrier layer.

[0031] Source region 106 and drain region 107. Source region 106 and drain region 107 are heavily doped regions. Source region 106 is located within the substrate on the gate side, adjacent to the channel region. Drain region 107 is located at the end of drift region 102. They are typically formed by implantation with a high dose of N-type ions (such as As+ or P+, on the order of 5E15 cm⁻²) followed by rapid thermal annealing. Source region 106 is typically shorted to the P-type body region (not shown separately in the figure, but can be integrated into substrate 101) through a contact hole to suppress parasitic bipolar transistor effects.

[0032] The core improvement of this invention is a single contact field plate 108. This contact field plate 108 is uniquely formed on the side surface of the gate sidewall 105 near the source region 106, and its lower end extends to the substrate surface, located between the edge of the sidewall 105 and the boundary of the source region 106. A thin dielectric layer (such as field oxide or deposited oxide, not separately indicated) is typically present between the field plate 108 and the underlying silicon substrate. Crucially, the contact holes and metal covering the field plate 108 achieve equipotential bonding with the source region 106, thereby fixing the local potential of the area where the field plate 108 is located to the source potential.

[0033] The field plate 108 is preferably a composite dielectric layer of silicon oxide and silicon nitride. The advantage of using this dielectric layer is its complete compatibility with standard CMOS processes, and its deposition and etching processes are very mature. The field plate can also withstand subsequent high-temperature process steps. In alternative embodiments, the field plate 108 may also be composed of a single layer of silicon oxide, or a combination of silicon oxide and silicon nitride of different thicknesses.

[0034] Dimensions: The lateral width (along the direction perpendicular to the gate) and vertical thickness of the field plate 108 are important design parameters. The width needs to be sufficient to cover the high electric field region below the gate edge, and is typically related to the sidewall width and the gate's coverage of the drift region. The thickness needs to ensure sufficient conductivity and mechanical stability. Optimized dimensions can be determined through device simulation (TCAD).

[0035] Silicide layer 109. To reduce parasitic resistance, a silicide layer 109 is formed on the top of the polysilicon gate structure 104 and on the surface of the source region 106 and drain region 107. The silicide layer 109 can be cobalt silicide (CoSi2), nickel silicide (NiSi), or titanium silicide (TiSi2), etc. The silicide layer 109 is formed by a self-aligned silicide process.

[0036] A dielectric layer 110, contact holes 111, and conductive plugs are included. One or more dielectric layers 110 (such as silicon dioxide deposited from tetraethyl orthosilicate, phosphosilicate glass, borosilicate glass, or low-k dielectric materials) cover the entire device structure. Multiple contact holes 111 are formed in the dielectric layer 110, exposing portions of the silicide layer 109 and the field plate 108. The contact holes 111 are filled with conductive material, such as tungsten plugs formed by chemical vapor deposition of tungsten followed by etch-back or chemical mechanical polishing, to achieve connection with subsequent interconnect metal lines. Specifically, one contact hole 111 connects the field plate 108 to the silicide layer 109 of the source region 106, thereby making the field plate 108 and the source at the same potential.

[0037] The working principle and beneficial effects of this invention are detailed below:

[0038] In traditional asymmetric high-voltage devices, when a high voltage is applied to the drain 107 while the gate 104 and source 106 are grounded, the depletion region extends from the drain junction to the source, forming an extremely high electric field peak at the silicon surface where the gate edge meets the drift region 102. This "hot spot" is the weakest link in the device, causing avalanche breakdown and limiting its maximum operating voltage.

[0039] The source-end contact field plate 108 introduced in this invention has a different equipotential distribution at its edge due to the metal connection above it being at the same potential as the source electrode. Consequently, the potential on the surface of the drift region 102 gradually increases from the source end to the drain end. Between the edge of the field plate 108 and the surface of the drift region 102, there exists a vertical electric field that is opposite to the direction of the transverse electric field of the drift region.

[0040] 1. Optimized electric field distribution and improved breakdown voltage: This vertical electric field generates an electric force pointing into the silicon mass, forcing the majority carriers (electrons in this case) near the surface of drift region 102 away from the surface, thus forming an additional depletion region near the surface. This additional depletion effect is equivalent to "flattening" the potential lines on the surface of the drift region, allowing the electric field peaks that were originally concentrated at the gate edge to be dispersed along a longer drift region path. From the perspective of the Poisson equation, the introduction of the field plate 108 is equivalent to introducing a fixed potential boundary condition on the surface of the drift region, modulating the two-dimensional distribution of the surface potential. The result is a significant reduction in the maximum electric field strength (Emax), thereby increasing the avalanche breakdown voltage (BV) of the device by 20% to 50% or even more (the specific value depends on the device structure and process parameters). This allows devices using the same process lithography node to withstand higher operating voltages.

[0041] 2. Suppressing Surface Leakage Current: Below the field plate 108, the vertical electric field it generates strongly depletes the carriers on the surface of the drift region 102. Under high drain voltage and gate voltage off conditions, this strong depletion layer effectively raises the surface barrier, preventing the formation of an inversion layer or accumulation layer and cutting off the leakage path along the surface. Therefore, the device's off-state leakage current (Ioff) and subthreshold swing characteristics are improved, which is crucial for low-power applications.

[0042] 3. Perfect Process Integration: Another significant advantage of this invention is its excellent process compatibility. As described in the following method embodiments, the formation of the field plate 108 can be cleverly combined with the fabrication process of the self-aligned silicide barrier layer. This means that the patterning step of defining the shape of the field plate can share the same photolithography and etching process with the step of defining which areas need to form silicide and which areas need to be protected (such as gate sidewalls, resistor regions, and the field plate regions of this invention). Therefore, in existing HV-CMOS process flows, no additional photomask is required, which greatly saves manufacturing costs and time, and is a key advantage enabling the industrialization of this invention.

[0043] Second embodiment: Preparation method

[0044] This embodiment provides a method for fabricating the aforementioned asymmetric HVCMOS device.

[0045] Step S301: Provide a substrate and form an isolation structure and drift zone.

[0046] like Figure 1As shown, firstly, a semiconductor substrate 101, such as a P-type silicon substrate, is provided. A hard mask layer is grown or deposited on the substrate 101, and shallow trenches are formed by photolithography and etching. Next, an isolation medium (such as silicon dioxide deposited by high-density plasma chemical vapor deposition) is filled into the trenches, and chemical mechanical polishing is performed to form a shallow trench isolation structure 103 to define the active region. Subsequently, N-type ions (such as phosphorus) are implanted into the region where the drift region 102 needs to be formed, with the implantation energy and dose designed according to the required junction depth and concentration, through photoresist masking. After implantation, high-temperature annealing is performed to activate impurities and repair lattice damage, forming the drift region 102. In this step, other basic doped regions such as P-type body regions and well regions can also be formed simultaneously or in stages.

[0047] Step S302: Form the gate structure and sidewalls.

[0048] like Figure 2 As shown, a high-quality gate oxide layer is grown on the cleaned silicon wafer surface via thermal oxidation. Subsequently, a layer of polysilicon is deposited via low-pressure chemical vapor deposition. This polysilicon layer is then in-situ doped (e.g., with phosphorus) or ion implanted to reduce its resistance. Next, photoresist is coated, the gate pattern is defined by photolithography, and the polysilicon layer is precisely patterned using dry etching (e.g., using a HBr / Cl2 / O2 mixed gas) to form a polysilicon gate structure 104. Afterward, sidewalls 105 are formed on both sides of the gate structure 104; these sidewalls 105 will be used for masking subsequent heavy source / drain doping implantation.

[0049] Step S303: Form the source region, the drain region, and the key structure of this invention—the source-end contact field plate, such as... Figure 3 As shown;

[0050] Source / drain implantation: Optionally, lightly doped drain implantation is performed first, followed by high-dose N+ source / drain implantation using sidewall 105 as a mask to form heavily doped source region 106 and drain region 107. Rapid thermal annealing is performed after implantation to activate impurities and form shallow junctions.

[0051] Definition of the field plate region: This is a core step in the process integration of this invention. After source and drain implantation is completed, a self-aligned silicide barrier layer needs to be prepared. Typically, a barrier dielectric (such as silicon nitride) is covered on the regions where silicide formation needs to be prevented (such as the gate sidewall sidewall, certain high-value resistor regions).

[0052] In this invention, the "source end field plate region" is also designed as one of the regions that need to be covered by the barrier layer. That is, when drawing the photolithographic pattern of the barrier layer, in addition to the conventional barrier pattern, a rectangular or strip pattern that is self-aligned with the sidewall is designed at a specific position on the sidewall 105 near the source region. This pattern corresponds exactly to the position of the field plate 108 to be formed later.

[0053] In terms of process, silicon oxide and silicon nitride are first deposited on the entire silicon wafer surface. Then, photoresist is coated, and photolithography exposure and development are performed using the same "silicide barrier mask". After development, the photoresist is removed in the areas where silicide needs to be formed (source region, drain region, gate top), exposing the underlying composite dielectric layer; while in the areas where it needs to act as a silicide barrier and field plate (such as gate sidewalls, high-value resistor regions, and planned field plate regions).

[0054] Next, dry etching is performed to remove the silicon nitride layer not protected by photoresist, exposing the underlying silicon oxide surface. The silicide barrier layer in the field plate region, protected by the photoresist, is preserved intact. Then, wet etching is performed to remove the exposed silicon oxide, and finally, the photoresist is removed. At this point, a field plate composed of silicon oxide and silicon nitride is formed at a predetermined location on the silicon wafer surface. This is a single contact field plate 108. Its position, shape, and size are precisely controlled by the photolithography and etching processes defined in the previous step.

[0055] Thus far, the formation of the field plate 108 did not introduce any new or independent photolithography steps, and fully reused the patterning process of the silicide barrier layer, achieving zero mask cost increase.

[0056] Step S304: Form a self-aligned silicide layer.

[0057] like Figure 4 As shown, after forming the field plate 108, a standard self-aligned silicide process is performed. First, a metal (such as nickel or cobalt) is deposited, followed by a first rapid thermal treatment to react the metal with the exposed silicon to form silicide. Next, unreacted metal is removed by selective wet etching. Finally, a second rapid thermal treatment is performed to transform the silicide phase into a low-resistivity stable phase (such as NiSi or CoSi2), thereby forming a low-resistivity silicide layer 109 on top of the source region 106, drain region 107, and gate 104.

[0058] Step S305: Forming contacts and interconnections.

[0059] like Figure 5As shown, firstly, a thick interlayer dielectric layer 110, such as silicon dioxide, is deposited on the silicon wafer surface using methods such as chemical vapor deposition. Then, contact hole photolithography and dry etching are performed to etch contact holes 111 into the dielectric layer 110. A critical contact hole simultaneously or separately exposes the silicide layer 109 of the source region 106 and the top of the adjacent field plate 108. Subsequently, conductive material is filled into the contact hole 111, typically by first depositing a titanium / titanium nitride adhesion / barrier layer, then depositing tungsten, and finally removing excess tungsten from the surface using CMP to form a tungsten plug. In this way, the field plate 108 is interconnected with the metal through this shared contact hole or an adjacent contact hole, and is electrically connected to the source potential.

[0060] Subsequently, standard back-end interconnect processes can be carried out, such as depositing metal layers (e.g., aluminum-copper alloys), vias, passivation layers, etc., to complete the manufacturing of the entire integrated circuit.

[0061] Third Embodiment: Variations and Extensions

[0062] This invention is not limited to the specific structure described above. Based on the same working principle, those skilled in the art can make various variations:

[0063] Field plate potential connection: The field plate 108 does not necessarily have to be connected to the source region 106 through the same contact hole. It can have its own independent contact hole, but ultimately it is shorted to the source line through wiring in the metal interconnect layer (such as the first metal layer M1) to achieve the same potential.

[0064] Field plate structure: Field plate 108 is a composite dielectric layer made of silicon oxide and silicon nitride. Its cross-sectional shape can be rectangular, trapezoidal or rounded at the top, so as to fine-tune its modulation effect on the electric field.

[0065] Device type: This invention is also applicable to P-type high voltage devices (HVPMOS), simply by reversing all conduction types (N-type to P-type, P-type to N-type). In this case, the field plate 108 is connected to a high potential (such as the source potential; for PMOS, the source is usually connected to a high voltage VDD).

[0066] Combination with other technologies: The source-end field plate structure of the present invention can be combined with other technologies to improve breakdown voltage, such as stepped field plates, lateral doping, buried layers, superjunction structures, etc., to obtain better overall performance.

[0067] In summary, this invention cleverly optimizes the surface electric field distribution of asymmetric HVCMOS devices by introducing a source-end contact field plate structure with zero added process cost, significantly improving the breakdown voltage and reducing the leakage current, thus providing a highly competitive solution for the manufacturing of cost-effective, high-performance high-voltage integrated circuits.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An asymmetric HVCMOS device, comprising: Semiconductor substrate; A drift region of a first conductivity type formed in the substrate; a gate structure located on the substrate, the gate structure including a gate dielectric layer, a polysilicon gate and sidewalls located on both sides of the polysilicon gate; a source region and a drain region of the same conductivity type as the drift region formed in the substrate; characterized in that it further includes a field plate formed on the side surface of the sidewall near the source region and electrically connected to the source region.

2. The device according to claim 1, characterized in that, The field plate and the source region are electrically connected through the same contact hole or through a metal interconnect, so that the potential of the field plate is the same as the potential of the source region.

3. The device according to claim 1 or 2, characterized in that, The field plate is made of a composite dielectric layer of silicon oxide and silicon nitride.

4. The device according to claim 1, characterized in that, The lower end of the field plate extends to the surface of the substrate, located between the edge of the sidewall and the source region.

5. A method for fabricating an asymmetric high-voltage CMOS device as described in any one of claims 1-4, characterized in that, Including the following steps: (a) Forming a drift region and isolation structure within a semiconductor substrate; (b) Forming a gate structure and sidewalls on the substrate; (c) Forming source and drain regions in the substrate; (d) A field plate is formed on the side surface of the sidewall near the source region; (e) A self-aligned silicide layer is formed on the surfaces of the gate, source, and drain regions; (f) Forming an interlayer dielectric layer and contact interconnect structure; In step (d), the process of forming the field plate shares the same photolithography patterning step as the process of forming the self-aligned silicide barrier layer.

6. The method according to claim 5, characterized in that, Step (d) specifically includes: (d1) On the device surface after source and drain injection, a composite dielectric layer as a silicide barrier layer is deposited; (d2) Photoresist is coated on the composite dielectric layer, and exposure and development are performed using a mask that defines the silicide blocking region and the field plate region pattern; (d3) Using the developed photoresist as a mask, dry etching and wet etching are performed sequentially to remove the composite dielectric layer in the photoresist-covered opening area, exposing the underlying silicon or polysilicon surface, while retaining the composite dielectric layer in the photoresist-covered area to form the field plate.

7. The method according to claim 6, characterized in that, The dielectric layer is a composite dielectric layer of silicon oxide and silicon nitride.

8. The method according to claim 5, characterized in that, In step (f), a contact structure is formed that short-circuits the field plate to the source region.

9. A power integrated circuit, characterized in that, It includes the asymmetric high-voltage CMOS device as described in any one of claims 1-4.

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