LDMOS device with lateral mixed gate structure and manufacturing method thereof
Patent Information
- Application Number
- CN202611142187.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-30
- Publication Date
- 2026-10-27
AI Technical Summary
[0028]根据本发明的一些实施例，在步骤S4中，采用干法刻蚀与湿法刻蚀相结合的刻蚀工艺去除漏端区域的所述第一介电常数材料层；步骤S5中采用原子层沉积工艺填补所述第二介电常数材料。
Smart Images
Figure CN122995207A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor power device technology, and in particular to an LDMOS device with a lateral hybrid gate structure and a method for fabricating the LDMOS device. Background Technology
[0002] Lateral double-diffused metal-oxide-semiconductor (LDMOS) is a core device in power integrated circuits and high-voltage integrated circuits. Due to its excellent voltage withstand performance and good compatibility with complementary metal-oxide-semiconductor (CMOS) technology, it has been widely used in power management chips, automotive electronics, and industrial and consumer electronics.
[0003] Traditional LDMOS devices typically include a P-type semiconductor substrate, P-type and N-type wells (N-type drift regions) formed on the substrate, and a gate dielectric layer, a polysilicon gate, and a sidewall structure sequentially formed on the substrate surface. The gate structure covers the channel region formed by the P-type well and extends above the N-type drift region. The drain region is formed by the heavily N-type doped region on the surface of the drift region and leads out the drain electrode, while the source region is formed by the heavily P-type doped region on the surface of the channel region and leads out the source electrode. Compared to traditional metal-oxide-semiconductor field-effect transistors (MOSFETs), LDMOS effectively improves the device's breakdown voltage (BV) by introducing a relatively long, lightly doped drift region between the channel and drain regions.
[0004] However, LDMOS devices have long faced a trade-off between on-resistance (Rsp) and breakdown voltage (BV) in their research and application. To overcome this bottleneck, the industry commonly employs the following techniques for optimization:
[0005] One approach is to increase the breakdown voltage by increasing the lateral length of the drift region. However, this inevitably leads to an increase in the on-resistance of the device, resulting in a larger overall device size, which severely affects power density and conversion efficiency, and is detrimental to device miniaturization.
[0006] Secondly, the gate dielectric material can be changed, for example, by introducing a single high-k dielectric material to replace traditional silicon oxide. However, the uniform dielectric constant distribution of high-k materials along the channel direction results in a monotonically smooth rising curve of the channel potential from the source to the drain, with only a single-peak electric field near the source in the channel. Under this electric field distribution mode, carriers can only reach velocity saturation in a small region near the peak of the electric field, and the device lacks an active electric field control mechanism. In addition, the global introduction of high-k dielectrics also brings severe process compatibility problems and significantly increases manufacturing costs.
[0007] Third, the surface electric field distribution can be improved by introducing a multilayer field plate structure. However, the fabrication process of multilayer field plates is extremely complex, requiring additional photolithography layers and process steps, which significantly increases manufacturing costs.
[0008] Furthermore, in practical applications, the three existing technologies mentioned above generally face reliability issues caused by the hot carrier injection (HCI) effect. Due to excessive concentration of the local electric field, threshold voltage drift and transconductance degradation are easily induced, severely shortening the lifespan of the device.
[0009] In summary, existing LDMOS devices still have significant shortcomings in terms of gate control capability, electric field distribution control, high-frequency characteristics, manufacturing process complexity, and hot carrier reliability, and urgently need further improvement. Summary of the Invention
[0010] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes an LDMOS device with a lateral hybrid gate structure, which can effectively break the trade-off between Rsp and BV without adding additional photolithography layers and complex process steps, improve the channel electric field distribution (introducing additional electric field peaks), suppress the hot carrier injection effect, and reduce the gate-drain parasitic capacitance, thereby simultaneously achieving a balance between high drive current, high switching speed, and high reliability.
[0011] The present invention also proposes a method for fabricating an LDMOS device having the above-mentioned lateral hybrid gate structure.
[0012] According to a first aspect of the present invention, an LDMOS device with a lateral hybrid gate structure includes: a substrate; an N-type drift region and a P-type body region formed on the substrate, a drain region being disposed on the surface of the N-type drift region, and a source region being disposed on the surface of the P-type body region; the drain region is used to lead out a drain electrode, and the source region is used to lead out a source electrode; a gate structure disposed across the N-type drift region and the P-type body region, the gate structure including a gate dielectric layer, a gate conductive layer, a sidewall, and a gate lead, the gate conductive layer being located on the gate dielectric layer, the sidewall being located on the sidewall of the gate structure, and the gate lead being located above the gate conductive layer; the gate dielectric layer is divided into a source dielectric region and a drain dielectric region along the channel direction. The source dielectric region is composed of a layer of second dielectric constant material and a layer of first dielectric constant material, and the drain dielectric region is composed of the second dielectric constant material, wherein the first dielectric constant is greater than the second dielectric constant; the physical thickness of the source dielectric region is greater than the physical thickness of the drain dielectric region, and the equivalent oxide layer thickness of the source dielectric region is less than the equivalent oxide layer thickness of the drain dielectric region; the gate conductive layer above the source dielectric region and the gate conductive layer above the drain dielectric region have different work functions, and the work function of the gate conductive layer above the source dielectric region is less than the work function of the gate conductive layer above the drain dielectric region.
[0013] At least the following beneficial effects are achieved: By employing a lateral segmentation design with a high K dielectric material at the source and a low K dielectric material at the drain in the gate dielectric layer, coupled with a stepped thickness (thicker at the source and thinner at the drain), and a gate conductivity layer configuration with a low work function at the source and a high work function at the drain, the source end, due to the synergistic effect of the high K dielectric and low work function, has an extremely thin equivalent oxide layer, endowing it with strong gate control capability and a low threshold voltage. The drain end, due to the low K dielectric and high work function, has a higher threshold voltage. This source-drain threshold voltage difference artificially induces an additional electric field peak at the interface between the two dielectrics. This peak promotes a larger range of carriers in the channel to enter the velocity saturation region, thereby significantly increasing the saturation drive current of the device without increasing the physical channel length and effectively reducing the on-resistance, breaking the inherent trade-off between breakdown voltage and on-resistance in traditional LDMOS. The drain dielectric region uses a second dielectric material with a low dielectric constant and a relatively thin physical thickness. This feature directly reduces the parasitic capacitance between the gate and drain. Since the characteristic frequency and switching speed of a device are primarily limited by the charging and discharging time of the gate-drain capacitance (Cgd), the structure of this invention achieves lower high-frequency losses and faster switching speeds while ensuring strong source-end driving capability, making the device better suited for high-frequency power switching applications. This invention effectively blocks the leakage path by maintaining a relatively thick physical thickness at the source end; simultaneously, it utilizes the inherent physical properties of high-k materials to ensure an extremely low equivalent oxide layer thickness. This "physically thick but equivalently thin" design can be achieved with simple adjustments to the deposition and etching processes, without the need for additional photolithography layers, ensuring excellent electrical performance while maintaining high compatibility with existing CMOS processes.
[0014] According to some embodiments of the present invention, the first dielectric constant material is hafnium dioxide, and the second dielectric constant material is silicon dioxide.
[0015] According to some embodiments of the present invention, the physical thickness of the source end dielectric region is 2~5 nm, and the physical thickness of the drain end dielectric region is 1~2.5 nm.
[0016] According to some embodiments of the present invention, the boundary point between the source dielectric region and the drain dielectric region is located in the middle region of the channel along the current direction, and is biased towards one side of the source region.
[0017] According to some embodiments of the present invention, the gate conductive layer located above the source dielectric region is titanium nitride, and the gate conductive layer located above the drain dielectric region is tantalum nitride.
[0018] According to some embodiments of the present invention, the threshold voltage abrupt change at the interface between the source dielectric region and the drain dielectric region due to the difference in dielectric constant and work function causes at least two electric field peaks to be formed in the transverse electric field distribution of the channel.
[0019] According to some embodiments of the present invention, the gate conductive layer is a polysilicon layer, the polysilicon layer above the source dielectric region has a first doping type and a first doping concentration, the polysilicon layer above the drain dielectric region has a second doping type and a second doping concentration, and the first doping type is different from the second doping type, and / or the first doping concentration is different from the second doping concentration, so that their work functions are different.
[0020] A method for fabricating an LDMOS device according to a second aspect of the present invention includes an LDMOS device with a lateral hybrid gate structure according to the first aspect of the present invention, and further includes the following steps:
[0021] S1: Provide a substrate, form a dummy gate structure on the surface of the substrate, and perform ion implantation and high-temperature annealing in the substrate on both sides of the dummy gate to form the N-type drift region, the P-type body region, the source region and the drain region;
[0022] S2: Remove the dummy gate structure to expose the gate trench;
[0023] S3: A second dielectric constant material layer is formed at the bottom of the gate trench as an interface layer, and a first dielectric constant material layer is deposited at low temperature on the interface layer to cover the entire channel region. The dielectric constant of the first dielectric constant material is greater than the dielectric constant of the second dielectric material.
[0024] S4: Coat the surface of the first dielectric constant material layer with photoresist, retain only the photoresist above the source region through photolithography, and completely etch away the first dielectric constant material layer in the drain region.
[0025] S5: Fill the gate trench in the drain region with a second dielectric constant material to form the gate dielectric layer containing the source first dielectric constant material and the drain second dielectric constant material;
[0026] S6: Deposit the gate conductive layer on the gate dielectric layer, and form conductive materials with different work functions above the source dielectric region and the drain dielectric region, respectively.
[0027] According to some embodiments of the present invention, in step S3, the low-temperature deposition is an atomic layer deposition process, and before depositing the first dielectric constant material layer, a silicon dioxide interface layer with a thickness of 0.5~1.5 nm is grown at the bottom of the gate trench using an in-situ water vapor generation process.
[0028] According to some embodiments of the present invention, in step S4, an etching process combining dry etching and wet etching is used to remove the first dielectric constant material layer in the drain region; in step S5, an atomic layer deposition process is used to fill the second dielectric constant material.
[0029] It has at least the following beneficial effects: The method for fabricating an LDMOS device has all the beneficial effects brought about by the aforementioned LDMOS device with a lateral hybrid gate structure, which will not be repeated here.
[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:
[0032] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention;
[0033] Figure 2 This is a schematic diagram of the structure after step S2 of the present invention is completed;
[0034] Figure 3 This is a schematic diagram of the structure after the silicon dioxide interface layer is completed in step S3 of this embodiment of the invention;
[0035] Figure 4 This is a schematic diagram of the structure after step S3 of the present invention is completed;
[0036] Figure 5 This is a schematic diagram of the structure after etching in step S4 of this embodiment of the invention;
[0037] Figure 6 This is a schematic diagram of the structure after filling in step S5 of an embodiment of the present invention;
[0038] Figure 7 This is a schematic diagram of a structure in which the gate conductive layer of an embodiment of the present invention uses polysilicon;
[0039] Figure 8 This is a schematic diagram of the structure of metals with different work functions used in the gate conductive layer according to an embodiment of the present invention;
[0040] Figure 9 This is a schematic diagram of the existing technology;
[0041] Figure 10 Simulation diagram of the lateral electric field of a traditional LDMOS device;
[0042] Figure 11 This is a simulation diagram of the lateral electric field of an LDMOS device according to an embodiment of the present invention.
[0043] Icon labels:
[0044] Substrate 101, N-type drift region 102, P-type body region 103, drain region 104a, source region 104c, drain electrode 105, source electrode 106, sidewall 107, gate dielectric layer 108, gate conductive layer 109, gate lead 111 Detailed Implementation
[0045] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0046] In the description of this invention, the use of "first" and "second" is for the purpose of distinguishing technical features only, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.
[0047] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0048] Reference Figure 1 , Figure 7 as well as Figure 8 This invention discloses an LDMOS device with a lateral hybrid gate structure, comprising:
[0049] Substrate 101; An N-type drift region 102 and a P-type body region 103 are formed on the substrate 101. A drain region 104a is disposed on the surface of the N-type drift region 102, and a source region 104c is disposed on the surface of the P-type body region 103. The drain region 104a is used to lead out the drain electrode 105, and the source region 104c is used to lead out the source electrode 106. A gate structure is disposed across the N-type drift region 102 and the P-type body region 103. The gate structure includes a gate dielectric layer 108, a gate conductive layer 109, a sidewall 107, and a gate lead 111. The gate conductive layer 109 is located on the gate dielectric layer 108, the sidewall 107 is located on the sidewall of the gate structure, and the gate lead 111 is located above the gate conductive layer 109. Gate dielectric layer 108 The channel is divided into a source dielectric region and a drain dielectric region. The source dielectric region is made of a layer of material with a second dielectric constant plus a layer of material with a first dielectric constant. The drain dielectric region is made of material with a second dielectric constant, and the first dielectric constant is greater than the second dielectric constant. The physical thickness of the source dielectric region is greater than the physical thickness of the drain dielectric region, and the equivalent oxide layer thickness of the source dielectric region is less than the equivalent oxide layer thickness of the drain dielectric region. The gate conductive layer 109 above the source dielectric region and the gate conductive layer 109 above the drain dielectric region have different work functions, and the work function of the gate conductive layer 109 above the source dielectric region is less than the work function of the gate conductive layer 109 above the drain dielectric region.
[0050] Understandably, by employing a lateral segmentation design in the gate dielectric layer with a high K dielectric at the source and a low K dielectric at the drain, coupled with a stepped thickness (thicker at the source and thinner at the drain) and a gate conductivity layer configuration with a low work function at the source and a high work function at the drain, the source, due to the synergistic effect of the high K dielectric and low work function, has an extremely thin equivalent oxide layer, giving it strong gate control capability and a low threshold voltage. The drain, on the other hand, has a higher threshold voltage due to the low K dielectric and high work function. This source-drain threshold voltage difference artificially induces an additional electric field peak at the interface between the two dielectrics. This peak promotes a larger range of carriers in the channel to enter the velocity saturation region, thereby significantly increasing the saturation drive current of the device without increasing the physical channel length and effectively reducing the on-resistance, breaking the inherent trade-off between breakdown voltage and on-resistance in traditional LDMOS. The drain dielectric region uses a second dielectric material with a low dielectric constant and a relatively thin physical thickness. This feature directly reduces the parasitic capacitance between the gate and drain. Since the characteristic frequency and switching speed of a device are primarily limited by the charging and discharging time of the gate-drain capacitance (Cgd), the structure of this invention achieves lower high-frequency losses and faster switching speeds while ensuring strong source-end driving capability, making the device better suited for high-frequency power switching applications. This invention effectively blocks the leakage path by maintaining a relatively thick physical thickness at the source end; simultaneously, it utilizes the inherent physical properties of high-k materials to ensure an extremely low equivalent oxide layer thickness. This "physically thick but equivalently thin" design can be achieved with simple adjustments to the deposition and etching processes, without the need for additional photolithography layers, ensuring excellent electrical performance while maintaining high compatibility with existing CMOS processes.
[0051] The key improvement in this implementation method is as follows:
[0052] The gate dielectric layer 108 is divided into a "source dielectric region" and a "drain dielectric region" along the current direction; the material of the source dielectric region is a material with a first dielectric constant (high K), and the material of the drain dielectric region is a material with a second dielectric constant (low K), and the first dielectric constant is greater than the second dielectric constant.
[0053] In terms of thickness, a "reverse matching" design is adopted: the physical thickness of the source dielectric region is greater than the physical thickness of the drain dielectric region (to prevent leakage), but due to the inherent characteristics of high-K materials, the equivalent oxide layer thickness (EOT) of the source dielectric region is smaller than the EOT of the drain dielectric region.
[0054] Furthermore, the gate conductive layer 109 located above the source dielectric region and the gate conductive layer 109 located above the drain dielectric region have different work functions, and the work function of the source is smaller than that of the drain.
[0055] Physical modeling and simulation analysis of this implementation method:
[0056] To theoretically elucidate the physical mechanism by which this implementation generates "double electric field peaks," simulation verification was performed based on the classic quasi-two-dimensional Poisson equation model of MOS devices.
[0057] This invention utilizes the lateral splicing of two materials with different dielectric constants, changing the uniform distribution of gate dielectric capacitance in traditional LDMOS. Based on the basic capacitance formula... The source end uses a high dielectric constant material (such as...) With a thinner equivalent oxide layer (EOT), the gate oxide capacitance (Cox1) per unit area is much greater than that of the drain end using a low dielectric constant material (such as...). The capacitance (Cox2) at that time. According to the characteristic length theory of MOS channel surface potential, the characteristic length is... This means that the feature length at the source end is much smaller than the feature length at the drain end.
[0058] Under the quasi-two-dimensional approximation, the smaller the feature length, the faster the channel surface potential rises with position x. Therefore, the source potential rises at a high rate, while the drain potential rises at a low rate. This embodiment also configures different gate work functions at the source and drain (the source work function is lower than the drain work function), which directly leads to a difference in their threshold voltages. At the physical interface between the two dielectric regions (i.e., the boundary point), the slope of the potential change and the abrupt change in the threshold voltage work together to force a transverse electric field ( A significant local peak appears. This local peak is superimposed on the original single-peak electric field in the conventional LDMOS channel, resulting in a clear "double electric field peak" distribution in the channel's transverse electric field.
[0059] Under typical LDMOS device operating bias conditions (e.g., drain voltage Vds is in various ranges below the breakdown voltage), the lateral hybrid gate structure of the present invention can always stably generate a dual electric field peak distribution, as verified by the above-mentioned quasi-two-dimensional Poisson equation and TCAD simulation software. This proves that the structure has a robust control effect on the changes in bias voltage, channel length and process parameters.
[0060] Simulation results from this implementation method prove the above theoretical derivation. For example... Figure 10 As shown, in traditional LDMOS devices, the surface potential rises monotonically and smoothly, and the lateral electric field exhibits only a single-peak structure; while... Figure 11As shown, in this embodiment, an inflection point appears at the dielectric interface, and the lateral electric field is effectively reshaped into a double-peak structure. Simulation verification confirms that this "double electric field peak" not only effectively shares the local high voltage in the drain region and significantly suppresses the hot carrier injection effect, but also expands the range for carriers in the channel to enter the velocity saturation region, resulting in a significant improvement in the saturation drive current of this invention, breaking through the traditional trade-off between Rsp and BV in LDMOS.
[0061] Furthermore, in some preferred embodiments of the present invention, the first dielectric constant material is hafnium dioxide, and the second dielectric constant material is silicon dioxide.
[0062] It is understandable that, preferably, the first dielectric constant material (high K at the source end) is hafnium dioxide ( The second dielectric constant material (low K at the drain end) is silicon dioxide ( ). Its relative permittivity is approximately 25. Approximately 3.9. This classic material combination achieves a significant difference in dielectric constant (more than 6 times), ensuring that the ΔVt between the source and drain is sufficiently significant, thus generating a strong additional electric field peak. Furthermore, both materials are existing, mature materials in the industry, eliminating the need for additional material development.
[0063] Furthermore, in some preferred embodiments of the present invention, the physical thickness of the source-end dielectric region is 2~5 nm, and the physical thickness of the drain-end dielectric region is 1~2.5 nm.
[0064] As a preferred specific thickness parameter, the physical thickness of the source-end dielectric region is 2~5 nm, and the physical thickness of the drain-end dielectric region is 1~2.5 nm. The source-end thickness is 2~5 nm. This effectively suppresses "quantum tunneling leakage current" caused by excessively thin high-k dielectric, ensuring gate reliability. Simultaneously, due to its high dielectric constant, despite a physical thickness of 2-5 nm, the calculated EOT remains extremely thin (even less than 1 nm), guaranteeing excellent strong drive current. The drain terminal... Maintaining a thickness of 1~2.5nm allows for further reduction of the physical thickness while ensuring the device's withstand voltage capability, thereby significantly reducing Cgd (gate-drain capacitance) and improving switching speed.
[0065] Furthermore, in some embodiments of the present invention, the boundary between the source dielectric region and the drain dielectric region is located in the middle region of the channel along the current direction, and is biased toward one side of the source region 104c.
[0066] Preferably, setting the dielectric boundary point on the middle-side bias source ensures that the newly introduced "extra electric field peak" is located in the region where the channel electric field originally began to decay, thus playing a relay boosting role and leveraging the driving effect of the extra peak to enable a larger range of charge carriers to reach velocity saturation first, thereby increasing the device's driving current.
[0067] Furthermore, referring to Figure 8 In some preferred embodiments of the present invention, the gate conductive layer 109 located above the source dielectric region is titanium nitride, and the gate conductive layer 109 located above the drain dielectric region is tantalum nitride.
[0068] The work function of TiN is typically around 4.4 eV, while that of TaN is around 4.7 eV, with a work function difference of about 0.3 eV between the two. This "bimetallic gate" structure can directly, accurately, and stably increase the threshold voltage difference (ΔVt) between the source and drain terminals without additional ion implantation doping, and the fabrication process has extremely high repeatability and uniformity.
[0069] Furthermore, referring to Figure 7 In some preferred embodiments of the present invention, the gate conductive layer 109 is a polysilicon layer, the polysilicon layer above the source dielectric region has a first doping type and a first doping concentration, the polysilicon layer above the drain dielectric region has a second doping type and a second doping concentration, and the first doping type is different from the second doping type, and / or the first doping concentration is different from the second doping concentration, so that their work functions are different.
[0070] As an alternative implementation, if polysilicon is used as the gate conductive layer 109, its work function can be altered through ion implantation doping. Specifically, the polysilicon layer above the source dielectric region uses a first doping type and a first doping concentration, while the polysilicon layer above the drain dielectric region uses a second doping type and a second doping concentration. The first doping type can be different from the second doping type, or the first doping concentration can be different from the second doping concentration, thereby creating a difference in their work functions. This polysilicon doping scheme complements the metal gate scheme. For traditional foundries without metal gate process modules, work function differentiation can be achieved through region-selective ion implantation of the polysilicon (e.g., N-type doping at the source, P-type doping at the drain, or using different doping doses). This approach significantly lowers the barrier to device manufacturing and material costs.
[0071] Furthermore, in some preferred embodiments of the present invention, the threshold voltage abrupt change at the interface between the source and drain dielectric regions due to the difference in dielectric constant and work function causes at least two electric field peaks in the channel's lateral electric field distribution. This "double electric field peak" is the core physical effect of this structure. It demonstrates that the structure of the present invention is not a simple material assembly, but rather generates a novel physical synergistic effect. The double-peak distribution allows charge carriers at multiple locations in the channel to accelerate to saturation velocity at the electric field peaks, rewriting the electric field distribution state of traditional LDMOS and achieving a breakthrough balance between reducing on-resistance and increasing breakdown voltage.
[0072] Reference Figures 2 to 8 A method for fabricating an LDMOS device with a lateral hybrid gate structure as described in the first aspect of the present invention, according to a second aspect of the present invention, includes the following steps:
[0073] S1: Provide a substrate 101, form a dummy gate structure on the surface of the substrate 101, and perform ion implantation and high-temperature annealing in the substrate on both sides of the dummy gate to form an N-type drift region 102, a P-type body region 103, a source region 104c and a drain region 104a.
[0074] S2: Remove the dummy gate structure to expose the gate trench;
[0075] S3: A second dielectric constant material layer is formed at the bottom of the gate trench as an interface layer, and a first dielectric constant material layer is deposited at low temperature on the interface layer to cover the entire channel region. The dielectric constant of the first dielectric constant material is greater than that of the second dielectric material.
[0076] S4: Coat the surface of the first dielectric constant material layer with photoresist, retain only the photoresist above the source region through photolithography, and completely etch away the first dielectric constant material layer in the drain region.
[0077] S5: Fill the gate trench in the drain region with a second dielectric constant material to form a gate dielectric layer 108 containing a source first dielectric constant material and a drain second dielectric constant material;
[0078] S6: Deposit a gate conductive layer 109 on the gate dielectric layer 108, and form conductive materials with different work functions above the source dielectric region and the drain dielectric region, respectively.
[0079] This fabrication method completely separates the high-temperature process (annealing) from the low-temperature process (high-K dielectric deposition) through a dummy gate process, thus protecting the physical properties of the high-K material. Furthermore, this invention requires only one additional photomask (used in S4 to protect the source end) to complete the lateral mosaicking of high-K / low-K materials. Compared to traditional multilayer field boards, this invention reduces manufacturing costs while maintaining electrical performance.
[0080] As a further improvement to the above scheme, in step S3, the low-temperature deposition is an atomic layer deposition process, and before depositing the first dielectric constant material layer, an in-situ water vapor generation process (ISSG) is used to grow a silicon dioxide interface layer with a thickness of 0.5~1.5 nm at the bottom of the gate trench.
[0081] Without this thin oxide layer of ISSG (In-situ Water Vapor Generation Process), Direct growth on silicon (Si) substrates can lead to severe lattice mismatch and surface dangling bond defects, affecting carrier mobility. ISSG oxide layers have extremely high density and uniformity, which can perfectly repair the substrate surface and play an "interface passivation" role. This results in extremely low gate dielectric interface trap density, which significantly improves device reliability and channel carrier mobility.
[0082] As a further improvement to the above scheme, in step S4, a combination of dry etching and wet etching is used to remove the first dielectric constant material layer in the drain region; in step S5, atomic layer deposition (ALD) is used to fill the second dielectric constant material.
[0083] Dry etching is used to precisely define the removal area, while wet etching can perfectly remove residual polymer and surface damage from dry etching, ensuring an extremely smooth step sidewall at the interface between the two media; subsequently, the ALD process is used to fill the gap. It can achieve "perfect conformal filling" with extremely small feature size, leaving no voids or gaps, avoiding electrical leakage weak points at the stepped gate dielectric, and ensuring that the device has extremely high withstand voltage insulation performance.
[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0085] Of course, the present invention is not limited to the above-described embodiments. Those skilled in the art can make equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.
Claims
1. An LDMOS device with a lateral hybrid gate structure, characterized in that, include: Substrate (101); An N-type drift region (102) and a P-type body region (103) are formed on the substrate (101). A drain region (104a) is disposed on the surface of the N-type drift region (102), and a source region (104c) is disposed on the surface of the P-type body region (103). The drain region (104a) is used to lead out the drain electrode (105), and the source region (104c) is used to lead out the source electrode (106). A gate structure is provided across the N-type drift region (102) and the P-type body region (103). The gate structure includes a gate dielectric layer (108), a gate conductive layer (109), a sidewall (107), and a gate lead (111). The gate conductive layer (109) is located on the gate dielectric layer (108), the sidewall (107) is located on the sidewall of the gate structure, and the gate lead (111) is located above the gate conductive layer (109). The gate dielectric layer (108) is divided into a source dielectric region and a drain dielectric region along the channel direction; the material of the source dielectric region is a layer of second dielectric constant material plus a layer of first dielectric constant material, and the material of the drain dielectric region is the second dielectric constant material, and the first dielectric constant is greater than the second dielectric constant. The physical thickness of the source-end dielectric region is greater than the physical thickness of the drain-end dielectric region, and the equivalent oxide layer thickness of the source-end dielectric region is less than the equivalent oxide layer thickness of the drain-end dielectric region. The gate conductive layer (109) located above the source dielectric region has a different work function than the gate conductive layer (109) located above the drain dielectric region, and the work function of the gate conductive layer (109) above the source dielectric region is smaller than the work function of the gate conductive layer (109) above the drain dielectric region.
2. The LDMOS device with a lateral hybrid gate structure according to claim 1, characterized in that, The first dielectric constant material is hafnium dioxide, and the second dielectric constant material is silicon dioxide.
3. The LDMOS device with a lateral hybrid gate structure according to claim 1, characterized in that, The physical thickness of the source-end dielectric region is 2~5 nm, and the physical thickness of the drain-end dielectric region is 1~2.5 nm.
4. The LDMOS device with a lateral hybrid gate structure according to claim 1, characterized in that, The boundary between the source dielectric region and the drain dielectric region is located in the middle region of the channel along the current direction, and is biased towards one side of the source region (104c).
5. An LDMOS device with a lateral hybrid gate structure according to claim 1, characterized in that, The gate conductive layer (109) located above the source dielectric region is titanium nitride, and the gate conductive layer (109) located above the drain dielectric region is tantalum nitride.
6. An LDMOS device with a lateral hybrid gate structure according to claim 1, characterized in that, The threshold voltage abrupt change at the interface between the source dielectric region and the drain dielectric region due to the difference in dielectric constant and work function causes at least two electric field peaks to form in the transverse electric field distribution of the channel.
7. An LDMOS device with a lateral hybrid gate structure according to claim 1, characterized in that, The gate conductive layer (109) is a polysilicon layer. The polysilicon layer above the source dielectric region has a first doping type and a first doping concentration. The polysilicon layer above the drain dielectric region has a second doping type and a second doping concentration. The first doping type is different from the second doping type, and / or the first doping concentration is different from the second doping concentration, so that their work functions are different.
8. A method for fabricating an LDMOS device with a lateral hybrid gate structure according to any one of claims 1 to 7, characterized in that, Includes the following steps: S1: Provide a substrate (101), form a dummy gate structure on the surface of the substrate (101), and perform ion implantation and high-temperature annealing in the substrate on both sides of the dummy gate to form the N-type drift region (102), the P-type body region (103), the source region (104c) and the drain region (104a). S2: Remove the dummy gate structure to expose the gate trench; S3: A second dielectric constant material layer is formed at the bottom of the gate trench as an interface layer, and a first dielectric constant material layer is deposited at low temperature on the interface layer to cover the entire channel region. The dielectric constant of the first dielectric constant material is greater than the dielectric constant of the second dielectric material. S4: Coat the surface of the first dielectric constant material layer with photoresist, retain only the photoresist above the source region through photolithography, and completely etch away the first dielectric constant material layer in the drain region. S5: Fill the gate trench in the drain region with a second dielectric constant material to form the gate dielectric layer (108) containing the source first dielectric constant material and the drain second dielectric constant material. S6: Deposit the gate conductive layer (109) on the gate dielectric layer (108), and form conductive materials with different work functions above the source dielectric region and the drain dielectric region, respectively.
9. The method for fabricating an LDMOS device according to claim 8, characterized in that, In step S3, the low-temperature deposition is an atomic layer deposition process, and before depositing the first dielectric constant material layer, an in-situ water vapor generation process is used to grow a silicon dioxide interface layer with a thickness of 0.5~1.5 nm at the bottom of the gate trench.
10. A method for fabricating an LDMOS device according to claim 8, characterized in that, In step S4, a combination of dry and wet etching processes is used to remove the first dielectric constant material layer in the drain region; in step S5, an atomic layer deposition process is used to fill the second dielectric constant material.