SiC ldmos device and preparation method thereof

Abstract

The application discloses a SiC LDMOS device and a preparation method thereof. The SiC LDMOS device comprises a substrate, a doped region, a gate structure, a first source region, a second source region, a channel layer and a second source. The doping type of the substrate is different from the doping type of the doped region and the epitaxial layer. The gate structure is located on the surface of the doped region away from the substrate. The gate structure is in contact with the side surface of the epitaxial layer and the doped region. The gate structure comprises a first source, a gate and an oxide layer. The gate and the first source are separated by the oxide layer. The first source region is located on the side of the gate structure close to the epitaxial layer. The second source region is located on the side of the gate structure close to the substrate. The channel layer is located on the surface of the side of the gate structure close to the substrate. The first source and the second source are electrically connected. In the field of semiconductor device manufacturing, the application mainly solves the problems of high loss and bipolar degradation and high switching loss caused by poor reverse recovery performance of the body diode in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a SiC LDMOS device and its fabrication method. Background Technology

[0002] In the field of semiconductor device manufacturing, silicon carbide (SiC) lateral double-diffused metal-oxide-semiconductor (LDMOS) is a key basic device in the core electronics industry, widely used in high-voltage integrated circuits due to its advantages such as high gain and easy integration. However, traditional SiC LDMOS suffers from problems such as poor reverse recovery performance of the internal parasitic diode, large on-state voltage drop, and bipolar degradation.

[0003] Existing improvement solutions are mostly based on the SiC vertical double-diffused metal-oxide-semiconductor (VDMOS) structure, but they have the following drawbacks: First, the integrated Schottky diode process is complex and has poor high-temperature stability; second, the integrated accumulation channel diode is susceptible to the high drain electric field, posing a punch-through risk; and third, the dual-gate separation design has extremely high requirements for gate oxide thickness control, which can easily lead to structural failure. Furthermore, these solutions often struggle to balance the device's conduction capability, blocking capability, and switching losses, lacking high-performance improvement solutions specifically for SiC DMOS.

[0004] In summary, existing SiC LDMOS devices suffer from poor reverse recovery performance of the bulk parasitic diode, large on-state voltage drop, and severe bipolar degradation. Furthermore, existing SiC VDMOS-based improvement schemes suffer from complex fabrication processes, poor high-temperature stability, susceptibility to punch-through risks due to high drain electric fields, and difficulties in gate oxide control. Therefore, a SiC LDMOS device that can overcome these problems is urgently needed. Summary of the Invention

[0005] This application provides a SiC LDMOS device and its fabrication method to solve the problems of high loss, bipolar degradation, and high switching loss caused by poor reverse recovery performance of the body diode in the prior art.

[0006] According to one aspect of this application, a SiC LDMOS device is provided, comprising:

[0007] A substrate, comprising a substrate and an epitaxial layer, wherein the epitaxial layer is located on one side of the surface of the substrate;

[0008] A doped region is located on one side of the surface of the substrate. The doped region and the epitaxial layer are disposed adjacent to each other. The doping type of the substrate is different from the doping type of the doped region, and the doping type of the substrate is different from the doping type of the epitaxial layer.

[0009] A gate structure is located on the surface of the doped region away from the substrate. The surface of the gate structure near the epitaxial layer is in contact with the doped region. The gate structure includes a first source, a gate, and an oxide layer. The oxide layer is spaced between the gate and the first source. The gate is located on the side of the first source away from the substrate.

[0010] The first source region is located on the surface of the gate structure near the epitaxial layer;

[0011] The second source region is located on the surface of the gate structure on the side closest to the substrate;

[0012] The channel layer is located on the surface of the gate structure near the substrate;

[0013] The second source is located on the side of the first source region, the second source region, and the gate structure away from the substrate, and the first source and the second source are electrically connected.

[0014] Optionally, the SiC LDMOS device further includes: a shielding region located on the surface of the first source region near the epitaxial layer, the shielding region being in contact with a portion of the second source electrode, and the doping type of the shielding region being different from the doping type of the doped region.

[0015] Optionally, the material of the first source electrode is polycrystalline silicon, and the material of the second source electrode is metal.

[0016] Optionally, the first source region includes a first implantation region, a second implantation region, and a third implantation region. The second implantation region and the third implantation region are located on the side of the first implantation region away from the substrate. The second implantation region is located on the side of the third implantation region closer to the epitaxial layer. The doping type of the second implantation region is different from that of the third implantation region. The second source region includes a fourth implantation region, a fifth implantation region, and a sixth implantation region. The fifth implantation region is located on the surface of the sixth implantation region away from the channel layer. The fourth implantation region is located on the side of the fifth implantation region, the sixth implantation region, and the channel layer closer to the substrate. The doping type of the fifth implantation region is different from that of the sixth implantation region.

[0017] Optionally, the surface of the shielding region near the substrate and the first surface have a first distance, the surface of the first source region near the substrate and the first surface have a second distance, the first surface is the surface of the doped region away from the substrate, and the first distance is greater than the second distance.

[0018] Optionally, the doping type of the fourth implantation region is different from that of the sixth implantation region, the doping type of the fourth implantation region is different from that of the channel layer, and the doping concentration of the channel layer is greater than that of the doping region, while the doping concentration of the channel layer is less than that of the sixth implantation region.

[0019] Optionally, the channel layer satisfies at least one of the following: the thickness of the channel layer is in the range of 0.1 μm to 0.3 μm; the width of the channel layer is in the range of 0.3 μm to 0.5 μm.

[0020] According to one aspect of this application, a method for fabricating a SiC LDMOS device is provided, the method comprising the following steps:

[0021] A substrate is provided, the substrate comprising a substrate and an epitaxial layer, the epitaxial layer being located on a surface of one side of the substrate;

[0022] A doped region is formed on one side of the surface of the substrate, the doped region and the epitaxial layer are disposed adjacent to each other, the doping type of the substrate is different from the doping type of the doped region, and the doping type of the substrate is different from the doping type of the epitaxial layer;

[0023] A first source region extending inward along a first surface and a second source region extending inward along a second surface are formed in the doped region. A channel layer extending inward along the second surface is formed in the second source region. The first surface and the second surface are respectively the side surfaces of the doped region facing away from the substrate. The vertical distance between the first surface and the substrate is greater than the vertical distance between the second surface and the substrate.

[0024] A gate structure is formed on the second surface, the side surface of the gate structure near the epitaxial layer is in contact with the doped region, the gate structure includes a first source, a gate and an oxide layer, the oxide layer is spaced between the gate and the first source, and the gate is located on the side of the first source away from the substrate;

[0025] A second source electrode is formed in the first source region, the second source region, and the side of the gate structure facing away from the substrate, and the first source electrode and the second source electrode are electrically connected.

[0026] Optionally, ion implantation is performed on the first surface to form a first pre-implantation region, which is in contact with the shielding region. Ion implantation is performed on the side of the first pre-implantation region facing away from the substrate to form a second implantation region and a second pre-implantation region. A portion of the first pre-implantation region, a portion of the second pre-implantation region, and a portion of the doped region are removed to expose the second surface. The remaining first pre-implantation region is the first implantation region, and the remaining second pre-implantation region is the third implantation region. The second implantation region is located on the side of the third implantation region closer to the epitaxial layer. The first implantation region, the second implantation region, and the third implantation region constitute the first source region. The doping type of the second implantation region is different from that of the third implantation region. Ion implantation is performed on the second surface to form a fourth implantation region. Ion implantation is performed on the side of the fourth implantation region facing away from the substrate to form a fifth implantation region and a sixth implantation region. The fifth implantation region is located on the side of the sixth implantation region facing away from the epitaxial layer. The doping type of the fifth implantation region is different from that of the sixth implantation region. The fourth implantation region, the fifth implantation region, and the sixth implantation region constitute the second source region.

[0027] Optionally, the step of forming the gate structure includes: forming a preliminary oxide layer on the second surface, wherein the preliminary oxide layer is in contact with the doped region on one side surface near the epitaxial layer; removing a portion of the preliminary oxide layer to form a trench; sequentially forming a first source, a first oxide layer, the gate, and a second oxide layer in the trench; removing a portion of the preliminary oxide layer, wherein the remaining preliminary oxide layer, the first oxide layer, and the second oxide layer constitute the oxide layer, and the oxide layer, the first source, and the gate constitute the gate structure.

[0028] According to this application, a doped region is formed on one side of the substrate surface in a SiC LDMOS device. The doped region and the epitaxial layer are disposed adjacent to each other. The doping type of the substrate is different from the doping type of the doped region and the doping type of the epitaxial layer. The gate structure is located on the surface of the doped region away from the substrate. The surface of the gate structure near the epitaxial layer is in contact with the doped region. The gate structure includes a first source, a gate, and an oxide layer. The gate and the first source are located in the oxide layer. The gate is located on the side of the first source away from the substrate. The first source region is located on the surface of the gate structure near the epitaxial layer. The second source region is located on the surface of the gate structure near the substrate. The channel layer is located on the surface of the gate structure near the substrate. The second source is located on the side of the first source region, the second source region, and the gate structure away from the substrate. The first source and the second source are electrically connected. A MOS channel diode is integrated through a first source, a second source region, and a channel layer. In the forward conduction and breakdown voltage states, the PN junction formed by the channel layer and the adjacent second source region is in a fully depleted state. The energy band bending caused by the electric field in the depletion region forms the lowest conduction band energy point at the interface between the channel layer and the oxide layer, thereby constructing an electron barrier and suppressing the punch-through effect between the second source region and the epitaxial layer, ensuring that the integrated diode is in the off state to maintain high blocking capability. In the reverse conduction state, by applying a forward bias voltage to the first and second sources, the electron barrier height in the channel layer is much lower than that of the conventional PN junction barrier, thus providing a low-resistance channel for electrons to transport from the epitaxial layer to the heavily doped region in the second source region, prompting the integrated diode to turn on earlier. This significantly reduces the turn-on voltage and conduction voltage, reduces power loss, avoids the bipolar degradation effect caused by electron-hole recombination when the traditional SiC PN bulk diode is turned on, and improves reverse recovery performance. Meanwhile, the device in this application adopts a split gate design, that is, there is an oxide layer between the first source and the gate, with the gate located on top and the first source located on the bottom, and the two are isolated by a thick oxide layer. This vertical separation reduces the capacitance between the gate and drain, shortens the charging and discharging time of the device during the switching process, thereby improving the switching speed and reducing the switching loss. It solves the problems of large on-resistance, high switching loss and bipolar degradation of the body diode in the existing SiC LDMOS technology, and significantly improves the overall energy efficiency and reliability of the device. Attached Figure Description

[0029] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0030] Figure 1 This is a cross-sectional schematic diagram of a SiC LDMOS device provided according to an embodiment of this application;

[0031] Figure 2This is a schematic flowchart of a method for fabricating a SiC LDMOS device according to an embodiment of this application;

[0032] Figure 3 This illustration shows a cross-sectional view of the substrate provided in a method for fabricating a SiC LDMOS device according to an embodiment of this application.

[0033] Figure 4 It shows in Figure 3 A schematic cross-sectional view of the substrate after the formation of doped regions in the epitaxial layer;

[0034] Figure 5 It shows in Figure 4 A cross-sectional schematic diagram of the substrate after the formation of a shielding region, a first pre-implantation region, and a second implantation region in the doped region;

[0035] Figure 6 It shows in Figure 5 A cross-sectional schematic diagram of the matrix after the second pre-injection zone is formed in the first pre-injection zone;

[0036] Figure 7 It shows in Figure 6 A cross-sectional schematic diagram of the substrate after the first and third implantation regions are formed in the doped region;

[0037] Figure 8 It shows in Figure 7 A cross-sectional schematic diagram of the substrate after the fourth and fifth implantation regions are formed in the doped region;

[0038] Figure 9 It shows in Figure 8 A cross-sectional schematic diagram of the matrix after the formation of the sixth injection zone and the channel layer in the fourth injection zone;

[0039] Figure 10 It shows in Figure 9 A schematic cross-sectional view of the substrate after a pre-oxide layer is formed on the surface of the doped region;

[0040] Figure 11 It shows in Figure 10 A cross-sectional schematic diagram of the substrate after the first source electrode is formed in the pre-oxide layer;

[0041] Figure 12 It shows in Figure 11 A cross-sectional schematic diagram of the substrate after the first oxide layer is formed in the pre-oxide layer;

[0042] Figure 13 It shows in Figure 12 A cross-sectional schematic diagram of the substrate after the gate is formed in the pre-oxide layer;

[0043] Figure 14 It shows in Figure 13 A cross-sectional schematic diagram of the substrate after the second oxide layer is formed on the surface of the pre-oxide layer;

[0044] Figure 15 It shows in Figure 14 A cross-sectional view of the substrate after the doped region is formed into a gate structure.

[0045] 10. Substrate; 110. Substrate; 120. Epitaxial layer; 20. Doped region; 30. Shielding region; 40. First source region; 401. First implantation region; 402. Second implantation region; 403. Third implantation region; 410. First pre-implantation region; 420. Second pre-implantation region; 50. Second source region; 501. Fourth implantation region; 502. Fifth implantation region; 503. Sixth implantation region; 60. Gate structure; 601. First source; 602. Gate; 603. Oxide layer; 610. Pre-oxide layer; 620. First oxide layer; 630. Second oxide layer; 70. Second source; 80. Channel layer; 901. First drain; 902. Second drain. Detailed Implementation

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0050] According to embodiments of this application, a SiC LDMOS device is provided, such as... Figure 1 As shown, it includes:

[0051] The substrate 10 includes a substrate 110 and an epitaxial layer 120, wherein the epitaxial layer 120 is located on one side of the surface of the substrate 110;

[0052] The doped region 20 is located on one side of the surface of the substrate 110. The doped region 20 and the epitaxial layer 120 are disposed adjacent to each other. The doping type of the substrate 110 is different from the doping type of the doped region 20, and the doping type of the substrate 110 is different from the doping type of the epitaxial layer 120.

[0053] The gate structure 60 is located on the surface of the doped region 20 away from the substrate 110. The surface of the gate structure 60 near the epitaxial layer 120 is in contact with the doped region 20. The gate structure 60 includes a first source 601, a gate 602 and an oxide layer 603. The oxide layer 603 is spaced between the gate 602 and the first source 601. The gate 602 is located on the side of the first source 601 away from the substrate 110.

[0054] The first source region 40 is located on the surface of the gate structure 60 near the epitaxial layer 120;

[0055] The second source region 50 is located on the surface of the gate structure 60 near the substrate 110;

[0056] The channel layer 80 is located on the surface of the gate structure 60 near the substrate 110;

[0057] The second source 70 is located on the side of the first source region 40, the second source region 50 and the gate structure 60 away from the substrate 110, and the first source 601 and the second source 70 are electrically connected.

[0058] In this embodiment, a doped region 20 is formed on one side of the substrate 110 in the SiC LDMOS device. The doped region 20 and the epitaxial layer 120 are disposed adjacent to each other. The doping type of the substrate 110 is different from that of the doped region 20, and the doping type of the substrate 110 is different from that of the epitaxial layer 120. The gate structure 60 is located on the side of the doped region 20 facing away from the substrate 110. The side of the gate structure 60 closest to the epitaxial layer 120 is in contact with the doped region 20. The gate structure 60 includes a first source 601, a gate 602, and an oxide layer 603. The gate 602... The first source 601 is located in the oxide layer 603, and the gate 602 is located on the side of the first source 601 away from the substrate 110; the first source region 40 is located on the surface of the gate structure 60 near the epitaxial layer 120, the second source region 50 is located on the surface of the gate structure 60 near the substrate 110, the channel layer 80 is located on the surface of the gate structure 60 near the substrate 110, and the second source 70 is located on the side of the first source region 40, the second source region 50 and the gate structure 60 away from the substrate 110. The first source 601 and the second source 70 are electrically connected. A MOS channel diode is integrated through a first source 601, a second source region 50, and a channel layer 80. In the forward conduction and breakdown voltage states, the PN junction formed by the channel layer 80 and the adjacent second source region 50 is in a fully depleted state. The band bending caused by the electric field in the depletion region forms the lowest conduction band energy point at the interface between the channel layer 80 and the oxide layer 603, thereby constructing an electron barrier and suppressing the punch-through effect between the second source region 50 and the epitaxial layer 120, ensuring the integrated diode is in the off state to maintain high blocking capability. In the reverse conduction state, by applying a forward bias voltage to the first source 601 and the second source 70, the electron barrier height within the channel layer 80 is much lower than that of a conventional PN junction, thus providing a low-resistance channel for electron transport from the epitaxial layer 120 to the heavily doped region 20 in the second source region 50. This causes the integrated diode to turn on earlier, significantly reducing the turn-on voltage and conduction voltage, reducing power loss, and avoiding the drawbacks of traditional SiC diodes. The bipolar degradation effect caused by electron-hole recombination during PN body diode conduction improves reverse recovery performance. Furthermore, the device in this application employs a split-gate design, with an oxide layer 603 separating the first source 601 and the gate 602. The gate is located above, and the first source 601 is located below, isolated by the oxide layer 603. This vertical separation reduces the gate-drain capacitance, shortens the charging and discharging time during switching, thereby increasing switching speed and reducing switching losses. This solves the problems of high on-resistance, high switching losses, and bipolar degradation in the body diode in existing SiC LDMOS technology, significantly improving the overall energy efficiency and reliability of the device.

[0059] In this embodiment, the substrate 10 can be made of silicon carbide, which allows the device to have high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices that can operate under high temperature and high pressure environments. Figure 1 As shown, the substrate 10 includes a substrate 110 and an epitaxial layer 120.

[0060] In this embodiment, the polysilicon within the gate trench is divided into upper and lower parts, separated by a thick oxide layer 603. The upper part forms the polysilicon gate 602, controlling the switching on and off of the MOSFET channel, while the lower part forms the first source 601, controlling the switching on and off of the integrated MOSFET channel diode. This physical isolation of the upper and lower gate structures by the oxide layer 603 significantly reduces the coupling capacitance between the gate structure 60 and the drain region. This reduction in gate-drain capacitance improves the switching speed of the device, thereby reducing switching losses. Therefore, this gate structure 60 reduces parasitic capacitance through spatial isolation, thereby reducing energy loss during switching.

[0061] In this embodiment, the channel layer 80 beneath the first source 601 provides a low-barrier path for electrons to transport from the epitaxial layer 120 to the second source region 50. In the reverse conduction state, the electron barrier height within the channel layer 80 is significantly lower than that of the SiCPN junction, enabling the integrated MOS channel diode to turn on earlier. This low-barrier path results in low turn-on and turn-off voltages during reverse conduction, thereby reducing power loss. Simultaneously, single-carrier conduction via the channel layer 80 avoids the bipolar degradation problem caused by electron-hole recombination during the conduction process of a traditional SiC PN body diode.

[0062] In this embodiment, by connecting the first source 601 and the second source 70 in a circuit, this electrical connection ensures that the first source 601 can be applied with the correct bias voltage during reverse conduction, thereby opening the low barrier path formed by the channel layer 80 and realizing the function of the MOS channel diode, avoiding the diode failing to turn on or malfunctioning due to inconsistent potential.

[0063] In some alternative implementations, the SiC LDMOS device further includes: a shielding region 30 located on the surface of the first source region 40 near the epitaxial layer 120, the shielding region 30 being in contact with a portion of the second source 70, and the doping type of the shielding region 30 being different from that of the doped region 20.

[0064] In the above optional embodiments, the shielding region 30 is typically located in a high electric field region. By connecting it to the second source 70, it can modulate the electric field distribution of the drift region, preventing the high drain voltage from directly acting on the oxide layer 603, thereby protecting the gate oxide from breakdown. Simultaneously, since there is a certain coupling capacitance between the shielding region 30 and the gate structure 60, when the shielding region 30 is connected to the metal source, it can bypass part of the gate signal, or reduce the influence of drain voltage changes on the gate voltage through electrostatic shielding, thus reducing the effective gate-drain capacitance. The reduction in gate-drain capacitance directly reduces the Miller effect, improves the switching speed of the device, and consequently reduces energy loss during the switching process.

[0065] In some alternative implementations, the first source 601 is made of polycrystalline silicon, and the second source 70 is made of metal.

[0066] In the above optional embodiments, the first source 601 and gate, made of polysilicon, are located inside the trench, while the second source 70, made of metal, is located on the device surface. The first source 601, made of polysilicon, can serve as the gate control terminal of the integrated MOS channel diode. Simultaneously, by electrically connecting it to the second source 70, made of metal, it avoids the diode failing to turn on or malfunctioning due to potential inconsistency. Furthermore, the first source 601, made of polysilicon, is physically isolated from the polysilicon gate 602 by an oxide layer 603, forming a "separated gate" structure. This reduces gate-drain capacitance, improves device switching speed, and reduces device switching losses.

[0067] Specifically, the material of the second source electrode 70 includes metals and / or metal compounds, such as nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc., and metal compounds such as TiSi2 (titanium silicide), CoSi2 (cobalt silicide), etc. The embodiments of this application do not specifically limit the material.

[0068] In some optional embodiments, the first source region 40 includes a first implantation region 401, a second implantation region 402, and a third implantation region 403. The second implantation region 402 and the third implantation region 403 are located on the side of the first implantation region 401 away from the substrate 110. The second implantation region 402 is located on the side of the third implantation region 403 near the epitaxial layer 120. The doping type of the second implantation region 402 is different from that of the third implantation region 403. The second source region 50 includes a fourth implantation region 501, a fifth implantation region 502, and a sixth implantation region 503. The fifth implantation region 502 is located on the surface of the sixth implantation region 503 away from the channel layer 80. The fourth implantation region 501 is located on the side of the fifth implantation region 502, the sixth implantation region 503, and the channel layer 80 near the substrate 110. The doping type of the fifth implantation region 502 is different from that of the sixth implantation region.

[0069] In the above optional embodiments, the first implantation region 401 and the second implantation region 402 can be first type doped regions, having N-type doping or P-type doping; the third implantation region 403 can be second type doped region 20, having P-type doping or N-type doping; the fourth implantation region 501 and the fifth implantation region 502 can be first type doped regions, having N-type doping or P-type doping; and the sixth implantation region 503 can be second type doped region, having P-type doping or N-type doping. For example, the first type doped region has N-type doping, and the second type doped region has P-type doping, or the first type doped region has P-type doping, and the second type doped region has N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb); the P-type doping element is any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). This application does not specifically limit the specific doping elements.

[0070] In the above optional embodiments, the doping concentration of the first implantation region 401 is lower than that of the second implantation region 402 and the third implantation region 403, and the doping concentration of the fourth implantation region 501 is lower than that of the fifth implantation region 502 and the sixth implantation region 503. The lower doping concentrations of the first and fourth implantation regions 401 and 501 help to form a wider depletion layer during reverse blocking, thereby withstanding higher voltages and improving the device's breakdown voltage capability. Meanwhile, the higher doping concentrations of the third and sixth implantation regions 403 and the second and fifth implantation regions 502 allow these high-concentration regions to form good ohmic contacts when in contact with the second source 70, significantly reducing contact resistance. Furthermore, the high doping concentration of the sixth implantation region 503 helps to lower the potential barrier. Through this combination of low-concentration bulk regions and high-concentration source regions 20, the device ensures safe operation under high voltages while maintaining low on-resistance during conduction, thereby optimizing the overall electric field distribution and improving performance.

[0071] Specifically, the combination of the first injection region 401 with the second injection region 402 and the third injection region 403 optimizes the electric field distribution of the right source region. The first injection region 401 is located at the bottom to support the depletion layer to improve the withstand voltage, and the third injection region 403 serves as an electron channel to reduce the contact resistance. The combination of the fourth injection region 501, the fifth injection region 502 and the sixth injection region 503 optimizes the left source region. The sixth injection region 503 works with the channel layer 80 to provide a low barrier path, ensuring that majority carriers are transported during reverse conduction to avoid bipolar degradation.

[0072] In some alternative embodiments, the surface of the shielding region 30 near the substrate 110 has a first distance from the first surface, and the surface of the first source region 40 near the substrate 110 has a second distance from the first surface. The first surface is the surface of the doped region 20 away from the substrate 110, and the first distance is greater than the second distance.

[0073] In the above optional embodiments, the first distance is greater than the second distance, that is, the thickness of the shielding region 30 is greater than the thickness of the first source region 40. The shielding region 30 is closer to the substrate 110 than the source region, which can modulate the electric field distribution inside the device and shield the effect of high voltage from the drain on the oxide layer 603. When a high voltage is applied to the drain, the high electric field is mainly distributed in the drift region. The shielding region 30 is located close to the substrate 110, which can form a potential barrier or depletion region, removing the high electric field from the fragile oxide layer 603 and preventing gate oxide breakdown. By making the first distance greater than the second distance, the shielding region 30 can more effectively cover and shield the electric field at the bottom of the drift region, thereby protecting the gate structure 60 and ensuring stable operation of the device under high voltage.

[0074] In some alternative implementations, the doping type of the fourth implantation region 501 is different from that of the sixth implantation region 503, the doping type of the fourth implantation region 501 is different from that of the channel layer 80, and the doping concentration of the channel layer 80 is greater than that of the doping region 20, while the doping concentration of the channel layer 80 is less than that of the sixth implantation region 503.

[0075] In the above optional embodiments, the fourth injection region 501 differs from the sixth injection region 503 and the channel layer 80 in type, forming the necessary PN junction and N-type channel. The doping concentration of the channel layer 80 is higher than that of the doped region 20, which helps to form favorable band bending at the channel interface, reducing the electron injection barrier and thus lowering the turn-on voltage of the MOS channel diode. Simultaneously, the concentration of the channel layer 80 is much lower than that of the sixth injection region 503, ensuring that the source contact region has low-resistance ohmic contact characteristics.

[0076] Specifically, this concentration distribution allows the device to conduct electricity primarily through the channel formed by the P-type body region during forward conduction, while during reverse conduction, it conducts electricity through the low barrier path formed by the channel layer 80 and the heavily doped sixth implantation region 503. This avoids the high voltage drop and bipolar degradation of traditional body diodes, achieving high-performance asymmetric conduction characteristics.

[0077] In some alternative embodiments, the channel layer 80 satisfies at least one of the following: the thickness of the channel layer 80 is in the range of 0.1 μm to 0.3 μm; the width of the channel layer 80 is in the range of 0.3 μm to 0.5 μm.

[0078] In the above optional embodiments, a thickness in the range of 0.1~0.3 μm helps to form a suitable depletion layer width under reverse bias, ensuring sufficient band bending, thereby providing a low-barrier path during reverse conduction and reducing the turn-on voltage. A width in the range of 0.3~0.5 μm, combined with the doping concentration of the N-type channel layer 80, ensures that the channel region can effectively control the transport of electrons from the epitaxial layer 120 to the heavily doped region in the second source region 50. An appropriate width helps to ensure reverse conduction current capability while avoiding punch-through effect during forward blocking, i.e., preventing direct connection between the depletion region in the left source region and the bottom of the channel layer 80, which would lead to a drop in breakdown voltage. By limiting the width and thickness of the channel layer 80 within a specific range, the device can achieve low loss during reverse conduction using a low-barrier path, while maintaining good blocking capability during forward blocking, thus improving overall performance.

[0079] According to embodiments of this application, a method for fabricating a SiC LDMOS device is provided, used to fabricate the SiC LDMOS device described in the above embodiments, such as... Figure 2 As shown, the preparation method includes:

[0080] Step S1, providing a substrate, the substrate including a substrate and an epitaxial layer, the epitaxial layer being located on one side surface of the substrate;

[0081] Specifically, a substrate is provided, and an epitaxial layer is formed on the substrate using an epitaxial process, wherein the materials of the epitaxial layer and the substrate include silicon carbide. The epitaxial layer serves as a drift region, forming a depletion layer that withstands voltage during reverse bias.

[0082] Step S2: A doped region is formed on one side of the substrate surface. The doped region and the epitaxial layer are arranged adjacent to each other. The doping type of the substrate is different from the doping type of the doped region, and the doping type of the substrate is different from the doping type of the epitaxial layer.

[0083] Specifically, the substrate has a first doping type, and the epitaxial layer and doped regions have a second doping type. The first and second doping types are different. During forward conduction, the doped regions provide more electrons, which helps to reduce the on-resistance.

[0084] Step S3: A first source region extending from the first surface to the interior and a second source region extending from the second surface to the interior are formed in the doped region. A channel layer extending from the second surface to the interior is formed in the second source region. The first surface and the second surface are respectively the side surfaces of the doped region facing away from the substrate. The vertical distance between the first surface and the substrate is greater than the vertical distance between the second surface and the substrate.

[0085] Specifically, the first source region is located to the right of the doped region and is a conventional LDMOS source region. The second source region is located to the left of the doped region, below the first source region, and in contact with the gate structure, thus integrating a MOS channel diode.

[0086] Step S4: A gate structure is formed on the second surface. The side surface of the gate structure closest to the epitaxial layer is in contact with the doped region. The gate structure includes a first source, a gate, and an oxide layer. An oxide layer is spaced between the gate and the first source. The gate is located on the side of the first source away from the substrate.

[0087] Specifically, the gate and the first source are made of polysilicon, with an oxide layer between them to form a split gate structure. The upper part is the polysilicon gate, which controls the turning on and off of the MOSFET channel, and the lower part is the polysilicon source, which controls the turning on and off of the integrated MOS channel diode. The integrated MOS channel diode is a special diode structure that is controlled by the polysilicon source and provides a low-barrier electron channel through the channel layer. Under reverse bias, an electric field is formed between the polysilicon source and the channel layer. The electron barrier formed by the channel layer below the polysilicon source is much lower than the barrier height of the SiC PN junction.

[0088] In step S5, a second source electrode is formed on the side of the first source region, the second source region, and the gate structure away from the substrate, and the first source electrode and the second source electrode are electrically connected.

[0089] Specifically, the second source electrode is made of a metallic material, and the first and second sources are connected to ensure that the potential of the first source electrode is equal to that of the second source electrode, thereby correctly controlling the opening of the channel layer during reverse conduction.

[0090] In this embodiment, an epitaxial layer and a doped region are formed on one side of the substrate. The doped region and the epitaxial layer are disposed adjacent to each other. The doping type of the substrate is different from the doping type of the doped region and the doping type of the epitaxial layer. A first source region extending from the first surface to the interior and a second source region extending from the second surface to the interior are formed in the doped region. A channel layer extending from the second surface to the interior is formed in the second source region. The first surface and the second surface are respectively the side surfaces of the doped region away from the substrate. The vertical distance between the first surface and the substrate is greater than the vertical distance between the second surface and the substrate. A gate structure is formed on the second surface. The side surface of the gate structure closest to the epitaxial layer contacts the doped region. The gate structure includes a first source, a gate, and an oxide layer. An oxide layer is spaced between the gate and the first source. A second source is formed on the side of the first source region, the second source region, and the gate structure away from the substrate. The first source and the second source are electrically connected. A MOS channel diode is integrated through a first source, a second source region, and a channel layer. In the forward conduction and breakdown voltage states, the PN junction formed by the channel layer and the adjacent second source region is in a fully depleted state. The energy band bending caused by the electric field in the depletion region forms the lowest conduction band energy point at the interface between the channel layer and the oxide layer, thereby constructing an electronic barrier to suppress the punch-through effect between the second source region and the epitaxial layer, ensuring that the integrated diode is in the off state to maintain high blocking capability. In the reverse conduction state, by applying a forward bias voltage to the first and second sources, the electronic barrier height in the channel layer is much lower than that of the conventional PN junction barrier, thus providing a low-barrier channel for electrons to transport from the epitaxial layer to the heavily doped region in the second source region, prompting the integrated diode to turn on earlier. This significantly reduces the turn-on voltage and conduction voltage, reduces power loss, avoids the bipolar degradation effect caused by electron-hole recombination when the traditional SiC PN bulk diode is turned on, and improves reverse recovery performance. Meanwhile, the device in this application adopts a split gate design, that is, there is an oxide layer between the first source and the gate, with the gate located on top and the first source located on the bottom, and the two are isolated by a thick oxide layer. This vertical separation reduces the capacitance between the gate and drain, shortens the charging and discharging time of the device during the switching process, thereby improving the switching speed and reducing the switching loss. It solves the problems of large on-resistance, high switching loss and bipolar degradation of the body diode in the existing SiC LDMOS technology, and significantly improves the overall energy efficiency and reliability of the device.

[0091] Exemplary embodiments of the method for fabricating a SiC LDMOS device according to embodiments of this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0092] First, proceed to step S1: as follows Figure 3 As shown, a substrate 10 is provided, which includes a substrate 110 and an epitaxial layer 120, the epitaxial layer 120 being located on one side of the surface of the substrate 110.

[0093] In the above-mentioned optional embodiments, an epitaxial layer 120 is formed on one side of the substrate 110. The epitaxial layer 120 can be formed by low-pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD), and its material can be silicon carbide. The thickness ranges from 3 nm to 10 nm, and the width ranges from 10 nm to 20 nm. The substrate 110 has a first doping type with a doping concentration of 1e16 cm⁻¹. -3 The aforementioned epitaxial layer 120 has a second doping type, with a doping concentration ranging from 3e15cm. -3 up to 2e16cm -3 Between these, the first doping type can be N-type doping or P-type doping, the second doping type can be N-type doping or P-type doping, the N-type doping element can be any one of pentavalent elements including nitrogen (N), phosphorus (P), arsenic (As) and antimony (Sb), and the P-type doping element can be any one of trivalent elements including boron (B), aluminum (Al) and gallium (Ga). The embodiments of this application are not specifically limited.

[0094] Specifically, when the first doping type is P-type doping and the second doping type is N-type doping, a P-type silicon carbide substrate 110 is provided. The doping element of the substrate 110 is aluminum. An epitaxial layer 120 is formed on the substrate 110 through an epitaxial process. An N-type epitaxial layer 120 is formed by implanting nitrogen into the epitaxial layer 120. The N-type epitaxial layer 120 serves as a drift region, and its thickness and doping concentration determine the width of the depletion layer. A thicker epitaxial layer 120 and a lower doping concentration help to extend the depletion layer during reverse blocking, thereby withstanding higher reverse voltages and improving the device's breakdown voltage capability.

[0095] After providing a base including substrate 110 and epitaxial layer 120, step S2 is performed: as follows Figure 4 As shown, a doped region 20 is formed on one side of the surface of the substrate 110. The doped region 20 and the epitaxial layer 120 are arranged adjacent to each other. The doping type of the substrate 110 is different from the doping type of the doped region 20, and the doping type of the substrate 110 is different from the doping type of the epitaxial layer 120.

[0096] In the optional embodiment described above, in an environment with a temperature of 500°C, a doped region 20 with a second doping type is obtained by partial ion implantation on the epitaxial layer 120. Specifically, when the first doping type is P-type doping and the second doping type is N-type doping, ion implantation is continued on the N-type epitaxial layer 120 to obtain an N-type doped region 20. The doping element implanted is nitrogen, and the doping concentration range of the doped region 20 is 1e16cm. -3 up to 8e16cm -3 The doped region 20 is located on one side of the epitaxial layer 120 and is in contact with the substrate 110. During forward conduction, the doped region 20 provides more electrons, which helps to reduce the on-resistance. The doping concentration of the doped region 20 is higher than or close to the doping concentration of the epitaxial layer 120, which helps to suppress the excessive expansion of the depletion region of the PN junction formed by the P-type region in the first source region 40 and the N-type epitaxial layer 120, thereby optimizing the electric field distribution.

[0097] After forming the doped region and before forming the first source region and the second source region, this embodiment further includes the following step: forming a shielding region on the surface of the doped region away from the substrate by ion implantation. The shielding region has a first doping type. Specifically, when the first doping type is p-type doping, the implanted doping element is aluminum, and the doping concentration ranges from 5e17cm. -3 up to 3e18cm -3 The shielding region has a high doping concentration, enabling the formation of a wide depletion region around it. When a high voltage is applied to the drain, the high electric field is mainly distributed in the drift region. The shielding region, through its location and doping characteristics, can modulate the electric field distribution inside the device, removing the high electric field from the oxide layer and preventing gate oxide breakdown, thus protecting the gate structure. The shielding region is typically connected to the source potential; its potential remains relatively stable under varying drain voltages, thereby reducing the coupling capacitance between the gate and drain.

[0098] After providing the doped region 20 and the shielding region, proceed to step S3: as follows Figures 5 to 9 As shown, a first source region 40 extending from the first surface to the interior and a second source region 50 extending from the second surface to the interior are formed in the doped region 20. A channel layer 80 extending from the second surface to the interior is formed in the second source region 50. The first surface and the second surface are respectively the side surfaces of the doped region 20 facing away from the substrate 110. The vertical distance between the first surface and the substrate 110 is greater than the vertical distance between the second surface and the substrate 110.

[0099] In some alternative implementations, the steps of forming the first source region 40 and the second source region 50 include: step S301, as follows: Figure 5 and Figure 6As shown, ion implantation is performed on the first surface to form a first pre-implantation region 410, which is in contact with the shielding region 30. Ion implantation is then performed on the side of the first pre-implantation region 410 facing away from the substrate 110 to form a second implantation region 402 and a second pre-implantation region 420; step S302, as... Figure 7 As shown, a portion of the first pre-implantation region 410, a portion of the second pre-implantation region 420, and a portion of the doped region 20 are removed to expose the second surface. The remaining first pre-implantation region 410 is the first implantation region 401, and the remaining second pre-implantation region 420 is the third implantation region 403. The second implantation region 402 is located on the side of the third implantation region 403 closest to the epitaxial layer 120. The first implantation region 401, the second implantation region 402, and the third implantation region 403 constitute the first source region 40. The doping type of the second implantation region 402 is different from that of the third implantation region 403. Step S303, as follows: Figure 8 and Figure 9 As shown, ion implantation is performed on the second surface to form a fourth implantation region 501. Ion implantation is performed on a portion of the fourth implantation region 501 on the side facing away from the substrate 110 to form a fifth implantation region 502 and a sixth implantation region 503. The fifth implantation region 502 is located on the side of the sixth implantation region 503 facing away from the epitaxial layer 120. The doping type of the fifth implantation region 502 is different from that of the sixth implantation region 503. The fourth implantation region 501, the fifth implantation region 502, and the sixth implantation region 503 constitute the second source region 50.

[0100] In the above optional embodiments, the first injection region 401, the second injection region 402, the fourth injection region 501 and the fifth injection region 502 have a first doping type, the second injection region 402 and the sixth injection region 503 have a second doping type, the second injection region 402 and the third injection region 403 are located within the first injection region 401, and the doping concentration of the second injection region 402 and the third injection region 403 is greater than the doping concentration of the first injection region 401, and the injection depth of the second injection region 402 and the third injection region 403 is less than that of the first injection region 401. By using a trench etching process, a portion of the first pre-implantation region 410, a portion of the second pre-implantation region 420, and a portion of the doped region 20 are removed to expose the second surface. The distance between the second surface and the substrate 110 is less than the distance between the first surface and the substrate 110. Ion implantation is then performed on the second surface to obtain the second source region 50. The fifth implantation region 502 and the sixth implantation region 503 are located within the fourth implantation region 501, and the doping concentration of the second implantation region 402 and the third implantation region 403 is greater than the doping concentration of the first implantation region 401. The implantation depth of the fifth implantation region 502 and the sixth implantation region 503 is less than the implantation depth of the fourth implantation region 501.

[0101] Specifically, taking P-type doping as the first doping type and N-type doping as the second doping type as an example, under an ambient temperature of 500℃, ion implantation is performed on the surface of the N-type doped region 20 facing away from the substrate 110 to form a P-type first implantation region 401. The doping element is aluminum, and the doping concentration ranges from 6e to 16cm. -3 up to 5e17cm -3 Ion implantation is performed on a portion of the surface of the first P-type implantation region 401 to form a second P-type implantation region 402. The doping element is aluminum, and the doping concentration ranges from 1e19cm⁻¹. -3 Up to 1e20cm -3 Ion implantation is performed on another portion of the surface of the P-type first implantation region 401 to form the N-type third implantation region 403. The doping element is nitrogen, and the doping concentration ranges from 1e19cm. -3 Up to 1e20cm -3 After etching, a second surface is formed in the doped region 20. Ion implantation is then performed on a portion of this second surface to form a P-type fourth implantation region 501. The doping element is aluminum, and the doping concentration ranges from 6e to 16cm⁻¹. -3 up to 5e17cm -3 Ion implantation was performed on a portion of the surface of the fourth P-type implantation region 501 to form the fifth P-type implantation region 502. The doping element was aluminum, and the doping concentration ranged from 1e19cm. -3 Up to 1e20cm -3Ion implantation was performed on a portion of the surface of the P-type fourth implantation region 501 to form the N-type sixth implantation region 503. The doping element was nitrogen, and the doping concentration ranged from 1e19cm. -3 Up to 1e20cm -3 By employing a multi-step ion implantation and etching process, implantation regions with specific doping types and locations are formed in different areas of the device, constructing a MOS channel diode structure on the left and a standard source structure on the right, thereby achieving a comprehensive performance improvement in terms of low forward on-resistance, low reverse loss, and high breakdown voltage.

[0102] After forming the first source region 40 and the second source region 50, and before forming the gate structure, this embodiment further includes the following step: ion implantation is performed on the surface of the fourth implantation region 501 facing away from the substrate 110 to form a channel layer 80, wherein the channel layer 80 has a second doping type. Specifically, taking N-type doping as an example, the doping element of the channel layer 80 is nitrogen, and the doping concentration ranges from 2e16cm⁻¹. -3 up to 1e17cm -3 The channel layer 80 has a thickness ranging from 0.1µm to 0.3µm and a width ranging from 0.3µm to 0.5µm. It contacts the sixth implantation region 503, with the channel layer 80 located on the side of the sixth implantation region 503 opposite to the fifth implantation region 502. The channel layer 80 forms a conductive channel without introducing excessive scattering. It contacts the left-side heavily doped N-type region, i.e., the sixth implantation region 503, allowing electrons to flow directly from the N-type epitaxial layer 120 into the sixth implantation region 503 through the N-type channel layer 80 without passing through the high-barrier PN junction. Simultaneously, since the channel layer 80 can be turned on through a MOS channel or accumulation layer, it avoids the forward conduction voltage drop of the PN junction, thereby reducing the reverse conduction voltage drop of the device and significantly reducing power loss.

[0103] After forming the first source region 40, the second source region 50, and the channel layer 80, this embodiment further includes the following steps: placing the above-mentioned SiC LDMOS device in an argon atmosphere for high-temperature annealing to activate the implanted ions and repair lattice damage during the implantation process. The annealing temperature can be between 1600°C and 1800°C, and the time can be between 10 and 40 minutes.

[0104] After forming the first source region 40, the second source region 50, and the channel layer 80, proceed to step S4: as follows Figures 10 to 15 As shown, a gate structure 60 is formed on the second surface. The side surface of the gate structure 60 near the epitaxial layer 120 is in contact with the doped region 20. The gate structure 60 includes a first source 601, a gate, and an oxide layer 603. An oxide layer 603 is spaced between the gate and the first source 601. The gate is located on the side of the first source 601 away from the substrate 110.

[0105] In some alternative embodiments, forming the gate structure 60 includes: step S401, as follows: Figure 10 As shown, a pre-oxide layer 610 is formed on the second surface, and the side surface of the pre-oxide layer 610 near the epitaxial layer 120 contacts the doped region 20; step S402, as... Figures 11 to 14 As shown, a portion of the pre-oxidation layer 610 is removed to form a trench, and a first source 601, a first oxide layer 620, a gate 602, and a second oxide layer 630 are sequentially formed within the trench; step S403, as follows Figure 15 As shown, after removing part of the pre-oxidation layer 610, the remaining pre-oxidation layer 610, the first oxide layer 620 and the second oxide layer 630 constitute the oxide layer 603. The oxide layer 603, the first source 601 and the gate 602 constitute the gate structure 60.

[0106] In the above optional embodiments, a first oxide layer 620 is spaced between the polysilicon first source 601 and the polysilicon gate 602, forming an upper and lower separated gate. The polysilicon gate 602 controls the main MOS channel, and the polysilicon first source 601 controls the integrated MOS channel diode, thereby reducing the influence of the drain high voltage on the gate and reducing the gate-drain capacitance. At the same time, the polysilicon first source 601 serves as the gate of the MOS channel diode. When a voltage is applied, an inversion layer or accumulation layer can be formed in the N-type channel layer 80, providing a low-barrier electron path, reducing the reverse conduction voltage drop, and avoiding bipolar degradation.

[0107] Specifically, the oxide layer 603 can be made of silicon dioxide, the first source 601 and the gate 602 are made of polysilicon, and the doping element of the polysilicon gate is phosphorus (P), with a doping concentration ranging from 1e19cm⁻¹. -3 Up to 1e20cm -3 .

[0108] After the step of forming the above gate structure 60, step S5 is performed: as follows Figure 1 As shown, a second source 70 is formed on the side of the first source region 40, the second source region 50 and the gate structure 60 away from the substrate 110, and the first source 601 and the second source 70 are electrically connected.

[0109] In the above optional embodiments, after forming the gate structure 60, a portion of the surface of the second source region 50 is exposed, and a second source 70 is deposited on the exposed surface. The second source 70 covers the gate structure 60, the first source region 40, and a portion of the shielding region 30. The second source 70 contacts the second injection region 402, the third injection region 403, the fifth injection region 502, and the sixth injection region 503, respectively. For the electron flow provided by the channel layer 80, electrons flow from the epitaxial layer 120 to the sixth injection region 503, and then to the metal second source 70. The metal second source 70, together with the fifth injection region 502 and the sixth injection region 503, constitutes the anode side of the MOS channel diode. When the device is reverse-biased, a voltage needs to be applied to the polysilicon first source 601 to turn on the channel. Since the polysilicon first source 601 is located in the trench and is difficult to connect directly to the outside, it is electrically connected to the metal second source 70. This allows the voltage applied externally to the metal second source 70 to be transmitted to the polysilicon first source 601, thereby controlling the turn-on of the MOS channel diode and providing a control voltage for the integrated MOS channel diode. This ensures that the source impedance is low when the device is forward-biased and the MOS channel diode can turn on as expected when it is reverse-biased, thus optimizing the overall switching characteristics and conduction performance of the device.

[0110] Specifically, the material of the second source electrode 70 is a metallic material, selected from one or more of nickel (Ni), titanium (Ti), platinum (Pt), gold (Au) and tungsten (Wu), but not limited to the above types. This application does not make any specific limitation.

[0111] After forming the second source electrode 70, the embodiments of this application may further include the following steps: such as Figure 1 As shown, a first drain 901 extending into the epitaxial layer 120 is formed therein. The first drain 901 has a second doping type. A second drain 902 is formed on the side of the epitaxial layer 120 facing away from the substrate 110. The second drain 902 is in contact with the first drain 901. The projection of the second drain 902 onto the substrate 110 is a first projection, and the projection of the first drain 901 onto the substrate 110 is a second projection. The first projection is within the second projection. This ensures that current can be effectively collected from the epitaxial layer 120 through the first drain 901 to the metal electrode, reducing contact resistance. At the same time, it limits the second drain 902 from extending beyond the first drain 901, helping to protect the device edges or adjacent areas, preventing accidental short circuits or electric field concentration, and improving the reliability and withstand voltage of the device.

[0112] Specifically, taking N-type doping as an example, the doping element of the first drain 901 is nitrogen, and the doping concentration ranges from 1e19cm. -3 Up to 1e20cm -3The first drain 901 and the third implantation region 403 are fabricated using a unified mask, resulting in the same doping concentration. This simplifies the process and reduces manufacturing costs. Simultaneously, it ensures that the source and drain contact regions have the same low contact resistance characteristics, which is beneficial for high-performance device integration. The second drain 902 is made of a metallic material, selected from one or more of nickel (Ni), titanium (Ti), platinum (Pt), gold (Au), and tungsten (Wu), but is not limited to these types. This application does not impose specific limitations on this material.

[0113] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0114] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A SiC LDMOS device, characterized in that, include: A substrate, comprising a substrate and an epitaxial layer, wherein the epitaxial layer is located on one side of the surface of the substrate; A doped region is located on one side of the surface of the substrate. The doped region and the epitaxial layer are disposed adjacent to each other. The doping type of the substrate is different from the doping type of the doped region, and the doping type of the substrate is different from the doping type of the epitaxial layer. A gate structure is located on the surface of the doped region away from the substrate. The surface of the gate structure near the epitaxial layer is in contact with the doped region. The gate structure includes a first source, a gate, and an oxide layer. The oxide layer is spaced between the gate and the first source. The gate is located on the side of the first source away from the substrate. The first source region is located on the surface of the gate structure near the epitaxial layer; The second source region is located on the surface of the gate structure on the side closest to the substrate; The channel layer is located on the surface of the gate structure near the substrate; The second source is located on the side of the first source region, the second source region, and the gate structure away from the substrate, and the first source and the second source are electrically connected.

2. The SiC LDMOS device according to claim 1, characterized in that, The SiC LDMOS device also includes: A shielding region is located on the surface of the first source region near the epitaxial layer. The shielding region is in contact with a portion of the second source electrode. The doping type of the shielding region is different from that of the doped region.

3. The SiC LDMOS device according to claim 1, characterized in that, The first source electrode is made of polycrystalline silicon, and the second source electrode is made of metal.

4. The SiC LDMOS device according to claim 1, characterized in that, The first source region includes a first implantation region, a second implantation region, and a third implantation region. The second implantation region and the third implantation region are located on the side of the first implantation region away from the substrate. The second implantation region is located on the side of the third implantation region close to the epitaxial layer. The doping types of the second implantation region and the third implantation region are different. The second source region includes a fourth implantation region, a fifth implantation region, and a sixth implantation region. The fifth implantation region is located on the surface of the sixth implantation region away from the channel layer. The fourth implantation region is located on the side of the fifth implantation region, the sixth implantation region, and the channel layer close to the substrate. The doping type of the fifth implantation region is different from that of the sixth implantation region.

5. The SiC LDMOS device according to claim 2, characterized in that, The shielding region has a first distance between its surface near the substrate and the first surface, and the first source region has a second distance between its surface near the substrate and the first surface. The first surface is the surface of the doped region away from the substrate, and the first distance is greater than the second distance.

6. The SiC LDMOS device according to claim 4, characterized in that, The doping type of the fourth implantation region is different from that of the sixth implantation region, and the doping type of the fourth implantation region is different from that of the channel layer. Furthermore, the doping concentration of the channel layer is greater than that of the doped region, and the doping concentration of the channel layer is less than that of the sixth implantation region.

7. The SiC LDMOS device according to claim 1, characterized in that, The channel layer satisfies at least one of the following: The thickness of the channel layer ranges from 0.1 μm to 0.3 μm; The width of the channel layer ranges from 0.3 μm to 0.5 μm.

8. A method for fabricating a SiC LDMOS device, characterized in that, The method for fabricating the SiC LDMOS device according to any one of claims 1 to 7 comprises the following steps: A substrate is provided, the substrate comprising a substrate and an epitaxial layer, the epitaxial layer being located on a surface of one side of the substrate; A doped region is formed on one side of the surface of the substrate, the doped region and the epitaxial layer are disposed adjacent to each other, the doping type of the substrate is different from the doping type of the doped region, and the doping type of the substrate is different from the doping type of the epitaxial layer; A first source region extending inward along a first surface and a second source region extending inward along a second surface are formed in the doped region. A channel layer extending inward along the second surface is formed in the second source region. The first surface and the second surface are respectively the side surfaces of the doped region facing away from the substrate. The vertical distance between the first surface and the substrate is greater than the vertical distance between the second surface and the substrate. A gate structure is formed on the second surface, the side surface of the gate structure near the epitaxial layer is in contact with the doped region, the gate structure includes a first source, a gate and an oxide layer, the oxide layer is spaced between the gate and the first source, and the gate is located on the side of the first source away from the substrate; A second source electrode is formed in the first source region, the second source region, and the side of the gate structure facing away from the substrate, and the first source electrode and the second source electrode are electrically connected.

9. The preparation method according to claim 8, characterized in that, The steps for forming the first source region and the second source region include: Ion implantation is performed on the first surface to form a first pre-implantation region, which is in contact with the shielding region. Ion implantation is performed on the side of the first pre-implantation region away from the substrate to form a second implantation region and a second pre-implantation region. A portion of the first pre-implantation region, a portion of the second pre-implantation region, and a portion of the doped region are removed to expose the second surface. The remaining first pre-implantation region is the first implantation region, and the remaining second pre-implantation region is the third implantation region. The second implantation region is located on the side of the third implantation region closer to the epitaxial layer. The first implantation region, the second implantation region, and the third implantation region constitute the first source region. The doping type of the second implantation region is different from that of the third implantation region. Ion implantation is performed on the second surface to form a fourth implantation region. Ion implantation is performed on a portion of the fourth implantation region on the side facing away from the substrate to form a fifth implantation region and a sixth implantation region. The fifth implantation region is located on the side of the sixth implantation region facing away from the epitaxial layer. The doping types of the fifth implantation region and the sixth implantation region are different. The fourth implantation region, the fifth implantation region and the sixth implantation region constitute the second source region.

10. The preparation method according to claim 9, characterized in that, The steps for forming the gate structure include: A preliminary oxide layer is formed on the second surface, wherein the side surface of the preliminary oxide layer near the epitaxial layer is in contact with the doped region; Remove part of the prepared oxide layer to form a trench; The first source electrode, the first oxide layer, the gate electrode, and the second oxide layer are sequentially formed in the trench. By removing a portion of the pre-oxidation layer, the remaining pre-oxidation layer, the first oxide layer, and the second oxide layer constitute the oxide layer, and the oxide layer, the first source electrode, and the gate electrode constitute the gate structure.

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