LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a preparation method thereof. The first metal contact field plate and the second metal contact field plate are arranged above the drift region of the LDMOS device, and the first metal contact field plate is electrically connected with the gate metal, and the second metal contact field plate is electrically connected with the source metal, so that the alternating potential field plate can be provided, the electric field regulation is realized, and the reliability is improved. When the LDMOS device is prepared, the process step and the photomask do not need to be increased, so that the operation convenience can be realized, and the LDMOS device has wide applicability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to an LDMOS device and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are characterized by high voltage withstand capability, low on-resistance, strong driving capability, and good process compatibility, and are widely used in power management, automotive electronics, and high-voltage integrated circuits.

[0003] For LDMOS devices, when the device is in a high-voltage off state, the high voltage applied to the drain terminal is mainly absorbed and released through the drift region, which is an important functional region for achieving high withstand voltage. Therefore, the structure, potential distribution, and electric field distribution of the drift region have a significant impact on the device's breakdown voltage (BV), on-resistance (Ron), and long-term reliability.

[0004] For LDMOS devices, breakdown voltage, on-resistance, and reliability are interdependent. To improve breakdown voltage, it's typically necessary to reduce the drift region doping concentration, increase the drift region length, or enhance the drift region depletion capability to lower the peak electric field and increase the breakdown voltage. However, these measures increase the drift region resistance, thus raising the on-resistance. Conversely, while increasing the drift region doping concentration or shortening the drift region length can reduce on-resistance, it may lead to incomplete depletion and localized electric field concentration. This not only lowers the device's breakdown voltage but also enhances collisional ionization and hot carrier effects (HCI), resulting in an increase in interface states or oxide traps. This causes drift in parameters such as threshold voltage and on-resistance, ultimately reducing device reliability. Therefore, how to reduce the localized peak electric field and improve long-term reliability while maintaining a high breakdown voltage and low on-resistance is a key technical challenge in high-voltage LDMOS design.

[0005] In existing technologies, LDMOS devices typically employ a Local Oxidation of Silicon (LOCOS) structure or a single field plate structure to modulate the surface electric field of the drift region. The LOCOS structure utilizes a thicker field oxide layer to improve the potential distribution on the drift region surface and enhance the device's breakdown voltage. The field plate structure, on the other hand, adjusts the surface potential of the drift region through capacitive coupling between the conductive field plate and the drift region, thereby reducing the electric field intensity in certain areas. However, with the LOCOS structure, significant geometric and dielectric boundary changes occur at the LOCOS edges, beak regions, and locations where oxide layer thickness varies, leading to localized electric field concentration under high drain voltage conditions and resulting in poor device reliability. For LDMOS devices using a single field plate, although the field plate can redistribute the potential and electric field on the drift region surface to some extent, the limited coverage and coupling capability of the field plate make it difficult to achieve a uniform decrease in the overall potential of the drift region. Furthermore, new localized electric field peaks are easily formed at locations with significant potential changes, such as the ends of the field plate, which also contribute to poor device reliability.

[0006] Therefore, how to improve the potential and electric field distribution in the drift region of LDMOS, reduce the local peak electric field, and improve device reliability while maintaining a high breakdown voltage and low on-resistance remains a problem that needs to be solved by existing technologies. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an LDMOS device and its fabrication method to solve the problems of electric field concentration and reliability of LDMOS devices in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides an LDMOS device, the LDMOS device comprising:

[0009] Semiconductor substrate;

[0010] A drift region having a first conductivity type and located in the semiconductor substrate;

[0011] A body region having a second conductivity type, and the body region being located within the drift region;

[0012] A gate structure, wherein the gate structure is located on the drift region, and a portion of the body region is located below the gate structure;

[0013] A drain region and a source region, wherein the drain region has a first conductivity type and is located in the drift region, and the source region has a first conductivity type and is located in the body region; wherein, along a first direction, the drain region and the source region are respectively located on opposite sides of the gate structure;

[0014] The metal contact includes a gate metal contact, a source metal contact, and a metal contact field plate; wherein the gate metal contact is electrically connected to the gate structure; the source metal contact is electrically connected to the source region; the metal contact field plate is located between the gate structure and the drain region and is spaced apart, the metal contact field plate includes a first metal contact field plate and a second metal contact field plate, and the first metal contact field plate is electrically connected to the gate metal contact, and the second metal contact field plate is electrically connected to the source metal contact.

[0015] Optionally, both the first metal contact field plate and the second metal contact field plate extend along the second direction, and the first direction is perpendicular to the second direction.

[0016] Optionally, the top surfaces of the gate metal contact, the source metal contact, the first metal contact field plate, and the second metal contact field plate are located in the same plane or in different planes.

[0017] Optionally, it includes a plurality of first metal contact plates and a plurality of second metal contact plates.

[0018] Optionally, the first metal contact field plate and the second metal contact field plate may have the same number or different numbers.

[0019] Optionally, the first metal contact field plate and the second metal contact field plate may have the same morphology or different morphology.

[0020] Optionally, the first metal contact field plate and the second metal contact field plate are alternately arranged at equal intervals or alternately arranged at non-equal intervals.

[0021] Optionally, it further includes a silicide barrier layer located between the gate structure and the drain region, and all metal contact field plates are located on the silicide barrier layer; and / or further includes a body contact region having a second conductivity type, and the body contact region extends through the source region.

[0022] The present invention also provides a method for fabricating an LDMOS device, wherein the gate metal contact, source metal contact and metal contact field plate in the metal contact are fabricated simultaneously or in steps.

[0023] This invention also provides a method for fabricating an LDMOS device, comprising the following steps:

[0024] Provide semiconductor substrates;

[0025] A drift region having a first conductivity type is formed in the semiconductor substrate;

[0026] A gate structure is formed on the drift region;

[0027] A body region having a second conductivity type is formed in the drift region, and a portion of the body region is located below the gate structure;

[0028] Forming gate sidewalls;

[0029] A drain region having a first conductivity type is formed in the drift region, and a source region having a first conductivity type is formed in the body region; wherein, along a first direction, the drain region and the source region are respectively located on both sides of the gate structure;

[0030] A body contact region having a second conductivity type is formed in the source region, and the body contact region penetrates the source region;

[0031] A silicide barrier layer is formed between the gate structure and the drain region;

[0032] A metal contact is formed, comprising a gate metal contact, a source metal contact, and a metal contact field plate; wherein the gate metal contact is located on the gate structure and electrically connected to the gate structure; the source metal contact is located on the body contact region and electrically connected to the source region; the metal contact field plate is located on the silicide barrier layer between the gate structure and the drain region, and the metal contact field plate includes a first metal contact field plate and a second metal contact field plate spaced apart, wherein the first metal contact field plate is electrically connected to the gate metal contact, and the second metal contact field plate is electrically connected to the source metal contact.

[0033] As described above, the LDMOS device and its fabrication method of the present invention provide a first metal contact field plate and a second metal contact field plate above the drift region of the LDMOS device, such that the first metal contact field plate is electrically connected to the gate metal contact, and the second metal contact field plate is electrically connected to the source metal contact, thereby providing alternating potential field plates, realizing electric field modulation, and improving reliability. Furthermore, the LDMOS device of the present invention does not require additional process steps or photomasks during fabrication, thus achieving ease of operation and broad applicability. Attached Figure Description

[0034] Figure 1 The diagram shown is a top view of the LDMOS device in an embodiment of the present invention.

[0035] Figure 2 Displayed as Figure 1 A schematic diagram of the cross-sectional structure along the C-C' axis.

[0036] Figure 3 The diagram shows a comparison of the structure and electric field distribution of the LDMOS device in the embodiments and comparative examples of the present invention.

[0037] Figure 4 The diagram shows the fabrication process flow of the LDMOS device in an embodiment of the present invention.

[0038] Figure 5 The diagram shown is a schematic representation of the structure after the gate structure is formed in an embodiment of the present invention.

[0039] Figure 6 The diagram shown is a schematic representation of the structure after the gate sidewall is formed in an embodiment of the present invention.

[0040] Figure 7 The diagram shown is a schematic representation of the structure after the formation of the silicide barrier layer in an embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures

[0042] 100 Semiconductor substrate 200 Drift Zone 300 gate structure 301 Gate dielectric layer 302 Gate conductive layer 400 Body area 500 Gate sidewall 600 Drain region 700 Source region 800 Body contact area 900 silicide barrier layer 110 Metal contact 111 Gate metal contact 112 Source metal contact 113 First metal contact plate 114 Second metal contact plate Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0045] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] See Figure 1 and Figure 2 This embodiment provides an LDMOS device, wherein, Figure 1 This diagram shows a top view of the LDMOS device in this embodiment. Figure 2 This indicates that Figure 1 A schematic diagram of the cross-sectional structure along line C-C'. (See diagram below.) Figure 1 and Figure 2 As shown, the LDMOS device includes:

[0048] Semiconductor substrate 100;

[0049] A drift region 200 having a first conductivity type and located in the semiconductor substrate 100;

[0050] Body region 400, having a second conductivity type, and located within the drift region 200;

[0051] A gate structure 300 is located on the drift region 200, and a portion of the body region 400 is located below the gate structure 300;

[0052] A drain region 600 and a source region 700 are provided. The drain region 600 has a first conductivity type and is located in the drift region 200. The source region 700 has a first conductivity type and is located in the body region 400. Along a first direction, the drain region 600 and the source region 700 are located on opposite sides of the gate structure 300.

[0053] The metal contact 110 includes a gate metal contact 111, a source metal contact 112, and a metal contact field plate. The gate metal contact 111 is electrically connected to the gate structure 300; the source metal contact 112 is electrically connected to the source region 700; the metal contact field plate is located between and spaced apart from the gate structure 300 and the drain region 600. The metal contact field plate includes a first metal contact field plate 113 and a second metal contact field plate 114, with the first metal contact field plate 113 electrically connected to the gate metal contact 111 and the second metal contact field plate 114 electrically connected to the source metal contact 112.

[0054] In this embodiment, a first metal contact field plate 113 and a second metal contact field plate 114 are disposed above the drift region 200, such that the first metal contact field plate 113 is electrically connected to the gate metal contact 111 and the second metal contact field plate 114 is electrically connected to the source metal contact 112, thereby providing an alternating potential field plate, realizing electric field control, and improving reliability.

[0055] In this embodiment, the first conductivity type is N-type and the corresponding second conductivity type is P-type. In another embodiment, the first conductivity type can also be P-type, and the corresponding second conductivity type is N-type, depending on the needs.

[0056] The following description uses an N-type LDMO device where the first conductivity type is N-type and the corresponding second conductivity type is P-type as an example. In this embodiment, the semiconductor substrate 100 can be a P-type semiconductor substrate or a semiconductor substrate with a P-type doped region, such as a P-type silicon substrate, a P-type silicon-germanium substrate, or a P-type silicon-on-insulator (SOI). The drift region 200 is N-type, the body region 400 is P-type, and both the drain region 600 and the source region 700 are N-type.

[0057] For information on P-type LDMOS devices where the first conductivity type is P-type and the corresponding second conductivity type is N-type, please refer to the N-type LDMOS device documentation; further details will not be provided below.

[0058] As needed, the semiconductor substrate 100 may also be provided with an isolation structure (not shown) to define multiple device regions in the semiconductor substrate 100. The isolation structure may be, for example, shallow trench isolation (STI) or deep trench isolation (DTI).

[0059] Furthermore, in this embodiment, a P-type body contact region 800 is also provided, wherein the body contact region 800 penetrates the source region 700 and contacts the body region 400. The body contact region 800 and the body region 400 have the same conductivity type, and the doping concentration of the body contact region 800 is greater than that of the body region 400. Thus, the body contact region 800 can be used to reduce the contact resistance of the body region 400 and provide a discharge path for the charge carriers in the body region 400 to stabilize the potential of the body region 400.

[0060] The gate structure 300 includes a gate dielectric layer 301 and a gate conductive layer 302 located on the gate dielectric layer 301. The gate dielectric layer 301 may include, for example, a silicon oxide layer or other types of dielectric materials; the gate conductive layer 302 may include, for example, a doped polysilicon layer or a metal layer.

[0061] In this embodiment, a gate sidewall 500 is also provided on the sidewall of the gate structure 300, such as a silicon oxide gate sidewall, a silicon nitride gate sidewall, etc. The gate sidewall 500 can be a single-layer structure, or it can be a stacked structure as needed, which is not limited here.

[0062] In this embodiment, a silicide barrier layer 900 (SAB) is also provided, such as an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

[0063] The silicide barrier layer 900 is located between the gate structure 300 and the drain region 600. In this embodiment, the silicide barrier layer 900 extends to the gate sidewall 500 of the gate structure 300, but is not limited thereto. The metal contact field plates are all located on the silicide barrier layer 900. Thus, the silicide barrier layer 900 can prevent the formation of metal silicide in the drift region 200. On the other hand, the silicide barrier layer 900 can also serve as the dielectric layer of the metal contact field plates, thereby achieving dielectric isolation between the field plates and the semiconductor, forming a structure similar to a metal-oxide-semiconductor (MOS) capacitor. This allows the metal contact field plates to be capacitively coupled to the drift region 200 through the silicide barrier layer 900, thereby adjusting the surface potential and electric field of the drift region 200.

[0064] The LDMOS device may further include, for example, a self-aligned silicide contact layer (not shown) to reduce contact resistance; and the LDMOS device may further include, for example, a lightly doped region (not shown).

[0065] Among them, see Figure 1 and Figure 2 It is understood that a dielectric layer (not shown) may also be included around the metal contact 110 to facilitate the fabrication of the metal contact 110.

[0066] In this embodiment, the metal contact 110 includes the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114; wherein, the gate metal contact 111 is electrically connected to the gate structure 300; the source metal contact 112 is electrically connected to the source region 700; the first metal contact field plate 113 is electrically connected to the gate metal contact 111; and the second metal contact field plate 114 is electrically connected to the source metal contact 112.

[0067] It should be noted that, in this embodiment, for ease of description, the direction from the drain region 600 to the source region 700 is defined as the first direction, i.e., the X direction in the figure; the direction perpendicular to the first direction is defined as the second direction, i.e., the Y direction in the figure; and the direction perpendicular to the plane containing the first and second directions is defined as the third direction, i.e., the Z direction in the figure.

[0068] See Figure 1 and Figure 2 In this embodiment, the first metal contact field plate 113 and the second metal contact field plate 114 both extend along the second direction, such that the first metal contact field plate 113 and the second metal contact field plate 114 are parallel and spaced apart. However, in another embodiment, the first metal contact field plate 113 and the second metal contact field plate 114 may also be non-parallel and spaced apart.

[0069] See Figure 1 and Figure 2 In this embodiment, the top surfaces of the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114 are located on the same plane.

[0070] For details, please refer to Figure 2 In this embodiment, preferably, the top surfaces of the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114 are located on the same plane, and refer to Figure 1 In this embodiment, the interconnection between the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114 can be realized in the plane containing the first and second directions. That is, the first interconnection structure formed by the first metal contact field plate 113 and the gate metal contact 111 and the second interconnection structure formed by the second metal contact field plate 114 and the source metal contact 112 can be interconnected in a comb-like cross arrangement in the XY plane. Therefore, good electrical connection can be easily achieved without complex avoidance structures.

[0071] Of course, in another embodiment, the top surfaces of the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114 may also be located on different planes. For example, the top surface of the first interconnect structure formed by the first metal contact field plate 113 and the gate metal contact 111 is located on the first plane, and the top surface of the second interconnect structure formed by the second metal contact field plate 114 and the source metal contact 112 is located on the second plane. The first plane and the second plane have a height difference, so that the interconnection clearance space can be realized in the Z direction through the height difference between the first plane and the second plane for electrical connection.

[0072] See Figure 1 and Figure 2 In this embodiment, a plurality of first metal contact field plates 113 and a plurality of second metal contact field plates 114 are included. The number of first metal contact field plates 113 may include N ≥ 1, such as 1, 2, 3, 4, 5, etc., and the number of second metal contact field plates 114 may include M ≥ 1, such as 1, 2, 3, 4, 5, etc. The specific number of first metal contact field plates 113 and second metal contact field plates 114 is not excessively limited here.

[0073] The first metal contact field plate 113 and the second metal contact field plate 114 may have the same number, or they may have different numbers.

[0074] See Figure 1 and Figure 2 In this embodiment, there are 6 first metal contact field plates 113 and 6 second metal contact field plates 114, so that the first metal contact field plates 113 and the second metal contact field plates 114 have the same number. Of course, the first metal contact field plates 113 and the second metal contact field plates 114 can be set to have different numbers as needed.

[0075] The first metal contact field plate 113 and the second metal contact field plate 114 may have the same morphology, or they may be configured to have different morphologies.

[0076] See Figure 1 and Figure 2In this embodiment, both the first metal contact field plate 113 and the second metal contact field plate 114 adopt a strip structure, and preferably both have the same morphology. However, the morphology of the first metal contact field plate 113 and the second metal contact field plate 114 is not limited to this. For example, the first metal contact field plate 113 and the second metal contact field plate 114 may adopt different morphologies, such as having different lengths in the X direction, and / or having different widths in the Y square, or one of the first metal contact field plate 113 and the second metal contact field plate 114 may be strip-shaped and the other may be elliptical, etc.

[0077] The first metal contact plate 113 and the second metal contact plate 114 can be alternately arranged at equal intervals or alternately arranged at non-equal intervals.

[0078] See Figure 1 and Figure 2 In this embodiment, the first metal contact field plate 113 and the second metal contact field plate 114 are alternately arranged at equal intervals. However, as needed, the first metal contact field plate 113 and the second metal contact field plate 114 can also be alternately arranged at non-equal intervals.

[0079] See Figure 3 To illustrate the performance of the LDMOS device (structure B in the figure) in this embodiment, an LDMOS device with a comparative structure (structure A in the figure) is provided, along with a comparison diagram of the electric field distribution of the two.

[0080] It should be noted that in the electric field distribution diagram, the x-axis represents distance, the y-axis represents electric field strength (E), and the integral area represents potential difference.

[0081] Among them, the LDMOS device with structure A, compared with the LDMOS device with structure B, only retains the field plate electrically connected to the gate metal contact 111 on the silicide barrier layer 900, while the structure of the remaining regions is the same as that of the LDMOS device with structure B.

[0082] Specifically, in semiconductor devices, the reliability of the device often depends on the strength of the peak electric field of the device under a specific operating scenario (with the same area / potential difference). The stronger the peak electric field, the worse the reliability of the device under that scenario; the smaller the peak electric field, the better the reliability of the device under that scenario.

[0083] See Figure 3In this embodiment, the LDMOS device (B structure) introduces multiple alternating potentials in the first metal contact field plate 113 and the second metal contact field plate 114, thereby introducing multiple electric field peaks in the drift region 200. This increases the overall electric field at the low electric field troughs in the drift region 200, even if the potential of the entire drift region 200 is higher (L2>L1). Under the condition that the operating scenario remains unchanged, i.e., the integral area remains unchanged, the gate structure 300 is closer to the drain region 600 on the side ( Figure 3 The peak electric field at the edge or corner (weak point) of the gate (lower left) will drop more in the drift region 200 of L2 because the potential drops more, which can lower the peak electric field at the weak point, i.e., P2 < P1. Therefore, the peak electric field at the weak point is reduced, and the reliability is improved.

[0084] This embodiment also provides a method for fabricating the above-mentioned LDMOS device, wherein the gate metal contact 111, the source metal contact 112 and the metal contact field plate in the metal contact 110 are preferably fabricated simultaneously. Of course, in another embodiment, the gate metal contact 111, the source metal contact 112 and the metal contact field plate can also be fabricated in steps.

[0085] See Figure 4 This embodiment provides a method for fabricating the LDMOS device, but the method for fabricating the LDMOS device is not limited to this, and adaptive process adjustments can be made according to this method.

[0086] The following is in conjunction with the instruction manual. Figure 1 , Figure 2 and Figures 5-7 The fabrication method of the LDMOS device is further described below.

[0087] In this embodiment, the first conductivity type is N-type and the corresponding second conductivity type is P-type. In another embodiment, the first conductivity type can also be P-type, and the corresponding second conductivity type is N-type, depending on the needs.

[0088] The following explanation uses only an N-type LDMO device, where the first conductivity type is N-type and the corresponding second conductivity type is P-type, as an example.

[0089] First, refer to Figure 4 and Figure 5 Step S1 is performed to provide a semiconductor substrate 100.

[0090] Specifically, the semiconductor substrate 100 may be a P-type semiconductor substrate or a semiconductor substrate with a P-type doped region, such as a P-type silicon substrate, a P-type silicon-germanium substrate, or a P-type silicon-on-insulator (SOI). The size and material of the semiconductor substrate 100 can be selected as needed, and no excessive restrictions are imposed here.

[0091] As needed, the semiconductor substrate 100 may also be provided with an isolation structure (not shown) to define multiple device regions in the semiconductor substrate 100. The isolation structure may be, for example, shallow trench isolation (STI) or deep trench isolation (DTI).

[0092] Next, refer to Figure 4 and Figure 5 Step S2 is executed to form an N-type drift region 200 in the semiconductor substrate 100. The desired drift region 200 can be formed in the semiconductor substrate 100 by controlling the dopant implantation energy and implantation metering.

[0093] Next, refer to Figure 4 and Figure 5 Step S3 is executed to form a gate structure 300 on the drift region 200.

[0094] Specifically, a gate dielectric layer 301 can be formed on the drift region 200 by means of a thermal oxidation process, and then a doped polysilicon layer or metal layer can be formed on the gate dielectric layer 301 as a gate conductive layer 302, and the gate structure 300 can be prepared by a patterning process.

[0095] Next, refer to Figure 4 and Figure 6 Step S4 is executed to form a P-type body region 400 in the drift region 200, and a portion of the body region 400 is located below the gate structure 300.

[0096] Next, refer to Figure 4 and Figure 6 Step S5 is executed to form a gate sidewall 500, such as a silicon oxide gate sidewall or a silicon nitride gate sidewall. The gate sidewall 500 can be a single-layer structure, or it can be a stacked structure as needed. This is not limited here.

[0097] Next, refer to Figure 4 and Figure 7 Step S6 is executed to form an N-type drain region 600 in the drift region 200 and an N-type source region 700 in the body region 400; wherein, along the first direction, the drain region 600 and the source region 700 are respectively located on both sides of the gate structure 300.

[0098] Next, refer to Figure 4 and Figure 7 Step S7 is executed to form a P-type bulk contact region 800 in the source region 700, and the bulk contact region 800 penetrates the source region 700.

[0099] The body contact region 800 penetrates the source region 700 and contacts the body region 400. The body contact region 800 and the body region 400 have the same conductivity type, and the doping concentration of the body contact region 800 is greater than that of the body region 400. Thus, the body contact region 800 can be used to reduce the contact resistance of the body region 400 and provide a discharge path for the charge carriers in the body region 400 to stabilize the potential of the body region 400.

[0100] Next, refer to Figure 4 and Figure 7 Step S8 is executed, in which a silicide barrier layer 900 (SAB) is formed between the gate structure 300 and the drain region 600, such as an oxide layer, a nitride layer, an oxynitride layer or a combination thereof.

[0101] The silicide barrier layer 900 is located between the gate structure 300 and the drain region 600. In this embodiment, the silicide barrier layer 900 extends to the gate sidewall 500 of the gate structure 300, but is not limited thereto. The metal contact field plates are all located on the silicide barrier layer 900. Thus, the silicide barrier layer 900 can prevent the formation of metal silicide in the drift region 200. On the other hand, the silicide barrier layer 900 can also serve as the dielectric layer of the metal contact field plates, thereby achieving dielectric isolation between the field plates and the semiconductor, forming a structure similar to a metal-oxide-semiconductor (MOS) capacitor. This allows the metal contact field plates to be capacitively coupled to the drift region 200 through the silicide barrier layer 900, thereby adjusting the surface potential and electric field of the drift region 200.

[0102] The LDMOS device may also include, for example, a self-aligned silicide contact layer (not shown) to reduce contact resistance, and the LDMOS device may also include, for example, a lightly doped region (not shown).

[0103] Next, refer to Figure 4 and Figure 7Step S9 is executed to form a metal contact 110, which includes a gate metal contact 111, a source metal contact 112, and a metal contact field plate. The gate metal contact 111 is located on the gate structure 300 and electrically connected to the gate structure 300. The source metal contact 112 is located on the body contact region 800 and electrically connected to the source region 700. The metal contact field plate is located on the silicide barrier layer 900 between the gate structure 300 and the drain region 600. The metal contact field plate includes a first metal contact field plate 113 and a second metal contact field plate 114 spaced apart. The first metal contact field plate 113 is electrically connected to the gate metal contact 111, and the second metal contact field plate 114 is electrically connected to the source metal contact 112.

[0104] It can be understood that the formation of the metal contact 110 may include a step of forming a dielectric layer (not shown) to facilitate the preparation of the metal contact 110.

[0105] In this embodiment, it is preferred that the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114 are fabricated simultaneously. Of course, in another embodiment, the gate metal contact 111, the source metal contact 112, the first metal contact field plate 113, and the second metal contact field plate 114 can also be fabricated in stages.

[0106] For details regarding the morphology and distribution of the first metal contact field plate 113 and the second metal contact field plate 114, please refer to the above description of the LDMOS device; further details will not be provided here.

[0107] In summary, the LDMOS device and its fabrication method of the present invention provide a first metal contact field plate and a second metal contact field plate above the drift region of the LDMOS device, wherein the first metal contact field plate is electrically connected to the gate metal contact, and the second metal contact field plate is electrically connected to the source metal contact, thereby providing alternating potential field plates, achieving electric field modulation, and improving reliability. Furthermore, the LDMOS device of the present invention does not require additional process steps or photomasks during fabrication, thus achieving ease of operation and broad applicability.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LDMOS device, characterized in that, The LDMOS device includes: Semiconductor substrate; A drift region having a first conductivity type and located in the semiconductor substrate; A body region having a second conductivity type, and the body region being located within the drift region; A gate structure, wherein the gate structure is located on the drift region, and a portion of the body region is located below the gate structure; A drain region and a source region, wherein the drain region has a first conductivity type and is located in the drift region, and the source region has a first conductivity type and is located in the body region; wherein, along a first direction, the drain region and the source region are respectively located on opposite sides of the gate structure; The metal contact includes a gate metal contact, a source metal contact, and a metal contact field plate; wherein the gate metal contact is electrically connected to the gate structure; the source metal contact is electrically connected to the source region; the metal contact field plate is located between the gate structure and the drain region and is spaced apart, the metal contact field plate includes a first metal contact field plate and a second metal contact field plate, and the first metal contact field plate is electrically connected to the gate metal contact, and the second metal contact field plate is electrically connected to the source metal contact.

2. The LDMOS device according to claim 1, characterized in that: Both the first metal contact field plate and the second metal contact field plate extend along the second direction, and the first direction is perpendicular to the second direction.

3. The LDMOS device according to claim 1, characterized in that: The top surfaces of the gate metal contact, the source metal contact, the first metal contact field plate, and the second metal contact field plate are located on the same plane or on different planes.

4. The LDMOS device according to claim 1, characterized in that: It includes multiple first metal contact field plates and multiple second metal contact field plates.

5. The LDMOS device according to claim 4, characterized in that: The first metal contact field plate and the second metal contact field plate may have the same number or different numbers.

6. The LDMOS device according to claim 4, characterized in that: The first metal contact field plate and the second metal contact field plate have the same morphology or different morphologies.

7. The LDMOS device according to claim 4, characterized in that: The first metal contact field plate and the second metal contact field plate are alternately arranged with equal spacing or with non-equal spacing.

8. The LDMOS device according to claim 1, characterized in that: It also includes a silicide barrier layer located between the gate structure and the drain region, and all metal contact field plates are located on the silicide barrier layer; and / or includes a body contact region having a second conductivity type, and the body contact region extends through the source region.

9. A method for fabricating an LDMOS device as described in any one of claims 1 to 8, characterized in that: The gate metal contact, source metal contact, and metal contact field plate in the metal contact are fabricated simultaneously or in stages.

10. A method for fabricating an LDMOS device as described in any one of claims 1 to 8, characterized in that, Includes the following steps: Provide semiconductor substrates; A drift region having a first conductivity type is formed in the semiconductor substrate; A gate structure is formed on the drift region; A body region having a second conductivity type is formed in the drift region, and a portion of the body region is located below the gate structure; Forming gate sidewalls; A drain region having a first conductivity type is formed in the drift region, and a source region having a first conductivity type is formed in the body region; wherein, along a first direction, the drain region and the source region are respectively located on both sides of the gate structure; A body contact region having a second conductivity type is formed in the source region, and the body contact region penetrates the source region; A silicide barrier layer is formed between the gate structure and the drain region; A metal contact is formed, comprising a gate metal contact, a source metal contact, and a metal contact field plate; wherein the gate metal contact is located on the gate structure and electrically connected to the gate structure; the source metal contact is located on the body contact region and electrically connected to the source region; the metal contact field plate is located on the silicide barrier layer between the gate structure and the drain region, and the metal contact field plate includes a first metal contact field plate and a second metal contact field plate spaced apart, wherein the first metal contact field plate is electrically connected to the gate metal contact, and the second metal contact field plate is electrically connected to the source metal contact.

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