Semiconductor device and method of manufacturing the same, power module, power conversion circuit, vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a cell region, a transition region and a terminal region; the transition region surrounds the cell region, and the terminal region surrounds the transition region; the semiconductor device comprises: a semiconductor body comprising oppositely arranged first and second surfaces; a metal structure located in the transition region and on a side of the first surface away from the second surface, the metal structure comprising at least one of a gate metal and a source lead metal; a passivation layer extending from the terminal region to the transition region, the passivation layer covering the metal structure, the passivation layer comprising an oxide layer and a nitride layer located on a side of the oxide layer away from the first surface; and the passivation layer comprising a sidewall located on a sidewall of the metal structure, two adjacent sidewalls forming an opening penetrating through the passivation layer. The semiconductor device of the application can improve the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) are widely used in power electronics, automotive, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] Silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) in related technologies have advantages such as high current density and small cell spacing. However, MOSFETs are prone to failure during temperature cycling tests or other reliability tests, resulting in low reliability of semiconductor devices. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, to improve the reliability of semiconductor devices.

[0005] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising a cell region, a transition region, and a termination region; the transition region surrounds the cell region, and the termination region surrounds the transition region; the semiconductor device comprises: The semiconductor body includes a first surface and a second surface disposed opposite to each other; A metal structure is located in the transition region and on the side of the first surface away from the second surface, the metal structure comprising at least one of gate metal and source lead metal; A passivation layer extends from the terminal region to the transition region, covering the metal structure. The passivation layer includes an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface. The passivation layer includes sidewalls located on the sidewalls of the metal structure, with an opening forming between two adjacent sidewalls that penetrates the passivation layer.

[0006] Optionally, the metal structure includes the gate metal and a source lead metal located on the side of the gate metal away from the cell region; The sidewall located on the side of the source lead metal away from the cell region extends to the side of the source lead metal away from the first surface.

[0007] Optionally, the passivation layer forms a continuous surface in the portion of the terminal region.

[0008] Optionally, the semiconductor device further includes a protective layer that covers the passivation layer and contacts the nitride layer.

[0009] Optionally, the semiconductor device further includes a source metal located in the cell region, the source metal being connected to the source lead metal; the passivation layer further includes a sidewall located on the sidewall of the source metal near the transition region.

[0010] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, the semiconductor device comprising a cell region, a transition region, and a termination region; the transition region surrounds the cell region, and the termination region surrounds the transition region; The method for fabricating the semiconductor device includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; A metal structure is formed, the metal structure being located in the transition region and on the side of the first surface away from the second surface, the metal structure comprising at least one of gate metal and source lead metal; A passivation layer is formed, the passivation layer extending from the terminal region to the transition region, the passivation layer covering the metal structure, the passivation layer including an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface; the passivation layer includes sidewalls located on the sidewalls of the metal structure, and an opening penetrating the passivation layer is formed between two adjacent sidewalls.

[0011] Optionally, forming the passivation layer includes: Forming an oxide layer and a nitride layer that cover the entire surface; A mask layer is formed that extends from the terminal region to the transition region and terminates near the top of the metal structure near the terminal region; Using the mask layer as a mask, the oxide layer and the nitride layer not covered by the mask layer are etched to form the passivation layer.

[0012] Optionally, after forming the passivation layer, the method further includes forming a protective layer that covers and contacts the nitride layer.

[0013] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described above, the substrate being used to support the semiconductor device.

[0014] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described above, the semiconductor device being electrically connected to the circuit board.

[0015] According to another aspect of the present invention, a vehicle is provided, including a load and the power conversion circuit as described above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0016] The semiconductor device includes a cell region, a transition region, and a termination region; the transition region surrounds the cell region, and the termination region surrounds the transition region. The semiconductor device includes: a semiconductor body, comprising a first surface and a second surface disposed opposite to each other; a metal structure located in the transition region and on the side of the first surface away from the second surface, the metal structure including at least one of gate metal and source lead metal; a passivation layer extending from the termination region to the transition region, covering the metal structure, the passivation layer including an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface; the passivation layer includes sidewalls located on the sidewalls of the metal structure, with an opening forming between two adjacent sidewalls that penetrates the passivation layer. By creating openings in the passivation layer, external stress transmitted to the passivation layer is released at the openings, thereby preventing passivation layer fracture and improving the reliability of the semiconductor device. The presence of openings between any two sidewalls makes it easier for stress to be released at the corners of the passivation layer, further reducing the risk of passivation layer fracture and improving the reliability of the semiconductor device.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 3 to 17 This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1 The semiconductor device includes a cell region AA, a transition region NAA1, and a termination region NAA2; the transition region NAA1 surrounds the cell region AA, and the termination region NAA2 surrounds the transition region NAA1; a semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; a metal structure 81 located in the transition region NAA1 and on the side of the first surface 101 away from the second surface 102, the metal structure 81 including at least one of a gate metal 811 and a source lead metal 812; a passivation layer 82 extending from the termination region NAA2 to the transition region NAA1, the passivation layer 82 covering the metal structure 81, the passivation layer 82 including an oxide layer 821 and a nitride layer 822 located on the side of the oxide layer 821 away from the first surface 101; the passivation layer 82 includes a sidewall 82B located on the sidewall of the metal structure 81, and an opening 82A is formed between two adjacent sidewalls 82B that penetrates the passivation layer 82.

[0023] Specifically, the semiconductor device can be a silicon carbide semiconductor field-effect transistor, meaning the semiconductor body can be a wide-bandgap semiconductor material such as silicon carbide. The cellular region AA of the semiconductor device includes multiple cells, each of which can be equivalent to a MOSFET device. Multiple cells connected in parallel allow the semiconductor device to withstand a larger current. The transition region NAA1 is used to house metal structures 81, where the gate metal 811 provides the gate signal required by the semiconductor device, and the source metal 812 provides the source signal required by the semiconductor device. The termination region 83 is used to house structures such as a field-limiting ring 85 to protect the semiconductor device from interference from external electric fields.

[0024] A passivation layer 82 covers the metal structure 81. The passivation layer 82 prevents moisture and other contaminants from entering the semiconductor body 100 of the semiconductor device, thereby improving the reliability of the semiconductor device. Specifically, the nitride layer 822 has high density, making it difficult for sodium ions to penetrate, thus providing good water vapor resistance. The oxide layer 821 has relatively low intrinsic stress, providing a certain buffering effect. The stress generated by the metal structure 81 can be at least partially absorbed by the oxide layer 821, preventing it from being entirely transferred to the nitride layer 822. However, during reliability tests such as temperature cycling, the metal structure 81 transmits significant stress to the outside due to thermal expansion and contraction. Since the nitride layer 822 in the passivation layer 82 has relatively high intrinsic stress, it still experiences significant stress. Under large external stress, it is more prone to fracture, leading to semiconductor device failure. In this embodiment, by creating an opening 82A in the passivation layer 82, external stress transmitted to the passivation layer 82 will be released at the opening 82A, thereby preventing the passivation layer 82 from cracking and improving the reliability of the semiconductor device. The opening 82A completely penetrates the passivation layer 82, allowing more space for stress release within the passivation layer 82, thus enabling the passivation layer 82 to release stress more quickly and reducing the risk of cracking.

[0025] Furthermore, the passivation layer 82 forms a concave shape between the two metal structures, where stress is more concentrated at each corner, making it more prone to breakage. In this embodiment, an opening 82A is provided between any two sidewalls 82B, which makes it easier to release stress at each corner of the passivation layer 82, thereby further reducing the risk of passivation layer 82 breakage and improving the reliability of the semiconductor device.

[0026] The sidewall 82B and opening 82A configuration in this embodiment further simplifies the semiconductor device fabrication process and reduces fabrication difficulty. Specifically, since only the portion of the passivation layer 82 corresponding to the sidewall 82B needs to be retained in the passivation layer to be etched, the mask layer does not need to have fine openings; it only needs to cover the continuous portion that is not intended to be etched. During etching, the sidewall 82B and opening 82A are automatically formed, thereby greatly simplifying the fabrication process and reducing fabrication costs.

[0027] The technical solution of this embodiment employs a semiconductor device comprising a cell region, a transition region, and a termination region. The transition region surrounds the cell region, and the termination region surrounds the transition region. The semiconductor device includes: a semiconductor body, comprising a first surface and a second surface disposed opposite to each other; a metal structure located in the transition region and on the side of the first surface away from the second surface, the metal structure comprising at least one of a gate metal and a source lead metal; a passivation layer extending from the termination region to the transition region, the passivation layer covering the metal structure, the passivation layer comprising an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface; the passivation layer includes sidewalls located on the sidewalls of the metal structure, with an opening forming between two adjacent sidewalls that penetrates the passivation layer. By creating an opening in the passivation layer, when external stress is transmitted to the passivation layer, it will be released at the opening, thereby preventing the passivation layer from fracturing and improving the reliability of the semiconductor device. The presence of an opening between any two sidewalls makes it easier for stress at each corner of the passivation layer to be released, thereby further reducing the risk of passivation layer fracturing and improving the reliability of the semiconductor device.

[0028] Optionally, the semiconductor body includes a first region 60 and a well region 50 located in cell region AA; the first region 60 is configured with a first conductivity type and located on the first surface 101, and the well region 50 is configured with a second conductivity type and located on the side of the first region 60 away from the first surface 101; the semiconductor body 100 also includes a second region 30 located on the side of the well region 50 away from the first surface 101. The semiconductor body 100 may include at least one epitaxial layer for forming the second region 30, the well region 50, and the first region 60. The first region 60 and the second region 30 have the same conductivity type, while the well region 50 has a different conductivity type than the first region 60. For ease of description, the following example uses N-type as the first conductivity type and P-type as the second conductivity type. The first region 60 provides a conductive channel between the well region 50 and the source metal, and has a low contact resistance with the source metal. When the semiconductor device is in the off state, the well region 50 blocks the conductive channel between the first region 60 and the second region 30. When the voltage applied between the gate 721 and the source metal is greater than the threshold voltage of the semiconductor device, the gate 721 attracts minority carriers (such as electrons) in the well region 50 to move towards the region of the gate 721, causing the part of the well region 50 near the gate trench 72 to be inverted to the first conductivity type. That is, at this time, the first region 60, the part of the well region 50 near the gate trench 72 and the second region 30 have the same conductivity type. When a voltage is applied between the source metal and the drain, current can be generated, and the semiconductor device is in the conducting state.

[0029] Optionally, the semiconductor device can be an N-type MOSFET device. In some other embodiments, the semiconductor device can also be a P-type MOSFET. When the semiconductor body is an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; when the semiconductor device is a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. For example, regions with N-type conductivity can be formed by N-type doping, and the dopant ions for N-type doping can be phosphorus (P) ions or nitrogen (N) ions; regions with P-type conductivity can be formed by P-type doping, and the dopant ions for P-type doping can be aluminum (Al) ions or boron (B) ions.

[0030] Optionally, in some embodiments, the semiconductor device is a trench-gate semiconductor device; in other embodiments, the semiconductor device may also be a planar-gate semiconductor device. This embodiment uses a trench-gate semiconductor device as an example for illustration. Each cell corresponds to a gate trench 72, and the gate 721 fills the gate trench 72. It is understood that the semiconductor device also includes a gate oxide layer 71, which is used to insulate the gate 721 from the conductive channel of the cell. The gate oxide layer 71 may be formed by thermal oxidation of the inner wall of the gate trench 72. That is, the gate oxide layer 71 may be formed directly using the semiconductor body itself. A gate line layer 75 may be provided in the transition region NAA1. The material of the gate line layer 75 is the same as that of the gate 721, and they are an integral structure; the gate metal 811 is in contact with the gate line layer 75.

[0031] Optionally, the semiconductor device also includes a source metal 74 located in the cell region AA. The source metal 74 and the source lead metal 812 can be integrally connected to the same potential. Of course, it is understood that the metal structure 81 may only include the gate metal 811 or only the source lead metal 812. A fourth region 84 is also provided in the transition region NAA1. The fourth region 84 surrounds the cell region AA, is located on the first surface 101 and is in contact with the first source metal 812. The fourth region 84 is configured as a second conductivity type and its ion doping concentration is greater than that of the well region 50. The fourth region 84 can protect the cells in the cell region AA from interference by external electric fields, etc.

[0032] Optionally, such as Figure 1 As shown, the semiconductor body may further include a third region 20, which is located on the side of the second region 30 away from the first surface 101. The conductivity type of the third region 20 may be the same as that of the second region 30. That is, the third region 20 is of the first conductivity type, and its ion doping concentration may be lower than that of the second region 30. The third region 20 can be understood as a drift region, or an N-region, which can be used to withstand higher breakdown voltages when the semiconductor device is turned off.

[0033] Optionally, such as Figure 1 As shown, the semiconductor device also includes a fifth region 40, which is located on the first surface and is in contact with the first region 60, the well region 50, and the source metal 74. The fifth region 40 is of the second conductivity type and is used to provide a stable potential for the well region 50. The fifth region 40, the fourth region 84, and the field confinement ring 85 can have the same ion doping concentration and can be formed simultaneously.

[0034] Optionally, such as Figure 1As shown, the semiconductor body 100 may further include a substrate 10, which is of a first conductivity type. Of course, in some embodiments, the semiconductor body may not include a substrate 10. When the semiconductor body 100 includes a substrate 10, the surface of the substrate 10 away from the first surface 101 is the second surface 102 of the semiconductor body 100.

[0035] Optionally, in some embodiments, the semiconductor body includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer is used to form a third region 20. The second epitaxial layer is used to form a second region 30, and a first region 60, a well region 50, a fifth region 40, a fourth region 84, and a field confinement ring 85 can be formed in the second epitaxial layer by means of ion implantation or the like.

[0036] Optionally, continue to refer to Figure 1 In some embodiments, the semiconductor device further includes a field oxide structure 76 located in the transition region NAA1 and the terminal region NAA2, the field oxide structure 76 being used to isolate the gate line layer 75 and the fourth region 84. The semiconductor device also includes a dielectric layer 73, the portion of which in the cell region AA is used to isolate the gate 721 and the source metal 74. The portion of which in the transition region NAA1 is used to isolate the metal structure and the field oxide structure.

[0037] Optionally, continue to refer to Figure 1 The metal structure 81 includes a gate metal 811 and a source lead metal 812 located on the side of the gate metal 811 away from the cell region AA; a sidewall (hereinafter defined as the first sidewall) located on the side of the source lead metal 812 away from the cell region AA extends to the side of the source lead metal 812 away from the first surface 101.

[0038] Specifically, in this embodiment, the first sidewall extends to the top of the source lead metal 812, that is, completely covers the corner of the source lead metal 812 near the termination region NAA2. With this configuration, the mask layer set during the etching of the passivation layer can be positioned at any point on the top of the source lead metal 812, without needing to consider the distance between the cutoff point and the source lead metal 812 when it is positioned at the termination region NAA2; when the cutoff point is in the termination region, the corner of the source lead metal near the termination region NAA2 and the first surface 101 (i.e.,...) Figure 1 An opening is etched into the passivation layer at the bottom right corner. The size of this opening is related to the reliability of the semiconductor device. If it is not set properly, it will seriously affect the reliability. By setting the cutoff position at the top of the source lead metal 812, the corner of the source lead metal near the terminal region NAA2 and the first surface 101 is covered by the passivation layer, preventing moisture from entering the semiconductor device from here. In other words, it can reduce the design difficulty of the semiconductor device and also ensure that the semiconductor device has high reliability.

[0039] Optionally, continue to refer to Figure 1 The passivation layer 82 forms a continuous surface in the terminal region NAA2. That is, the passivation layer 82 in the terminal region NAA2 does not have an opening; on the one hand, this reduces the difficulty of etching the passivation layer; on the other hand, it can also provide better protection for the part of the semiconductor device in the terminal region NAA2, preventing moisture and other substances from entering the semiconductor body 100 in the terminal region NAA2.

[0040] Optionally, continue to refer to Figure 1 The semiconductor device also includes a protective layer 83, which covers the passivation layer 82 and contacts the nitride layer 822. In this embodiment, the protective layer 83 can be polyimide. The protective layer 83 provides physical buffer protection for the semiconductor device, so that when the semiconductor device is subjected to external impact, the impact energy is preferentially absorbed by the protective layer 83, avoiding damage to the semiconductor device. The protective layer 83 is in direct contact with the nitride layer 822. That is to say, the passivation layer 82 in this embodiment only includes two film layers: an oxide layer 821 and a nitride layer 822. When preparing the passivation layer, only a small number of film layer structures need to be prepared, thus reducing process costs and improving production efficiency.

[0041] Optionally, in some embodiments, oxide layer 821 may include silicon dioxide; nitride layer 822 may include silicon nitride.

[0042] Optionally, continue to refer to Figure 1 The semiconductor device also includes a source metal 74 located in the cell region AA, which is connected to the source lead metal 812. The passivation layer 82 also includes a sidewall located on the sidewall of the source metal 74 near the transition region NAA1, hereinafter defined as the second sidewall. The second sidewall exists only on the sidewall of the source metal 74, and no passivation layer is provided on the top of the source metal 74. The passivation layer can be formed using only the sidewall process, thereby reducing the etching difficulty. The second sidewall can also protect the sidewall and bottom corner of the source metal 74, preventing moisture from penetrating into the semiconductor body along the surface of the source metal 74 and the dielectric layer 73.

[0043] Optionally, continue to refer to Figure 1 The semiconductor device also includes a drain 90, which is located on the second surface 102.

[0044] Based on the same inventive concept, this invention also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any embodiment of this invention. For example... Figure 2 As shown, Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. The method includes: Step S110: Provide a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; Specifically, the semiconductor body can be formed epitaxially, and multiple conductive regions are provided in the semiconductor body. The conductive regions can be formed by means of ion implantation or other methods.

[0045] Step S120: Form a metal structure located in the transition region and on the side of the first surface away from the second surface. The metal structure includes at least one of gate metal and source lead metal. Specifically, a metal structure can be fabricated on the semiconductor body, and the metal structure can be prepared through processes such as metal sputtering. The gate metal is used to provide the gate signal required by the semiconductor device, while the source lead metal is used to lead out the source metal of the semiconductor device and provide the source signal.

[0046] Step S130: A passivation layer is formed, which extends from the terminal region to the transition region and covers the metal structure. The passivation layer includes an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface. The passivation layer includes a sidewall located on the sidewall of the metal structure, and an opening through the passivation layer is formed between two adjacent sidewalls.

[0047] Specifically, by creating openings in the passivation layer, external stress transmitted to the passivation layer is released at these openings, thus preventing passivation layer fracture and improving the reliability of semiconductor devices. The presence of openings between any two sidewalls further facilitates stress release at the corners of the passivation layer, thereby reducing the risk of passivation layer fracture and improving the reliability of semiconductor devices.

[0048] The technical solution of this embodiment employs a semiconductor device fabrication method comprising: providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; forming a metal structure, the metal structure being located in a transition region and on the side of the first surface away from the second surface, the metal structure including at least one of a gate metal and a source lead metal; forming a passivation layer, the passivation layer extending from the termination region to the transition region, the passivation layer covering the metal structure, the passivation layer including an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface; the passivation layer including sidewalls located on the sidewalls of the metal structure, with an opening formed between two adjacent sidewalls penetrating the passivation layer. By creating an opening in the passivation layer, when external stress is transmitted to the passivation layer, it will be released at the opening, thereby preventing the passivation layer from fracturing and improving the reliability of the semiconductor device. The presence of an opening between any two sidewalls makes it easier for stress at each corner of the passivation layer to be released, thereby further reducing the risk of passivation layer fracturing and improving the reliability of the semiconductor device.

[0049] Optionally, Figures 3 to 17This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention. (Reference) Figure 3 The method for fabricating a semiconductor device includes: firstly, epitaxially forming a first epitaxial layer on a substrate 10; then, as... Figure 4 As shown, a second epitaxial layer is epitaxially grown on the first epitaxial layer; then as... Figure 5 As shown, a first region 60, a well region 50, a fifth region 40, a fourth region 84, and a field-limiting ring 85 are formed by ion implantation. At this point, the step of providing the semiconductor body is complete. Then, as... Figure 6 As shown, the gate trench 72 is formed by dry etching. Then, as... Figure 7 As shown, silicon dioxide is deposited on the first surface 101 and a field oxygen structure 76 is formed by mask etching. Then, as... Figure 8 As shown, a gate oxide layer 71 is formed by thermal oxidation, and a gate 721 and a gate line layer 75 are fabricated. Then, as... Figure 9 As shown, a dielectric layer 73 is deposited, and contact holes are formed by photolithography; these contact holes are used for subsequent contact between the gate metal and the gate line layer. Then, as... Figure 10 As shown, metal materials are deposited and photolithography is used to form source metal 74, gate metal 811, and source lead metal 812. Then, a passivation layer is formed.

[0050] Optionally, forming a passivation layer includes: forming an oxide layer and a nitride layer that cover the entire surface; Specifically, such as Figure 11 As shown, full-area coverage can be formed using PECVD (Plasma Enhanced Chemical Vapor Deposition). Figure 10 The oxide layer 821 on the surface of the structure shown. Then as... Figure 12 As shown, a nitride layer 822 covering the entire surface is then formed by methods such as PECVD.

[0051] A mask layer is formed that extends from the terminal region to the transition region and terminates at the top of the metal structure near the terminal region. Specifically, such as Figure 13 As shown, a mask layer 201 can be formed on the entire surface first, and the mask layer 201 can be a photoresist. Then, as... Figure 14 As shown, by exposing and developing the mask layer 201, the mask layer 201 is stopped at the top of the source lead metal 812. That is, the portion of the mask layer 201 located near the terminal region at the stop position is retained, while the other portion is removed.

[0052] Using a mask layer as a mask, the oxide layer and nitride layer not covered by the mask layer are etched to form a passivation layer.

[0053] Specifically, such as Figure 15 As shown, the nitride layer 822 and the oxide layer 821 can be dry-etched sequentially to partially remove the passivation layer. Then, as... Figure 16 As shown, mask layer 201 is removed. The passivation layer at this point forms the corresponding sidewalls and openings. This embodiment uses a sidewall etching process, which can form the sidewalls and corresponding openings in one step without needing to create precise openings on the mask layer. This greatly simplifies the process flow and reduces the fabrication cost of semiconductor devices.

[0054] Optionally, after forming the passivation layer, the process further includes forming a protective layer that covers and contacts the nitride layer.

[0055] Specifically, such as Figure 17 As shown, in this embodiment, the protective layer 83 is in direct contact with the nitride layer 822. That is to say, the passivation layer 82 in this embodiment only includes two film layers: the oxide layer 821 and the nitride layer 822. When preparing the passivation layer, only a small number of film layer structures need to be prepared, thus reducing the process cost and improving the production efficiency.

[0056] Optionally, after forming the protective layer, the process further includes: grinding the second surface and forming a drain electrode on the second surface. The final result is as follows: Figure 1 The structure shown.

[0057] Based on the same inventive concept, the present invention also provides a power module. The power module includes a substrate and at least one semiconductor device as described in any embodiment of the present invention, with the substrate serving to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of the present invention will not be elaborated further here.

[0058] Based on the same inventive concept, this invention also provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, with the semiconductor device electrically connected to the circuit board. Therefore, the beneficial effects of this power conversion circuit including any semiconductor device as described in any embodiment of this invention will not be elaborated further here.

[0059] Based on the same inventive concept, the present invention also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert alternating current to direct current, alternating current to alternating current, direct current to direct current, or direct current to alternating current, and then input the converted direct current to the load. Therefore, the beneficial effects of the vehicle including the semiconductor device described in any embodiment of the present invention will not be elaborated further here.

[0060] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0061] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0062] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a cell region, a transition region, and a termination region; the transition region surrounds the cell region, and the termination region surrounds the transition region; the semiconductor device includes: The semiconductor body includes a first surface and a second surface disposed opposite to each other; A metal structure is located in the transition region and on the side of the first surface away from the second surface, the metal structure comprising at least one of gate metal and source lead metal; A passivation layer extends from the terminal region to the transition region, covering the metal structure. The passivation layer includes an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface. The passivation layer includes sidewalls located on the sidewalls of the metal structure, with an opening forming between two adjacent sidewalls that penetrates the passivation layer.

2. The semiconductor device according to claim 1, characterized in that, The metal structure includes the gate metal and the source lead metal located on the side of the gate metal away from the cell region; The sidewall located on the side of the source lead metal away from the cell region extends to the side of the source lead metal away from the first surface.

3. The semiconductor device according to claim 2, characterized in that, The passivation layer forms a continuous surface in the portion of the terminal region.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a protective layer that covers the passivation layer and contacts the nitride layer.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a source metal located in the cell region, the source metal being connected to the source lead metal; the passivation layer further includes a sidewall located on the sidewall of the source metal near the transition region.

6. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a cell region, a transition region, and a termination region; the transition region surrounds the cell region, and the termination region surrounds the transition region; The method for fabricating the semiconductor device includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; A metal structure is formed, the metal structure being located in the transition region and on the side of the first surface away from the second surface, the metal structure comprising at least one of gate metal and source lead metal; A passivation layer is formed, the passivation layer extending from the terminal region to the transition region, the passivation layer covering the metal structure, the passivation layer including an oxide layer and a nitride layer located on the side of the oxide layer away from the first surface; the passivation layer includes sidewalls located on the sidewalls of the metal structure, and an opening penetrating the passivation layer is formed between two adjacent sidewalls.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The formation of the passivation layer includes: Forming an oxide layer and a nitride layer that cover the entire surface; A mask layer is formed that extends from the terminal region to the transition region and terminates near the top of the metal structure near the terminal region; Using the mask layer as a mask, the oxide layer and the nitride layer not covered by the mask layer are etched to form the passivation layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The process of forming the passivation layer further includes forming a protective layer that covers and contacts the nitride layer.

9. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-5, wherein the substrate is used to support the semiconductor device.

10. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-5, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 10, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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