A single-event effect resistant VDMOS device and a manufacturing method thereof

Abstract

The application relates to an anti-single-particle-effect VDMOS device and a manufacturing method thereof. The VDMOS device comprises a composite gate oxide structure arranged between an epitaxial layer and a polysilicon layer, and the composite gate oxide structure comprises a bottom gate oxide layer, a silicon nitride layer and a local thick oxide layer; the bottom gate oxide layer is located on the epitaxial layer; the silicon nitride layer covers the bottom gate oxide layer; the local thick oxide layer covers part of the surface of the silicon nitride layer; and the polysilicon layer is located on the local thick oxide layer and extends to the surface of the silicon nitride layer at the end. According to the embodiment of the application, the local thick oxide layer is arranged, so that the anti-single-particle gate penetration capability is remarkably improved without sacrificing the electrical performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor radiation hardening, specifically relating to a VDMOS device resistant to single-event effects and its fabrication method. Background Technology

[0002] Outer space contains a large amount of X-rays, gamma rays, neutrons, heavy particles, etc. Spacecraft operating in space are exposed to radiation from these rays and particles, causing disturbances in the spacecraft's electronic systems and even leading to their failure, seriously affecting the safe operation of the spacecraft in orbit. Vertical double-diffused-metal-Oxide-semiconductor field-effect transistors (VDMOS) are one of the core components of satellite secondary DC / DC (Direct Current-Direct Current) power supplies. They play a role in power conversion or power transformation in the power system, providing the necessary energy for the normal operation of satellite electronic systems. X-ray and gamma-ray radiation power VDMOS devices mainly experience the total dose effect of ionizing radiation, causing device parameter drift. Neutron radiation power VDMOS devices mainly cause an increase in device power consumption, which can be addressed through redundancy design. However, heavy particle radiation power VDMOS devices are susceptible to single-event gate breakdown (SEGR) and single-event burnout (SEB) effects, leading to device failure and rendering the electronic system inoperable. In particular, for power VDMOS devices manufactured using micron / submicron processes and planar structures, single-event radiation hardening has become one of the bottlenecks and shortcomings restricting the development of satellite power technology, information security control, and the self-sufficiency of core components.

[0003] In traditional single-layer gate oxide (STO) VDMOS devices operating at high / ultra-high voltage, single-particle incident radiation can easily generate a transient strong electric field, directly breaking down the gate oxide and becoming a major cause of satellite power supply failures. Conventional STO VDMOS devices can be hardened by adjusting the doping of the P-body, N-source, and JFET regions, which can improve their radiation resistance to some extent. However, for high-voltage and ultra-high-voltage power VDMOS devices, such as 600V VDMOS, existing hardening measures are limited by the gate oxide layer's inherent capabilities and cannot meet the requirements for single-event gate breakdown (SEGR). Furthermore, existing hardening measures can negatively impact the performance of the power VDMOS device itself, such as on-resistance and conduction losses, necessitating further optimization.

[0004] Therefore, overcoming the shortcomings of existing VDMOS, such as insufficient single-event gate breakdown resistance, difficulty in high-voltage hardening, increased on-resistance after hardening, and increased cost, has become an urgent technical problem to be solved. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a VDMOS device resistant to single-event effects and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a VDMOS device resistant to single-event effects, comprising: a composite gate oxide structure disposed between an epitaxial layer and a polysilicon layer, wherein the composite gate oxide structure comprises: a bottom gate oxide layer, a silicon nitride layer, and a locally thick oxide layer; The bottom gate oxide layer is located on the epitaxial layer; The silicon nitride layer covers the bottom gate oxide layer; the locally thick oxide layer covers a portion of the surface of the silicon nitride layer; the polysilicon layer is located on the locally thick oxide layer and extends to the surface of the silicon nitride layer.

[0006] In one embodiment of the present invention, the localized thick oxide layer is located in the central region beneath the polycrystalline silicon layer.

[0007] In one embodiment of the present invention, the width of the local thick oxide layer is 1 / 3 to 1 / 2 of the width of the polycrystalline silicon layer.

[0008] In one embodiment of the present invention, the thickness of the bottom gate oxide layer is 50-120 nm, and the thickness of the silicon nitride layer is 10-40 nm; The material of the locally thick oxide layer includes silicon dioxide.

[0009] In one embodiment of the present invention, it further includes: a substrate, a buffer layer, an epitaxial layer, a body region, a contact hole doped region, a source doped region, a polysilicon layer, an interlayer dielectric layer, a front metal layer, and a back metal layer; The substrate, the buffer layer, and the epitaxial layer are stacked sequentially. The body region is formed in the epitaxial layer; the contact hole doped region and the source doped region are formed in the body region and are in contact with each other; The bottom gate oxide layer is located on the epitaxial layer, and both ends extend to cover a portion of the body region and a portion of the source doped region; The interlayer dielectric layer covers a portion of the surface of the epitaxial layer, the polysilicon layer, and the source doped region, and contact holes are formed in the interlayer dielectric layer; The front metal layer is located on the interlayer dielectric layer and is in contact with a portion of the body region, the contact hole doped region, and a portion of the source doped region through the contact hole; The back metal layer is located on the other surface of the substrate.

[0010] In one embodiment of the invention, a JFET region is further included, the JFET region being formed in an epitaxial layer between the body regions.

[0011] In one embodiment of the present invention, the VDMOS device is either an N-channel VDMOS device or a P-channel VDMOS device.

[0012] Another embodiment of the present invention provides a method for fabricating a VDMOS device resistant to single-event effects, comprising the steps of: First, gate oxide is oxidized on the surface of the epitaxial layer to form the bottom gate oxide layer; Silicon nitride is deposited on the bottom gate oxide layer to form a silicon nitride layer; A thick gate oxide layer is deposited on the silicon nitride layer, and photoresist is spin-coated on the obtained wafer surface. The wafer is exposed and developed using a mask of the polysilicon layer to obtain a polysilicon region pattern window. Then, the thick gate oxide layer in the polysilicon region pattern window is wet-etched to etch the thick gate oxide layer to a preset width to obtain the local thick oxide layer.

[0013] In one embodiment of the present invention, the step further includes: A buffer layer and an epitaxial layer are grown sequentially on the substrate; A bulk region is prepared in the epitaxial layer; A composite gate oxide structure is fabricated on the epitaxial layer; wherein the composite gate oxide structure includes the bottom gate oxide layer, the silicon nitride layer, and the locally thick oxide layer; the bottom gate oxide layer is located on the epitaxial layer, and both ends extend to cover a portion of the body region; A polycrystalline silicon layer is prepared on the sample surface, the polycrystalline silicon layer being located on the locally thick oxide layer and extending to the surface of the silicon nitride layer at its ends; Ion implantation is performed in the bulk region to form a source-doped region; An interlayer dielectric layer is prepared on the sample surface, and contact holes are etched in the interlayer dielectric layer. Ions are implanted through the contact holes in the bulk region to form a contact hole doped region, which is in contact with the source doped region. A front metal layer is formed on the interlayer dielectric layer, and the front metal layer contacts a portion of the body region, a doped region of the contact hole, and a portion of the source doped region through a contact hole on the interlayer dielectric layer. A back metal layer is formed on the other surface of the substrate.

[0014] In one embodiment of the present invention, before fabricating the body region in the epitaxial layer, the step further includes: Ion implantation is performed in the epitaxial layer between the body regions to form JFET regions.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. In the VDMOS device of this invention, by setting a locally thick oxide layer below the polysilicon layer, the electric field strength borne by the gate oxide after a single particle incident can be greatly reduced, thereby improving the device's resistance to single-particle gate breakdown and significantly reducing the probability of single-particle gate breakdown. This effectively solves the technical problem of gate oxide breakdown in high-voltage and ultra-high-voltage applications in existing technologies. Simultaneously, since the locally thick oxide layer is only located in a portion of the polysilicon layer and does not affect the channel region, the conventional electrical parameters of the device, such as on-resistance, threshold voltage, and switching speed, are essentially unaffected. This achieves a balance between radiation hardening and electrical performance, avoiding the problem of increased on-resistance caused by adjusting the doped region for hardening in existing technologies. Therefore, this invention significantly improves the resistance to single-particle gate breakdown without sacrificing electrical performance by setting a locally thick oxide layer. 2. In the fabrication method of the present invention, there is no need to increase the cost of the photomask. The existing polysilicon layer photomask is used as the mask. When etching the thick oxide, silicon nitride can act as a barrier layer to prevent the etching of the lower gate oxide. Without adding special processes, the local thickening of the gate oxide is achieved, and the radiation resistance of the device is improved without increasing the cost. It is compatible with the existing VDMOS process flow and can be directly produced on existing production lines. It has obvious cost advantages and strong process compatibility. Attached Figure Description

[0016] Figure 1 A schematic diagram of a VDMOS device resistant to single-event effects provided in an embodiment of the present invention; Figure 2 A schematic flowchart illustrating a method for fabricating a VDMOS device resistant to single-event effects, provided in an embodiment of the present invention. Figure 3 A schematic diagram illustrating the process of fabricating a VDMOS device resistant to single-event effects, as provided in an embodiment of the present invention. Figure 4 This is a comparison of the gate oxide electric field (lateral) at the same moment after a single particle is incident from 1.5 μm under the same bias conditions between a conventional device and a locally thick oxide device in this embodiment. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Example 1 Please see Figure 1 , Figure 1This is a schematic diagram of a VDMOS device resistant to single-event effects provided in an embodiment of the present invention. The VDMOS device includes: a substrate 1, a buffer layer 2, an epitaxial layer 3, a body region 4, a contact hole doped region 5, a source doped region 6, a bottom gate oxide layer 7, a silicon nitride layer 8, a locally thick oxide layer 9, a polysilicon layer 10, an interlayer dielectric layer 11, a front metal layer 12, and a back metal layer 13.

[0019] Substrate 1, buffer layer 2, and epitaxial layer 3 are stacked sequentially; body region 4 is formed in epitaxial layer 3; contact hole doped region 5 and source doped region 6 are formed in body region 4 and are in contact with each other; bottom gate oxide layer 7 is located on epitaxial layer 3 and extends at both ends to cover a portion of body region 4 and a portion of source doped region 6; silicon nitride layer 8 covers bottom gate oxide layer 7; locally thick oxide layer 9 covers a portion of surface of silicon nitride layer 8; polysilicon layer 10 is located on locally thick oxide layer 9 and extends at its ends to surface of silicon nitride layer 8. Interlayer dielectric layer 11 covers a portion of surface of epitaxial layer 3, polysilicon layer 10, and source doped region 6, and contact holes are formed in interlayer dielectric layer 11; front metal layer 12 is located on interlayer dielectric layer 11 and contacts a portion of body region 4, contact hole doped region 5, and a portion of source doped region 6 through contact holes in interlayer dielectric layer 11; back metal layer 13 is located on the other surface of substrate 1.

[0020] Specifically, buffer layer 2 can be formed by stacking several sub-buffer layers with different doping concentrations and thicknesses to improve SEB capability. Epitaxial layer 3 has a certain thickness and doping concentration to achieve basic breakdown voltage and other electrical parameters. Body region 4 is disposed on both sides of the top of epitaxial layer 3 and extends from the surface of epitaxial layer 3 to its interior. Contact hole doped region 5 and source doped region 6 extend from the surface of body region 4 to its interior. Body region 4, contact hole doped region 5, and source doped region 6 are all formed by ion implantation. Bottom gate oxide layer 7 extends from one source doped region 6 in body region 4 to another source doped region 6 in body region 4. Silicon nitride layer 8 completely covers bottom gate oxide layer 7, and locally thick oxide layer 9 partially covers silicon nitride layer 8. Polysilicon layer 10 covers the surface and two sides of locally thick oxide layer 9 and is located on the surface of uncovered silicon nitride layer 8. An interlayer dielectric layer 11 covers the surface of the device, and contact holes are provided in the interlayer dielectric layer 11 to expose a portion of the body region 4, the contact hole doped region 5, and a portion of the source doped region 6. The front metal layer 12 forms ohmic contacts with the body region 4, the contact hole doped region 5, and the source doped region 6 simultaneously through the contact holes, realizing a short circuit between the source and the body regions. The back metal layer 13 serves as the drain, providing the drain electrode for the device.

[0021] A composite gate oxide structure is formed by the bottom gate oxide layer 7, the silicon nitride layer 8, and the locally thick oxide layer 9. The bottom gate oxide layer 7 serves as the traditional gate oxide dielectric, ensuring the device's basic electrical parameters such as threshold voltage. The silicon nitride layer 8 covers the bottom gate oxide layer 7 and acts as a barrier layer during subsequent etching of the locally thick oxide layer 9, preventing the etching solution from damaging the bottom gate oxide layer 7 and thus ensuring the integrity and reliability of the gate oxide. The locally thick oxide layer 9 is located in a region below the polysilicon layer 10, specifically at the location with the strongest electric field corresponding to the gate region, while not affecting the channel region.

[0022] In one specific embodiment, the local thick oxide layer 9 is located in the central region below the polysilicon layer 10, and the width of the local thick oxide layer 9 is 1 / 3 to 1 / 2 of the width of the polysilicon layer 10.

[0023] The central region beneath the polysilicon layer 10 has the most concentrated gate oxide electric field intensity during single-particle incident. Setting a local thick oxide layer 9 can more effectively reduce the electric field intensity borne by the gate oxide after single-particle incident, thereby improving the device's resistance to single-particle gate penetration.

[0024] Specifically, the bottom gate oxide layer 7 has a thickness of 50-120 nm, and the silicon nitride layer 8 has a thickness of 10-40 nm; the material of the locally thick oxide layer includes silicon dioxide.

[0025] Specifically, substrate 1 includes a Si substrate with a thickness of 715~735 μm and a resistivity of 0.002~0.006 Ω·cm; substrate 1 can be a heavily doped N-type Si substrate. The buffer layer 2 can have 2~5 layers in total, with a total thickness of 20~50 μm and a resistivity of 0.01~0.5 Ω·cm. The epitaxial layer 3 can have 2~5 layers in total, with a total thickness of 5~25 μm and a resistivity of 1~10 Ω·cm. The front metal layer 12 is made of Al and has a thickness of 4~6 μm; the back metal layer 13 is made of Ti / Ni / Ag and has a thickness of 5~10 μm.

[0026] In one specific embodiment, the VDMOS device resistant to single-event effects further includes a junction field-effect transistor region (JFET). The JFET region is formed by ion implantation in the epitaxial layer 3 between the bulk regions 4, extending from the surface of the epitaxial layer 3 to its interior. By setting the JFET region in this embodiment, the base resistance can be reduced, thereby decreasing the threshold for parasitic transistor turn-on.

[0027] In one specific embodiment, the VDMOS device is either an N-channel VDMOS device or a P-channel VDMOS device.

[0028] Specifically, for an N-channel VDMOS device, substrate 1, buffer layer 2, and epitaxial layer 3 are N-type doped, body region 4 is a P-doped region, contact via doped region 5 is a P+ doped region, and source doped region 6 is an N+ doped region. For a P-channel VDMOS device, substrate 1, buffer layer 2, and epitaxial layer 3 are P-type doped, body region 4 is an N-doped region, contact via doped region 5 is an N+ doped region, and source doped region 6 is a P+ doped region.

[0029] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic flowchart illustrating a method for fabricating a VDMOS device resistant to single-event effects according to an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating a method for fabricating a VDMOS device resistant to single-event effects, as provided in an embodiment of the present invention. The fabrication method uses an N-channel VDMOS device as an example and specifically includes the following steps: S1. A buffer layer 2 and an epitaxial layer 3 are grown sequentially on a substrate 1.

[0030] Specifically, substrate 1 is first selected to provide support for subsequent processes. Substrate 1 includes a Si substrate with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω·cm. For example, a heavily doped N-type Si substrate is selected as substrate 1.

[0031] Then, several buffer layers 2 with different doping concentrations and thicknesses can be grown on the upper surface of the substrate 1 to improve the SEB capability. For example, the resistivity of the buffer layer 2 is 0.01~0.5Ω·cm, the total thickness of the buffer layer is 20~50μm, and the number of buffer layers 2 is 2~5.

[0032] Finally, a voltage-resistant epitaxial layer 3 of a certain thickness and doping concentration is grown on the buffer layer 2 to achieve the basic voltage-resistant isoelectric parameters. For example, the resistivity of the epitaxial layer 3 is 1~10 Ω·cm, the total thickness of the epitaxial layer 3 is 5-25 μm, and the number of epitaxial layers 3 is 2~5.

[0033] S2. Photolithography, implantation and push-junction are performed in epitaxial layer 3 to prepare body region 4 to match threshold voltage parameters.

[0034] Specifically, photoresist is spin-coated onto the upper surface of the sample, followed by exposure and development using a mask to obtain a P-body pattern window. Boron ions are then implanted within the P-body pattern window to obtain the P-body region. For example, the implantation energy is 100~300 keV, and the implantation dose is 1×10⁻⁶. 12 ~9×10 13 ion·cm -2 .

[0035] S3. A composite gate oxide structure is fabricated on the epitaxial layer 3. The composite gate oxide structure includes a bottom gate oxide layer 7, a silicon nitride layer 8, and a locally thick oxide layer 9. The bottom gate oxide layer 7 is located on the epitaxial layer 3 and extends to cover a portion of the body region 4 at both ends.

[0036] Step S3 specifically includes: S31. Gate oxide is first oxidized on the surface of epitaxial layer 3 to form bottom gate oxide layer 7; the material of bottom gate oxide layer 7 includes silicon dioxide.

[0037] S32. Deposit silicon nitride on the bottom gate oxide layer 7 to form a silicon nitride layer 8. The function of silicon nitride is to block thick oxide etching and prevent damage to the bottom gate oxide.

[0038] S33. A thick gate oxide layer is deposited on the silicon nitride layer 8; the material of the thick gate oxide layer includes silicon dioxide.

[0039] S33. Photoresist is spin-coated onto the wafer surface where a thick gate oxide layer is obtained. Exposure and development are performed using a mask of the polysilicon layer to obtain a polysilicon region pattern window. Then, wet etching is performed on the thick gate oxide layer within the polysilicon region pattern window to etch the thick gate oxide layer to a preset width, resulting in a localized thick oxide layer 9. Because silicon dioxide is isotropic, both sides of the silicon dioxide are etched simultaneously, thus retaining a thick gate oxide layer in the central region, forming a localized thick oxide layer 9 in the central region below the polysilicon. This region corresponds to the area with the strongest electric field after a single particle incident.

[0040] For example, the thickness of the bottom gate oxide layer 7 is 50-120 nm, the thickness of the silicon nitride layer 8 is 10-40 nm, the thickness of the thick gate oxide layer before etching is 300-500 nm, the width of the thick gate oxide layer etched away on each side is 1 / 4-1 / 3 of the width of the entire polysilicon layer 10, the width of the thick gate oxide layer etched away on both sides is 1 / 2-2 / 3 of the width of the entire polysilicon layer 10, and the width of the remaining local thick oxide layer 9 is 1 / 3-1 / 2 of the width of the polysilicon layer 10.

[0041] In this embodiment, when performing photolithography and etching of composite gate oxide to form a composite gate oxide structure with localized thick oxide, a polysilicon photomask is reused, without adding a photomask, resulting in good process compatibility and low cost.

[0042] S4. Polysilicon layer 10 is prepared by depositing, photolithography and etching on the sample surface. The polysilicon layer 10 is located on the local thick oxide layer 9 and extends to the surface of the silicon nitride layer 8.

[0043] Specifically, polysilicon is deposited on the sample surface obtained in step S3, and exposed and developed using a mask to obtain a polysilicon layer pattern window. Then, dry etching is performed to remove excess polysilicon and leave the required polysilicon layer.

[0044] S5. In the bulk region 4, photolithography, implantation and push-junction of the source doped region are performed to form the source doped region 6.

[0045] Specifically, photoresist is spin-coated onto the sample surface obtained in step S5, and then exposed and developed using a mask to obtain source doped region pattern windows located on each P-body region. Arsenic ions are then implanted into each source doped region pattern window to form source doped region 6. Exemplarily, the implantation energy is 100~200 keV, and the implantation dose is 9×10⁻⁶. 14 ~5×10 15 ion·cm -2 .

[0046] S6. An interlayer dielectric layer 11 is prepared on the sample surface, and contact holes are etched in the interlayer dielectric layer. Ion implantation is performed in the bulk region 4 through the contact holes to form a contact hole doped region 5, which is in contact with the source doped region 6.

[0047] Specifically, in step S5, the sample growth interlayer dielectric layer 11 is obtained, and then photoresist is spin-coated onto the wafer surface. Exposure and development are performed using a mask to obtain the doped region pattern window of the contact hole area. Subsequently, contact holes are dry-etched, and BF2 ions are implanted into each contact hole doped region and activated to form the hole P+ region, resulting in contact hole doped region 5. Exemplarily, the implantation energy is 100~200 keV, and the implantation dose is 9×10⁻⁶. 14 ~5×10 15 ion·cm -2 .

[0048] S7. A front metal layer 12 is formed on the interlayer dielectric layer 11. The front metal layer 12 contacts a portion of the body region 4, a portion of the contact hole doped region 5, and a portion of the source doped region 6 through contact holes on the interlayer dielectric layer 11.

[0049] Specifically, source metal is deposited on the upper surface of the sample obtained in step S6 to form a front metal layer 12. For example, the source metal is Al with a thickness of 4~6 μm. After the source metal deposition is completed, photoresist is spin-coated on the obtained sample surface, and then exposed and developed using a mask to obtain a metal interconnect pattern window. The separation of the source metal layer and the gate electrode is completed according to the metal interconnect pattern window.

[0050] S8. A back metal layer 13 is formed on the other surface of the substrate 1.

[0051] Specifically, a drain metal layer is formed by depositing drain metal on the lower surface of substrate 1. For example, the deposited metals are Ti / Ni / Ag in sequence, and the thickness is 5~10μm.

[0052] In one specific embodiment, before fabricating the body region 4 in the epitaxial layer 3, the step further includes: Photolithography, ion implantation, and push-junction are performed in the epitaxial layer 3 between the bulk regions 4 to form the JFET region.

[0053] Specifically, photoresist is spin-coated onto the sample surface after the epitaxial layer is prepared. Then, exposure and development are performed using a mask to obtain a JFET implantation pattern window. Phosphorus ions are then implanted into the JFET implantation pattern window to form a JFET region, thereby reducing the base region resistance and decreasing the threshold for parasitic transistor turn-on. For example, the implantation energy is 200~400 keV, and the implantation dose is 2×10⁻⁶. 12 ~2×10 13 ion·cm -2 .

[0054] This embodiment further simulates the gate oxide electric field at the moment of strongest electric field after incident on conventional devices and locally thick oxide devices with particles of the same energy at the same location. The simulation results can be found in [link to simulation results]. Figure 4 , Figure 4 This image shows a comparison of the gate oxide electric field (lateral) at the same moment after a single particle is incident from a distance of 1.5 μm under the same bias conditions between a conventional device and the locally thick oxide device of this embodiment. The comparison reveals that the maximum gate oxide electric field of the conventional device is 1.25 × 10⁻⁶. 6 V / cm, the maximum electric field strength of the locally thick oxygen device in this embodiment is 3.02×10 V / cm. 5 With a voltage of V / cm, the peak field strength of the device in this embodiment is reduced by 75.8% after incident radiation through a localized thick oxide layer, which greatly reduces the probability of single-event gate penetration and significantly improves the device's single-event immunity.

[0055] In the VDMOS device of this invention, by setting a locally thick oxide layer below the polysilicon layer, the electric field strength borne by the gate oxide after a single particle incident can be greatly reduced, thereby improving the device's resistance to single-particle gate breakdown and significantly reducing the probability of single-particle gate breakdown. This effectively solves the technical problem of gate oxide breakdown in high-voltage and ultra-high-voltage applications in existing technologies. At the same time, since the locally thick oxide layer is only located in a part of the polysilicon layer and does not affect the channel region, the conventional electrical parameters of the device, such as on-resistance, threshold voltage, and switching speed, are basically unaffected. This achieves a balance between radiation hardening and electrical performance, avoiding the problem of increased on-resistance caused by adjusting the doping region for hardening in existing technologies. Therefore, this invention significantly improves the resistance to single-particle gate breakdown without sacrificing electrical performance by setting a locally thick oxide layer.

[0056] The fabrication method of this invention does not require additional photomask costs. It uses the existing polysilicon layer photomask as a mask. When etching thick oxide, silicon nitride can act as a barrier layer to prevent etching of the underlying gate oxide. Without adding special processes, it achieves localized thickening of the gate oxide and improves the radiation resistance of the device with virtually no increase in cost. It is compatible with the existing VDMOS process flow and can be directly produced on existing production lines. It has significant cost advantages and strong process compatibility.

[0057] The VDMOS device in this embodiment is suitable for VDMOS devices with a withstand voltage of 30V to 1200V, and is especially suitable for single-event hardening of high voltage and ultra-high voltage power VDMOS of 600V and above. It can be widely used in fields with stringent requirements for single-event reliability, such as satellite, aerospace, deep space exploration, military electronics, and radiation-resistant power supply systems.

[0058] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A VDMOS device resistant to single-event effects, characterized in that, include: A composite gate oxide structure is disposed between the epitaxial layer (3) and the polysilicon layer (10), the composite gate oxide structure comprising: a bottom gate oxide layer (7), a silicon nitride layer (8) and a locally thick oxide layer (9); The bottom gate oxide layer (7) is located on the epitaxial layer (3); The silicon nitride layer (8) covers the bottom gate oxide layer (7); the local thick oxide layer (9) covers a portion of the surface of the silicon nitride layer (8); the polysilicon layer (10) is located on the local thick oxide layer (9) and extends to the surface of the silicon nitride layer (8).

2. The VDMOS device resistant to single-event effects according to claim 1, characterized in that, The localized thick oxide layer (9) is located in the central region below the polycrystalline silicon layer (10).

3. The VDMOS device resistant to single-event effects according to claim 1, characterized in that, The width of the local thick oxide layer (9) is 1 / 3 to 1 / 2 of the width of the polycrystalline silicon layer (10).

4. The VDMOS device resistant to single-event effects according to claim 1, characterized in that, The thickness of the bottom gate oxide layer (7) is 50-120 nm, and the thickness of the silicon nitride layer (8) is 10-40 nm; The material of the locally thick oxide layer (9) includes silicon dioxide.

5. The VDMOS device resistant to single-event effects according to claim 1, characterized in that, Also includes: Substrate (1), buffer layer (2), epitaxial layer (3), body region (4), contact hole doped region (5), source doped region (6), polysilicon layer (10), interlayer dielectric layer (11), front metal layer (12) and back metal layer (13); The substrate (1), the buffer layer (2), and the epitaxial layer (3) are stacked sequentially; The body region (4) is formed in the epitaxial layer (3); the contact hole doped region (5) and the source doped region (6) are formed in the body region (4) and are in contact with each other; The bottom gate oxide layer (7) is located on the epitaxial layer (3), and both ends extend to cover a portion of the body region (4) and a portion of the source doped region (6); The interlayer dielectric layer (11) covers part of the surface of the epitaxial layer (3), the polysilicon layer (10) and the source doped region (6), and contact holes are formed in the interlayer dielectric layer (11); The front metal layer (12) is located on the interlayer dielectric layer (11) and is in contact with a portion of the body region (4), the contact hole doped region (5), and a portion of the source doped region (6) through the contact hole; The back metal layer (13) is located on the other surface of the substrate (1).

6. The VDMOS device resistant to single-event effects according to claim 5, characterized in that, It also includes a JFET region formed in the epitaxial layer (3) between the body regions (4).

7. The VDMOS device resistant to single-event effects according to claim 1, characterized in that, The VDMOS device is either an N-channel VDMOS device or a P-channel VDMOS device.

8. A method for fabricating a VDMOS device resistant to single-event effects, characterized in that, Including the following steps: Gate oxide is first applied to the surface of the epitaxial layer (3) to form a bottom gate oxide layer (7); Silicon nitride is deposited on the bottom gate oxide layer (7) to form a silicon nitride layer (8); A thick gate oxide layer is deposited on the silicon nitride layer (8), and photoresist is spin-coated on the obtained wafer surface. The polysilicon layer is exposed and developed using a mask to obtain a polysilicon region pattern window. Then, the thick gate oxide layer in the polysilicon region pattern window is wet-etched to etch the thick gate oxide layer to a preset width to obtain the local thick oxide layer (9).

9. The method for fabricating a VDMOS device resistant to single-event effects according to claim 8, characterized in that, It also includes the following steps: A buffer layer (2) and an epitaxial layer (3) are sequentially grown on a substrate (1); A body region (4) is prepared in the epitaxial layer (3); A composite gate oxide structure is fabricated on the epitaxial layer (3); wherein the composite gate oxide structure includes the bottom gate oxide layer (7), the silicon nitride layer (8) and the local thick oxide layer (9); the bottom gate oxide layer (7) is located on the epitaxial layer (3) and extends at both ends to cover a portion of the body region (4); A polycrystalline silicon layer (10) is prepared on the sample surface, the polycrystalline silicon layer (10) being located on the locally thick oxide layer (9) and extending to the surface of the silicon nitride layer (8) at its ends; Ion implantation is performed in the body region (4) to form a source doped region (6); An interlayer dielectric layer (11) is prepared on the sample surface, and contact holes are etched in the interlayer dielectric layer. Ions are implanted in the body region (4) through the contact holes to form a contact hole doped region (5). The contact hole doped region (5) is in contact with the source doped region (6). A front metal layer (12) is formed on the interlayer dielectric layer (11), and the front metal layer (12) contacts a portion of the body region (4), a portion of the contact hole doped region (5), and a portion of the source doped region (6) through a contact hole on the interlayer dielectric layer (11); A back metal layer (13) is formed on the other surface of the substrate (1).

10. The method for fabricating a VDMOS device resistant to single-event effects according to claim 9, characterized in that, Before fabricating the bulk region (4) in the epitaxial layer (3), the following steps are also included: Ion implantation is performed in the epitaxial layer (3) between the body regions (4) to form JFET regions.

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