Local insulation si / sic hetero-interface coupled step floating island VDMOS and manufacturing method thereof

Abstract

The application discloses a local insulation Si / SiC heterojunction coupling step floating island VDMOS and a manufacturing method thereof. In the VDMOS, a Si / SiC heterojunction between an N-type silicon drift region and an N-type 4H-SiC field expansion layer is provided with a Si / SiC direct contact conductive window composed of an N+ type silicon interface transition region and an N+ type silicon carbide interface transition region, and lateral sides of the Si / SiC direct contact conductive window are provided with embedded medium field adjusting regions; a plurality of P-type silicon floating charge compensation regions are arranged in the N-type silicon drift region, lateral sizes of the P-type silicon floating charge compensation regions gradually decrease, and effective compensation charges gradually decrease; a last-stage floating charge compensation region and the embedded medium field adjusting region longitudinally project at least partially overlap, and a distance d0 from the last-stage floating charge compensation region to the heterojunction is less than a minimum longitudinal distance d1 between the last-stage floating charge compensation region and an adjacent upper-stage floating charge compensation region. The application considers longitudinal low-resistance conduction, heterojunction electric field modulation and low bonding thermal budget.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor devices and heterogeneous integration technology, specifically relating to a locally insulated Si / SiC heterogeneous interface coupled stepped floating island VDMOS and its fabrication method. Background Technology

[0002] In reverse blocking mode, VDMOS relies on the drift region to withstand the drain-source voltage. Increasing the breakdown voltage usually requires reducing the doping concentration of the drift region and increasing the drift region thickness, which increases the specific on-resistance. Floating islands or charge compensation blocks can form multiple auxiliary PN junctions and additional electric field peaks in the drift region, making the longitudinal electric field more uniform. However, uniform-sized compensation blocks will continuously occupy the conductive cross-section, while non-uniform compensation blocks need to balance the peak electric fields at each stage and the channel width.

[0003] Existing methods also propose using wide bandgap materials such as silicon carbide to form the substrate and drift region, and setting multiple P-type compensation blocks in the silicon carbide drift region; another method forms or bonds a silicon active layer on the wide bandgap drift layer, so that the channel is located in the silicon material. The above methods can utilize the high critical breakdown electric field of silicon carbide, but their P-type compensation regions are usually formed within the silicon carbide drift region, involving multiple silicon carbide epitaxy, P-type ion implantation and high-temperature activation, and the process thermal budget and doping activation control are relatively strict.

[0004] If only the drain substrate of the silicon-based stepped floating island VDMOS is replaced with a silicon carbide substrate, the band steps, bonding defects, and dielectric constant differences at the silicon / silicon carbide interface may cause additional on-state voltage drop, interface leakage, or local electric field concentration. Conversely, if a dielectric layer is placed across the entire interface, it will block the longitudinal main current. While adding a highly doped layer at the interface can reduce contact resistance, it cannot simultaneously define the relative positions of the dielectric edge field and the depletion region of the final floating island. Therefore, it is necessary to maintain a low-resistance longitudinal conductive path while ensuring a detectable spatial coupling relationship between the interface transition region, the local dielectric, the final floating island, and the silicon carbide field-carrying layer. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this application provides a locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS and its fabrication method. The technical problem to be solved by this application is achieved through the following technical solution: In a first aspect, this application provides a locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS comprising: an N+ type 4H-SiC substrate, an N-type 4H-SiC field extension layer located on the N+ type 4H-SiC substrate, an N-type silicon drift region located on the N-type 4H-SiC field extension layer, a P-type base region formed in the upper region of the N-type silicon drift region, an N+ type source region and a P+ type body contact region formed in the P-type base region, a source electrode formed in the upper part of the P-type base region, a gate dielectric layer formed on the N-type silicon drift region, a gate electrode formed on the gate dielectric layer, and a drain electrode formed on the back side of the N+ type 4H-SiC substrate; The N-type silicon drift region and the N-type 4H-SiC field extension layer are separated by a Si / SiC heterojunction. An N+ type silicon interface transition region extending upwards to the N-type silicon drift region is provided along the Si / SiC heterojunction, and an N+ type silicon carbide interface transition region extending downwards into the N-type 4H-SiC field extension layer is provided along the Si / SiC heterojunction. The N+ type silicon interface transition region and the N+ type silicon carbide interface transition region constitute a Si / SiC direct contact conductive window. Buried dielectric field adjustment regions are provided on both sides of the Si / SiC direct contact conductive window. Within the N-type silicon drift region, multiple levels of P-type silicon floating charge compensation regions are arranged at intervals along the direction from the P-type base region to the Si / SiC heterointerface. The lateral dimension and effective compensation charge of each level of the P-type silicon floating charge compensation region decrease progressively along the direction from the P-type base region to the Si / SiC heterointerface.

[0006] Optionally, the longitudinal projection of the final-stage P-type silicon floating charge compensation region closest to the Si / SiC heterointerface at least partially overlaps with the buried dielectric field-tuning region. The Si / SiC direct contact conductive window is aligned with the central longitudinal conductive channel between the final-stage P-type silicon floating charge compensation regions located on opposite sides. Furthermore, the distance d0 from the final-stage P-type silicon floating charge compensation region to the Si / SiC heterointerface is less than the minimum longitudinal distance d1 between it and the adjacent previous-stage P-type silicon floating charge compensation region. The ratio of the distance d0 to the distance d1 is between 0.20 and 0.80.

[0007] Optionally, along the direction from the P-type base region to the Si / SiC heterostructure, in two adjacent P-type silicon floating charge compensation regions, the effective compensation charge of the latter stage is 0.55 to 0.90 times that of the former stage.

[0008] Optionally, the number of stages of the P-type silicon floating charge compensation region is 3 to 12, the lateral dimension of each stage of the P-type silicon floating charge compensation region is 0.4 μm to 8 μm, the longitudinal thickness is 0.1 μm to 1.5 μm, and the longitudinal interval between two adjacent stages is 0.2 μm to 4 μm.

[0009] Optionally, both the N+ type 4H-SiC substrate and the N-type 4H-SiC field extension layer are made of 4H-SiC material; the N-type silicon drift region, the P-type base region, and each level of the P-type silicon floating charge compensation region are made of single-crystal silicon material; the thickness of the N-type silicon drift region is 5 μm to 40 μm, and the average effective donor concentration is 1 × 10¹. 4 cm - ³~1×10¹ 6 cm - ³; The thickness of the N-type silicon carbide field extension layer is 1 μm to 30 μm, and the average effective donor concentration is 5 × 10¹. 4 cm - ³~5×10¹ 6 cm - ³; The doping concentration of the N+ type 4H-SiC substrate is higher than that of the N type silicon carbide field extension layer.

[0010] Optionally, the lateral width of the Si / SiC direct contact conductive window is 40% to 90% of the width of the central longitudinal conductive channel between the two opposite P-type silicon floating charge compensation regions. The overlap length between the final P-type silicon floating charge compensation region and the corresponding buried dielectric field adjustment region in the longitudinal projection is not less than 50% of the lateral dimension of the final P-type silicon floating charge compensation region. Furthermore, the edge of the Si / SiC direct contact conductive window is located between the inner edges of the two opposite P-type silicon floating charge compensation regions.

[0011] Optionally, the Si / SiC direct contact conductive window is a strip, a ring, multiple parallel strips, a circular array, or a grid-like Si / SiC direct contact conductive window; each Si / SiC direct contact conductive window is aligned with the corresponding central longitudinal conductive channel.

[0012] Optionally, the thickness of the embedded dielectric field-modulating region is 20 nm to 500 nm, and the material is silicon dioxide, silicon nitride, aluminum oxide, or a stack formed of at least two of these materials; the edge of the embedded dielectric field-modulating region facing the Si / SiC direct contact conductive window is a rounded corner, a bevel, or a multi-step surface.

[0013] Secondly, this application provides a method for fabricating a locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS as described in the first aspect, comprising: S1: Provide an N+ type 4H-SiC substrate, and form an N-type 4H-SiC field extension layer on the N+ type 4H-SiC substrate; S2: An N+ type silicon carbide interface transition region is formed in the window area on the surface of the N-type 4H-SiC field extension layer. An embedded dielectric field adjustment region is formed on both sides of the window area. The embedded dielectric field adjustment region is planarized so that the bonding surface of the embedded dielectric field adjustment region is coplanar with the surface of the N+ type silicon carbide interface transition region. S3: An N-type silicon drift structure is prefabricated on a silicon wafer with a carrier layer. During the prefabrication process, multiple levels of isolated P-type silicon floating charge compensation regions are formed. The lateral dimensions and effective compensation charge of each level of the P-type silicon floating charge compensation region are gradually reduced towards the bonding surface. An N-type silicon isolation layer is retained between each level of the P-type silicon floating charge compensation region and the bonding surface. The activation of each P-type silicon floating charge compensation region is completed before bonding. S4: Align and hybrid bond the bonding surface to the N-type 4H-SiC field extension layer, so that the central conductive region of the bonding surface directly contacts the N+ type silicon carbide interface transition region, thereby forming a Si / SiC heterojunction between the N-type silicon drift region and the N-type 4H-SiC field extension layer. A Si / SiC direct contact conductive window is formed at the center of the Si / SiC heterojunction by the direct contact between the central conductive region and the N+ type silicon carbide interface transition region. The buried dielectric field adjustment region is located on both lateral sides of the Si / SiC direct contact conductive window. Specifically, an N+ type silicon interface transition region is pre-formed in the central conductive region of the bonding surface, so that the N+ type silicon interface transition region directly contacts the N+ type silicon carbide interface transition region and together constitutes the Si / SiC direct contact conductive window. S5: Remove or thin the carrier layer to expose the device surface of the N-type silicon drift structure; S6: A P-type base region, an N+ type source region, a P+ type body contact region, a gate dielectric layer, a gate and a source are formed on the surface of the device, and a drain is formed on the back side of the N+ type 4H-SiC substrate, wherein the P-type base region is formed in the upper region of the N-type silicon drift region and is isolated from the uppermost P-type silicon floating charge compensation region.

[0014] Optionally, in S3, each level of P-type silicon floating charge compensation region is formed by boron ion implantation, selective P-type silicon epitaxy, or solid-state source diffusion. Activation annealing is performed before bonding to isolate each level of P-type silicon floating charge compensation region from each other, and an N-type silicon isolation layer is retained between the P-type silicon floating charge compensation region closest to the bonding surface and the bonding surface. By jointly setting the mask opening size, implantation dose, longitudinal thickness, and longitudinal spacing of each level of P-type silicon floating charge compensation region, the effective compensation charge of adjacent P-type silicon floating charge compensation regions is made such that the subsequent level is 0.55 to 0.90 times that of the previous level, and the ratio of the distance d0 from the P-type silicon floating charge compensation region closest to the bonding surface to the bonding surface to its minimum longitudinal distance d1 to the adjacent previous level P-type silicon floating charge compensation region is between 0.20 and 0.80. In step S4, alignment is performed using alignment marks formed on the silicon wafer and the N+ type 4H-SiC substrate, respectively, to align the N+ type silicon interface transition region with the N+ type silicon carbide interface transition region. The overlap length in the longitudinal projection between the P-type silicon floating charge compensation region closest to the bonding surface and the buried dielectric field-tuning region is not less than 50% of the lateral dimension of the P-type silicon floating charge compensation region. The edge of the Si / SiC direct contact conductive window is located between the inner edges of the P-type silicon floating charge compensation regions closest to the bonding surface on opposite sides. Before bonding, the surfaces of the bonding surface and the N-type 4H-SiC field extension layer are deoxidized, plasma activated, and cleaned, and pre-bonding and bonding enhancement annealing are completed at a temperature not exceeding 450°C.

[0015] Beneficial effects: (1) In this application, the P-type base region and the multi-level P-type silicon floating charge compensation region are both set in the N-type silicon drift region, so there is no need to form a P-type compensation region in the SiC material, thus avoiding the high-temperature activation process of P-type doping in SiC; at the same time, the lateral size and effective compensation charge of each level of P-type silicon floating charge compensation region decrease step by step along the direction pointing to the Si / SiC hetero interface, forming a double gradient distribution, which can form multiple electric field peaks in the drift region and make the electric field envelope change smoothly towards the hetero interface, which is beneficial to improve the breakdown voltage and reduce the specific on-resistance.

[0016] (2) The Si / SiC heterostructure is configured with a Si / SiC direct contact conductive window formed by the direct contact between the N+ type silicon interface transition region and the N+ type silicon carbide interface transition region. This conductive window forms a continuous semiconductor conductive path from the N-type silicon drift region to the N-type 4H-SiC field extension layer. The lateral boundaries of the two interface transition regions are located within the conductive window and are laterally spaced from the buried dielectric field tuning region, thereby ensuring low resistance conduction in the longitudinal direction while avoiding the formation of a high field low resistance channel along the dielectric edge. The buried dielectric field tuning region avoids the center. The main current path is used to modulate the interface electric field. The final-stage P-type silicon floating charge compensation region and the buried dielectric field modulation region at least partially overlap in the longitudinal projection, and the distance d0 from the final-stage P-type silicon floating charge compensation region to the Si / SiC heterostructure is less than the minimum longitudinal distance d1 between it and the adjacent previous stage. The ratio of d0 to d1 is between 0.20 and 0.80, so that the depletion region of the final-stage floating region is preferentially coupled with the depletion region near the heterostructure, and the multi-peak electric field envelope of the silicon drift region is smoothly connected to the SiC field extension layer, thus alleviating the concentration of the interface electric field.

[0017] (3) The effective compensation charge of the adjacent two-stage P-type silicon floating charge compensation regions meets the requirement that the latter stage is 0.55 to 0.90 times that of the former stage. With the range of 3 to 12 stages, the lateral dimension of 0.4 μm to 8 μm, the longitudinal thickness of 0.1 μm to 1.5 μm, and the longitudinal spacing of 0.2 μm to 4 μm, the electric field distribution of the drift region can be further optimized. The lateral width of the Si / SiC direct contact conductive window is 40% to 90% of the width of the central longitudinal conductive channel between the two end-stage P-type silicon floating charge compensation regions. The longitudinal projection overlap length between the end-stage P-type silicon floating charge compensation region and the buried dielectric field adjustment region is not less than 50% of its lateral dimension. The edge of the conductive window is located between the inner edges of the two end-stage P-type silicon floating charge compensation regions, thereby achieving effective decoupling between the main current path and the dielectric edge electric field, improving the device withstand voltage and reliability.

[0018] (4) The fabrication method involves first prefabricating and activating each level of P-type silicon floating charge compensation region on a silicon wafer with a carrier layer, and then aligning and mixing it with an N-type 4H-SiC field extension layer with a buried dielectric field-tuning region. The bonding temperature is no higher than 450℃, so that the high-temperature activation of the P-type silicon floating charge compensation region is completed before bonding, avoiding the heterogeneous interface from undergoing high-temperature processing, which helps to reduce interface defects and interface-added voltage drop. At the same time, by jointly setting the mask opening size, implantation dose, longitudinal thickness and longitudinal spacing, the effective compensation charge ratio and d0 / d1 relationship can be precisely controlled to ensure the consistency of device performance. The Si / SiC direct contact conductive window can adopt a strip, ring, multiple parallel strips, circular array or grid structure, which is convenient for flexible arrangement according to layout requirements. The following will describe this application in further detail with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 A schematic cross-sectional view of a partially insulated Si / SiC heterojunction coupled stepped floating island VDMOS provided in this application; Figure 2 for Figure 1 Enlarged schematic diagram of the bottom two P-type silicon floating charge compensation regions and the locally insulating Si / SiC heterostructure interface; Figure 3 This is a schematic diagram of the layout of the floating charge compensation region, the buried dielectric field modulation region, and the Si / SiC direct contact conductive window of each level of P-type silicon in this application. Figure 4 This is a qualitative schematic diagram of the effective compensation charge gradients at each level and the longitudinal electric field envelope under the blocking state in this application; Figure 5 This is a schematic flowchart illustrating a method for fabricating a partially insulated Si / SiC heterojunction coupled stepped floating island VDMOS provided in this application. Detailed Implementation

[0020] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0021] In this application, "vertical" refers to the direction from the source to the drain, and "lateral" refers to the direction perpendicular to the vertical. "Floating" means that the corresponding P-type region is not directly connected to the source or drain through a low-resistance path. "Projection overlap" means that when projected along the vertical direction onto the Si / SiC heterojunction, there is a common coverage area.

[0022] like Figure 1 As shown, this embodiment is an N-channel planar gate VDMOS. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS includes an N+ type 4H-SiC substrate 9, an N-type 4H-SiC field extension layer 8 on the N+ type 4H-SiC substrate 9, an N-type silicon drift region 7 on the N-type 4H-SiC field extension layer 8, a P-type base region 6 formed in the upper region of the N-type silicon drift region 7, an N+ type source region 5 and a P+ type body contact region 4 formed in the P-type base region 6, a source 1 formed on the upper part of the P-type base region 6, a gate dielectric layer 3 formed on the N-type silicon drift region 7, a gate 2 formed on the gate dielectric layer 3, and a drain 14 formed on the back side of the N+ type 4H-SiC substrate 9.

[0023] The back side of the N+ type 4H-SiC substrate 9 has a drain 14, and the front side is epitaxially formed with an N-type 4H-SiC field extension layer 8. The N-type silicon drift region 7 is formed on top of the N-type 4H-SiC field extension layer 8 through hybrid bonding, and the area where the two are in direct contact constitutes an N-type Si / SiC heterojunction. The P-type base region 6 is entirely located on top of the N-type silicon drift region 7, and the P-type base region 6 has an N+ type source region 5 and a P+ type body contact region 4. The source 1 is in contact with both the N+ type source region 5 and the P+ type body contact region 4, and the gate 2 controls the channel through the gate dielectric layer 3.

[0024] A Si / SiC heterojunction 13 is formed between the N-type silicon drift region 7 and the N-type 4H-SiC field extension layer 8. An N+ type silicon interface transition region extending upwards from the Si / SiC heterojunction 13 to the N-type silicon drift region 7 is formed, and an N+ type silicon carbide interface transition region extending downwards from the Si / SiC heterojunction 13 to the N-type 4H-SiC field extension layer 8 is formed. The N+ type silicon interface transition region and the N+ type silicon carbide interface transition region constitute a Si / SiC direct contact conductive window 11. Buried dielectric field adjustment regions 12 are formed on both lateral sides of the Si / SiC direct contact conductive window 11. The lateral boundaries of both interface transition regions are located within the lateral boundaries of the Si / SiC direct contact conductive window 11, and both interface transition regions are laterally spaced from the buried dielectric field adjustment regions 12. The average effective donor concentration of the two interface transition regions is no less than five times the average effective donor concentration of their adjacent N-type silicon drift region 7 or N-type 4H-SiC field extension layer 8, and their longitudinal thicknesses are 0.02 μm to 1 μm, respectively. The thickness and doping concentration of the two N+ type interface transition regions can be different, but their lateral boundaries must not extend below the dielectric region to avoid forming a high-field, low-resistance channel along the dielectric edge. The bonding surface of the buried dielectric field-tuning region 12 is coplanar with the silicon carbide material surface at the Si / SiC direct contact conductive window 11. The buried dielectric field-tuning regions 12 are separated from each other, and the Si / SiC direct contact conductive window 11 constitutes a continuous semiconductor conductive path from the N-type silicon drift region 7 to the N-type 4H-SiC field extension layer 8.

[0025] Within the N-type silicon drift region 7, multiple levels of P-type silicon floating charge compensation regions 10a to 10g are spaced apart along the direction from the P-type base region 6 to the Si / SiC heterointerface 13. In this embodiment, seven levels of P-type silicon floating charge compensation regions 10a to 10g are provided. N-type silicon isolation regions are retained between each level of floating island and between the uppermost floating island 10a and the P-type base region 6. An N-type silicon isolation region is also retained between the lowermost floating island 10g and the Si / SiC heterointerface 13; therefore, all floating islands are located within the silicon material and maintain electrical levitation. No P-type silicon floating charge compensation region extends into the N-type 4H-SiC field extension layer 8. The lateral dimensions and effective compensation charge of each level of P-type silicon floating charge compensation region 10a to 10g decrease progressively along the direction from the P-type base region 6 to the Si / SiC heterointerface 13. In this embodiment, the lateral dimensions of each level of the floating island, from top to bottom, are 4μm, 3.4μm, 2.9μm, 2.4μm, 2.0μm, 1.6μm, and 1.2μm; the thickness is 0.6μm for all levels, and the average effective acceptor concentration can be set to be the same, thus the effective compensation charge decreases progressively with the lateral dimension. The same decreasing relationship of effective compensation charge can also be obtained by simultaneously changing the thickness and the injection dose.

[0026] The effective compensation charge is the integral value of the net acceptor charge in the i-th level P-type silicon floating charge compensation region. For a strip-shaped compensation region extending uniformly along a direction perpendicular to the device profile, the effective compensation charge per unit depth Qi = q·NA,i·ti·Li, where q is the elementary charge, NA,i is the average effective acceptor concentration, ti is the longitudinal thickness, and Li is the lateral extension dimension measured from the boundary of the central longitudinal conductive channel. Along the direction from the P-type base region 6 to the Si / SiC heterointerface 13, in adjacent P-type silicon floating charge compensation regions, the effective compensation charge of the latter level is 0.55 to 0.90 times that of the former level. This gradient relationship allows the upper floating island to bear a stronger main junction electric field expansion effect, while the lower floating island gradually reduces the crowding of the central conductive channel and suppresses the superposition of the lowest-level floating island with the dielectric edge to form excessively high local peaks.

[0027] In this embodiment, the lateral width of the Si / SiC direct contact conductive window 11 is 40% to 90% of the width of the central longitudinal conductive channel between the two opposite final-stage P-type silicon floating charge compensation regions 10g. The overlap length of the final-stage P-type silicon floating charge compensation region 10g and the corresponding buried dielectric field-tuning region 12 in the longitudinal projection is not less than 50% of the lateral dimension of the final-stage P-type silicon floating charge compensation region 10g, and the edge of the Si / SiC direct contact conductive window 11 is located between the inner edges of the two opposite final-stage P-type silicon floating charge compensation regions 10g, to avoid the dielectric layer crossing the longitudinal main current channel.

[0028] In this embodiment, the thickness of the buried dielectric field-modulating region 12 is 20nm to 500nm, and the material is silicon dioxide, silicon nitride, aluminum oxide, or a stack formed of at least two of these materials. The edge of the buried dielectric field-modulating region 12 facing the Si / SiC direct contact conductive window 11 is rounded, beveled, or has a multi-step surface to reduce the local electric field concentration caused by the edge curvature.

[0029] In this embodiment, the thickness of the N-type silicon drift region 7 is 5 μm to 40 μm, and the average effective donor concentration is 1 × 10¹. 4 cm - ³~1×10¹ 6 cm - ³; The thickness of the N-type 4H-SiC field extension layer 8 is 1 μm to 30 μm, and the average effective donor concentration is 5 × 10¹ 4 cm - ³~5×10¹ 6 cm - ³; The doping concentration of the N+ type 4H-SiC substrate 9 is higher than that of the N type 4H-SiC field extension layer 8.

[0030] In this embodiment, the gate 2 is a planar gate or a trench gate, and the gate dielectric layer 3 is silicon dioxide, a high dielectric constant dielectric material, or a stack thereof. When a trench gate is used, the bottom of the trench preferably maintains a sufficient longitudinal distance from the topmost floating island, and the trench does not penetrate the Si / SiC heterostructure interface.

[0031] like Figure 2 The diagram shows an enlarged view of the bottom two floating islands and the locally insulating Si / SiC heterostructure interface. The longitudinal projection of the final-stage P-type silicon floating charge compensation region 10g, closest to the Si / SiC heterostructure interface 13, at least partially overlaps with the buried dielectric field-tuning region 12. The central longitudinal conductive channel between the Si / SiC direct contact conductive window 11 and the final-stage P-type silicon floating charge compensation regions 10g located on opposite sides is aligned. The distance d0 from the final-stage P-type silicon floating charge compensation region 10g to the Si / SiC heterostructure interface 13 is less than the minimum longitudinal distance d1 between it and the adjacent previous-stage P-type silicon floating charge compensation region 10f. In this embodiment, the ratio of distance d0 to distance d1 is between 0.20 and 0.80. This distance relationship allows the depletion region of the final-stage floating island to preferentially couple with the depletion region near the heterostructure interface during the blocking process, thereby smoothly continuing the multi-peak electric field envelope of the silicon drift region to the N-type 4H-SiC field extension layer 8.

[0032] In this embodiment, the number of stages of the P-type silicon floating charge compensation region is 3 to 12. The lateral dimension of each stage of the P-type silicon floating charge compensation region is 0.4μm to 8μm, the longitudinal thickness is 0.1μm to 1.5μm, and the longitudinal interval between adjacent stages is 0.2μm to 4μm.

[0033] like Figure 3 As shown, in the three-dimensional unit, each level of P-type silicon floating charge compensation region can form a closed ring, or it can be set as a segmented ring with an opening, or it can form a polygonal ring structure around the central longitudinal conductive channel. The Si / SiC direct contact conductive window 11 is located in the center, and the buried dielectric field adjustment region 12 is arranged around the conductive window. The segmented ring can be used to reduce hole accumulation or to leave channels for layout alignment marks, gate leads and terminal structures. The Si / SiC direct contact conductive window 11 can be a strip, a ring, multiple parallel strips, a circular array or a grid-like Si / SiC direct contact conductive window; each Si / SiC direct contact conductive window 11 is aligned with the corresponding central longitudinal conductive channel.

[0034] Field limiting rings, junction termination extension regions, field plates, or trench terminations can also be set around the device. These termination structures do not change the coupling relationship between the conductive window, buried medium, and final floating island within the device unit.

[0035] In the forward conduction state, gate 2 opens the silicon surface channel, and electrons enter the N-type silicon drift region 7 from the N+ source region 5. As the lateral dimensions of the P-type silicon floating charge compensation regions 10a to 10g gradually shorten towards the drain, the central conductive channel gradually widens. Electrons then sequentially pass through the N+ silicon interface transition region, the Si / SiC direct contact conductive window 11, and the N+ silicon carbide interface transition region into the N-type 4H-SiC field extension layer 8 and the N+ 4H-SiC substrate 9. The buried dielectric field modulation region 12 is located on both sides of the window and is not connected in series with the central main current path.

[0036] In the reverse blocking state, multiple electric field peaks are formed at the main junction of the P-type base region 6 and the N-type silicon drift region 7, as well as at the edges of each level of floating islands. The effective compensation charge decreases step by step, causing the peak envelope to smoothly decrease towards the heterojunction; the smaller d0 connects the final depletion region with the depletion region near the heterojunction. The buried dielectric field-tuning region 12 changes the normal displacement current and the bending position of the equipotential lines at the interface, while the Si / SiC direct contact conductive window 11 electrically couples the central region, which is not isolated by the dielectric, with the N-type 4H-SiC field extension layer 8, so that a portion of the voltage is borne within the N-type 4H-SiC field extension layer 8. Figure 4 This indicates the qualitative relationship between the peak value and the envelope of the electric field. The specific peak value is determined by the doping concentration, geometric dimensions, and interface parameters.

[0037] Four sets of control devices can be fabricated for verification: the first set uses a continuous Si / SiC direct interface without an interface transition region; the second set only has an N+ type interface transition region at the direct interface; the third set adds a locally buried dielectric but makes d0 equal to or greater than d1; the fourth set uses the interface transition region, locally buried dielectric, projection overlap, and d0 / d1 relationship of this invention. Each set maintains the same total compensation charge for the silicon drift region, SiC field extension layer, and floating island. Interface leakage current, specific on-resistance, and electric field transfer are evaluated by blocking IV, conducting IV, interface contact resistance, temperature characteristics, and cross-sectional scanning capacitance or electron beam induced current tests.

[0038] like Figure 5 As shown, this application provides a method for fabricating a locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS, including: S1: Provide an N+ type 4H-SiC substrate 9, and form an N-type 4H-SiC field extension layer 8 on the N+ type 4H-SiC substrate 9.

[0039] Specifically, an N-type 4H-SiC field extension layer 8 is epitaxially grown on the front side of an N+ type 4H-SiC substrate 9.

[0040] S2: An N+ type silicon carbide interface transition region is formed in the window region on the surface of the N-type 4H-SiC field extension layer 8. An embedded dielectric field adjustment region 12 is formed on both sides of the window region. The embedded dielectric field adjustment region 12 is planarized so that the bonding surface of the embedded dielectric field adjustment region 12 is coplanar with the surface of the N+ type silicon carbide interface transition region.

[0041] Specifically, an N+ type silicon carbide interface transition region is formed in the predetermined window area by ion implantation or selective epitaxy. Then, a dielectric layer is deposited or grown and patterned to form mutually separated buried dielectric field-tuning regions 12. The dielectric region and the predetermined window area are planarized so that they constitute a continuous coplanar surface to be bonded. The formation of the buried dielectric field-tuning region 12 includes the growth or deposition of the dielectric layer, photolithography, and etching to form a silicon dioxide region, silicon nitride region, alumina region, or multilayer dielectric region with a thickness of 20 nm to 500 nm. At least one of etching back, chemical mechanical polishing, and thermal treatment is used to ensure that the buried dielectric field-tuning region 12 and the predetermined window area meet the coplanar requirements for mixed bonding.

[0042] S3: An N-type silicon drift structure is prefabricated on a silicon wafer with a carrier layer. During the prefabrication process, multiple levels of isolated P-type silicon floating charge compensation regions 10a to 10g are formed. The lateral dimensions and effective compensation charge of each level of the P-type silicon floating charge compensation region 10a to 10g are gradually reduced towards the bonding surface. An N-type silicon isolation layer is retained between each level of the P-type silicon floating charge compensation region 10a to 10g and the bonding surface. The activation of each P-type silicon floating charge compensation region 10a to 10g is completed before bonding.

[0043] Specifically, on a silicon wafer with a sacrificial layer or a removable carrier layer, multiple N-type silicon epitaxial sublayers are sequentially formed from the future device surface toward the future bonding surface. After forming the corresponding epitaxial sublayers, P-type doped regions are formed by boron ion implantation or selective P-type epitaxy, such that at least one of the mask aperture size and implantation dose decreases toward the future bonding surface. After completing all P-type doped regions, activation annealing is performed to form P-type silicon floating charge compensation regions 10a to 10g that are separated from each other in each P-type region. An N-type silicon isolation layer is then formed on one side of the future bonding surface, and an N+ type silicon interface transition region is formed in the central conductive region corresponding to the predetermined region of the SiC side window.

[0044] Each level of P-type silicon floating charge compensation region 10a to 10g is formed by boron ion implantation, selective P-type silicon epitaxy, or solid-state source diffusion. After activation, adjacent P-type silicon floating charge compensation regions are separated from each other, and an N-type silicon isolation layer is retained between the P-type silicon floating charge compensation region 10g closest to the bonding surface and the bonding surface.

[0045] By jointly setting the mask opening size, implantation dose, longitudinal thickness, and longitudinal spacing of each level of P-type silicon floating charge compensation region 10a to 10g, the effective compensation charge of adjacent P-type silicon floating charge compensation regions is made to satisfy that the subsequent level is 0.55 to 0.90 times that of the previous level, and the ratio of the distance d0 from the P-type silicon floating charge compensation region 10g closest to the bonding surface to the bonding surface to the minimum longitudinal distance d1 from it to the adjacent upper-level P-type silicon floating charge compensation region 10f is between 0.20 and 0.80.

[0046] S4: Align and mix the bonding surface to be bonded with the N-type 4H-SiC field extension layer 8, so that the central conductive region of the bonding surface directly contacts the N+ type silicon carbide interface transition region at the window region, thereby forming a Si / SiC heterostructure 13 between the N-type silicon drift region 7 and the N-type 4H-SiC field extension layer 8. At the center of the Si / SiC heterostructure 13, the central conductive region directly contacts the N+ type silicon carbide interface transition region at the window region to form a Si / SiC direct contact conductive window 11. The buried dielectric field adjustment region 12 is located on both sides of the Si / SiC direct contact conductive window 11. In this case, an N+ type silicon interface transition region is pre-formed in the central conductive region of the bonding surface, so that the N+ type silicon interface transition region directly contacts the N+ type silicon carbide interface transition region and together constitutes the Si / SiC direct contact conductive window 11.

[0047] Specifically, the bonding surfaces of the silicon wafer and the SiC wafer are subjected to chemical mechanical polishing, deoxidation, plasma activation, and cleaning. Alignment marks on the two wafers are used to ensure direct contact between the central conductive region of the bonding surface and the N+ type silicon carbide interface transition region at the window area within the Si / SiC direct contact conductive window 11. Simultaneously, the N+ type silicon interface transition region is made to directly contact the N+ type silicon carbide interface transition region, and the buried dielectric field-tuning region 12 overlaps with the projection of the lowest-level floating island, satisfying the d0 / d1 relationship. Pre-bonding and bonding enhancement annealing are completed at a temperature not exceeding 450°C.

[0048] Alignment is achieved using alignment marks formed on the silicon wafer and the N+ type 4H-SiC substrate 9, respectively, to align the N+ type silicon interface transition region with the N+ type silicon carbide interface transition region. The overlap length in the longitudinal projection between the P-type silicon floating charge compensation region 10g closest to the bonding surface and the buried dielectric field-tuning region 12 is not less than 50% of the lateral dimension of the P-type silicon floating charge compensation region 10g. The edge of the Si / SiC direct contact conductive window 11 is located between the inner edges of the P-type silicon floating charge compensation regions 10g closest to the bonding surface on opposite sides. Before bonding, the surfaces of the bonding surface and the N-type 4H-SiC field extension layer 8 are subjected to deoxidation, plasma activation, and cleaning, and pre-bonding and bonding enhancement annealing are performed at a temperature not exceeding 450°C.

[0049] S5: Remove or thin the carrier layer to expose the device surface of the N-type silicon drift structure.

[0050] Specifically, the future device surface of the N-type silicon drift region 7 is exposed by selectively etching, grinding, and chemical mechanical polishing to remove or thin the silicon wafer carrier layer.

[0051] S6: A P-type base region 6, an N+ type source region 5, a P+ type body contact region 4, a gate dielectric layer 3, a gate 2, and a source 1 are formed on the surface of the device, and a drain 14 is formed on the back side of the N+ type 4H-SiC substrate 9, wherein the P-type base region 6 is formed in the upper region of the N-type silicon drift region 7 and is isolated from the uppermost P-type silicon floating charge compensation region 10a.

[0052] Specifically, a P-type base region 6, an N+ type source region 5, and a P+ type body contact region 4 are formed on the exposed device surface; a gate dielectric layer 3 and a gate electrode 2 are formed to complete the interlayer dielectric, contact hole, and source electrode 1; the back side of the N+ type 4H-SiC substrate 9 is thinned and metallized to form a drain electrode 14, and passivation and segmentation are completed.

[0053] The above sequence ensures that the high-temperature activation of the P-type silicon floating charge compensation region 10a–10g and the N+ type silicon interface transition region is completed before Si / SiC hybrid bonding. The N+ type silicon carbide interface transition region can be implanted and activated before dielectric patterning to avoid high-temperature SiC activation after bonding. After bonding, the window boundaries, interface transition region doping, projection overlap relationship, and doping profile are confirmed by cross-sectional transmission electron microscopy, secondary ion mass spectrometry, or scanning extended resistance testing. The central conductive window can be a single strip window, multiple parallel strip windows, a circular array window, or a grid window; the buried dielectric field-tuning region 12 correspondingly adopts a strip, ring, segmented ring, or grid pattern.

[0054] In the three-dimensional unit cell, each level of P-type silicon floating charge compensation region can form a closed ring, or it can be configured as a segmented ring with openings, or it can form a polygonal ring structure. The Si / SiC direct contact conductive window 11 is located in the center, and the buried dielectric field-modulating region 12 is arranged around the conductive window. The segmented ring can be used to reduce hole accumulation or to leave channels for layout alignment marks, gate leads, and termination structures.

[0055] Gate 2 can be a planar gate or a trench gate. When using a trench gate, the bottom of the trench should preferably maintain a sufficient longitudinal distance from the top-level floating island, and the trench should not penetrate the Si / SiC heterostructure interface. Field limiting rings, junction termination extension regions, field plates, or trench terminations can also be set around the device periphery. These termination structures do not change the coupling relationship between the conductive window, buried dielectric, and the final-level floating island within the device unit.

[0056] The embedded dielectric field-tuning region 12 can be a single layer of silicon dioxide, or it can be a silicon dioxide / silicon nitride, silicon dioxide / alumina, or a stack containing a high dielectric constant material. The inner edge of the dielectric can be rounded, beveled, or have multiple steps to reduce local electric field concentration caused by edge curvature. The thickness and doping concentration of the two N+ type interface transition regions can be different, but their lateral boundaries must not extend below the dielectric region to avoid forming a high-field, low-resistivity channel along the dielectric edge.

[0057] The above embodiments are for illustrative purposes only and do not limit the scope of protection. The specific number, size, doping dose, interface window shape, dielectric material, and bonding method of the floating islands can be adjusted within the coupling relationship defined in the claims.

[0058] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS, characterized in that, include: An N+ type 4H-SiC substrate, an N-type 4H-SiC field extension layer on the N+ type 4H-SiC substrate, an N-type silicon drift region on the N-type 4H-SiC field extension layer, a P-type base region formed in the upper region of the N-type silicon drift region, an N+ type source region and a P+ type body contact region formed in the P-type base region, a source electrode formed in the upper part of the P-type base region, a gate dielectric layer formed on the N-type silicon drift region, a gate electrode formed on the gate dielectric layer, and a drain electrode formed on the back side of the N+ type 4H-SiC substrate. The N-type silicon drift region and the N-type 4H-SiC field extension layer are separated by a Si / SiC heterojunction. An N+ type silicon interface transition region extending upwards to the N-type silicon drift region is provided along the Si / SiC heterojunction, and an N+ type silicon carbide interface transition region extending downwards into the N-type 4H-SiC field extension layer is provided along the Si / SiC heterojunction. The N+ type silicon interface transition region and the N+ type silicon carbide interface transition region constitute a Si / SiC direct contact conductive window. Buried dielectric field adjustment regions are provided on both sides of the Si / SiC direct contact conductive window. Within the N-type silicon drift region, multiple levels of P-type silicon floating charge compensation regions are arranged at intervals along the direction from the P-type base region to the Si / SiC heterointerface. The lateral dimension and effective compensation charge of each level of the P-type silicon floating charge compensation region decrease progressively along the direction from the P-type base region to the Si / SiC heterointerface.

2. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, The projection of the final-stage P-type silicon floating charge compensation region closest to the Si / SiC heterointerface in the longitudinal direction at least partially overlaps with the buried dielectric field adjustment region. The Si / SiC direct contact conductive window is aligned with the central longitudinal conductive channel between the final-stage P-type silicon floating charge compensation regions located on opposite sides. Furthermore, the distance d0 from the final-stage P-type silicon floating charge compensation region to the Si / SiC heterointerface is less than the minimum longitudinal distance d1 between it and the adjacent previous-stage P-type silicon floating charge compensation region. The ratio of the distance d0 to the distance d1 is between 0.20 and 0.

80.

3. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, Along the direction from the P-type base region to the Si / SiC heterostructure, in two adjacent P-type silicon floating charge compensation regions, the effective compensation charge of the latter stage is 0.55 to 0.90 times that of the former stage.

4. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, The number of stages of the P-type silicon floating charge compensation region is 3 to 12. The lateral dimension of each stage of the P-type silicon floating charge compensation region is 0.4 μm to 8 μm, the longitudinal thickness is 0.1 μm to 1.5 μm, and the longitudinal interval between adjacent stages is 0.2 μm to 4 μm.

5. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, Both the N+ type 4H-SiC substrate and the N-type 4H-SiC field extension layer are made of 4H-SiC material; the N-type silicon drift region, the P-type base region, and each level of the P-type silicon floating charge compensation region are made of single-crystal silicon material; the thickness of the N-type silicon drift region is 5 μm to 40 μm, and the average effective donor concentration is 1 × 10¹. 4 cm - ³~1×10¹ 6 cm - ³; The thickness of the N-type silicon carbide field extension layer is 1 μm to 30 μm, and the average effective donor concentration is 5 × 10¹. 4 cm - ³~5×10¹ 6 cm - ³; The doping concentration of the N+ type 4H-SiC substrate is higher than that of the N type silicon carbide field extension layer.

6. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, The lateral width of the Si / SiC direct contact conductive window is 40% to 90% of the width of the central longitudinal conductive channel between the two opposite P-type silicon floating charge compensation regions. The overlap length between the final P-type silicon floating charge compensation region and the corresponding buried dielectric field adjustment region in the longitudinal projection is not less than 50% of the lateral dimension of the final P-type silicon floating charge compensation region. Furthermore, the edge of the Si / SiC direct contact conductive window is located between the inner edges of the two opposite P-type silicon floating charge compensation regions.

7. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, The Si / SiC direct contact conductive window is a strip, a ring, multiple parallel strips, a circular array, or a grid-like Si / SiC direct contact conductive window; each Si / SiC direct contact conductive window is aligned with the corresponding central longitudinal conductive channel.

8. The locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 1, characterized in that, The thickness of the embedded dielectric field-modulating region is 20 nm to 500 nm, and the material is silicon dioxide, silicon nitride, aluminum oxide, or a stack of at least two of these materials; the edge of the embedded dielectric field-modulating region facing the Si / SiC direct contact conductive window is a rounded corner, a bevel, or a multi-step surface.

9. A method for fabricating a locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS as described in any one of claims 1 to 8, characterized in that, include: S1: Provide an N+ type 4H-SiC substrate, and form an N-type 4H-SiC field extension layer on the N+ type 4H-SiC substrate; S2: An N+ type silicon carbide interface transition region is formed in the window area on the surface of the N-type 4H-SiC field extension layer. An embedded dielectric field adjustment region is formed on both sides of the window area. The embedded dielectric field adjustment region is planarized so that the bonding surface of the embedded dielectric field adjustment region is coplanar with the surface of the N+ type silicon carbide interface transition region. S3: An N-type silicon drift structure is prefabricated on a silicon wafer with a carrier layer. During the prefabrication process, multiple levels of isolated P-type silicon floating charge compensation regions are formed. The lateral dimensions and effective compensation charge of each level of the P-type silicon floating charge compensation region are gradually reduced towards the bonding surface. An N-type silicon isolation layer is retained between each level of the P-type silicon floating charge compensation region and the bonding surface. The activation of each P-type silicon floating charge compensation region is completed before bonding. S4: Align and hybrid bond the bonding surface to the N-type 4H-SiC field extension layer, so that the central conductive region of the bonding surface directly contacts the N+ type silicon carbide interface transition region, thereby forming a Si / SiC heterojunction between the N-type silicon drift region and the N-type 4H-SiC field extension layer. A Si / SiC direct contact conductive window is formed at the center of the Si / SiC heterojunction by the direct contact between the central conductive region and the N+ type silicon carbide interface transition region. The buried dielectric field adjustment region is located on both lateral sides of the Si / SiC direct contact conductive window. Specifically, an N+ type silicon interface transition region is pre-formed in the central conductive region of the bonding surface, so that the N+ type silicon interface transition region directly contacts the N+ type silicon carbide interface transition region and together constitutes the Si / SiC direct contact conductive window. S5: Remove or thin the carrier layer to expose the device surface of the N-type silicon drift structure; S6: A P-type base region, an N+ type source region, a P+ type body contact region, a gate dielectric layer, a gate and a source are formed on the surface of the device, and a drain is formed on the back side of the N+ type 4H-SiC substrate, wherein the P-type base region is formed in the upper region of the N-type silicon drift region and is isolated from the uppermost P-type silicon floating charge compensation region.

10. The method for fabricating a locally insulated Si / SiC heterojunction coupled stepped floating island VDMOS according to claim 9, characterized in that, In S3, each level of P-type silicon floating charge compensation region is formed by boron ion implantation, selective P-type silicon epitaxy, or solid source diffusion. Activation annealing is performed before bonding to isolate each level of P-type silicon floating charge compensation region from each other, and to retain an N-type silicon isolation layer between the P-type silicon floating charge compensation region closest to the bonding surface and the bonding surface. By jointly setting the mask opening size, injection dose, longitudinal thickness, and longitudinal spacing of each level of P-type silicon floating charge compensation region, the effective compensation charge of adjacent P-type silicon floating charge compensation regions is made to satisfy that the subsequent level is 0.55 to 0.90 times that of the previous level, and the ratio of the distance d0 from the P-type silicon floating charge compensation region closest to the bonding surface to the bonding surface to its minimum longitudinal distance d1 to the adjacent upper-level P-type silicon floating charge compensation region is between 0.20 and 0.

80. In step S4, alignment is performed using alignment marks formed on the silicon wafer and the N+ type 4H-SiC substrate, respectively, to align the N+ type silicon interface transition region with the N+ type silicon carbide interface transition region. The overlap length in the longitudinal projection between the P-type silicon floating charge compensation region closest to the bonding surface and the buried dielectric field-tuning region is not less than 50% of the lateral dimension of the P-type silicon floating charge compensation region. The edge of the Si / SiC direct contact conductive window is located between the inner edges of the P-type silicon floating charge compensation regions closest to the bonding surface on opposite sides. Before bonding, the surfaces of the bonding surface and the N-type 4H-SiC field extension layer are deoxidized, plasma activated, and cleaned, and pre-bonding and bonding enhancement annealing are completed at a temperature not exceeding 450°C.

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