Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The structure comprises: a group of well regions extending inwardly through a first surface of a substrate, comprising first well regions arranged at intervals along a first direction and extending along a second direction, and second well regions arranged at intervals along the second direction and connecting adjacent first well regions; wherein the first well regions and the second well regions comprise base regions and source regions with top surfaces in the base regions; a doped region located in the second well regions, penetrating the source regions through the first surface and extending into the substrate, and used for forming an ohmic contact; a composite gate penetrating the first well regions in a direction towards the substrate, comprising first gates located between adjacent doped regions and second gates connected with the adjacent first gates; the second gates comprise extensions covering the top surfaces of the first well regions; the extensions comprise conductive materials; and at least the channel can be significantly encrypted to obtain a lower on-resistance.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of modern electronic technology, higher requirements are being placed on semiconductor materials, especially in fields such as high voltage, high frequency, high power, high temperature, and radiation resistance. Silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] With the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of the physical size of devices has driven the continuous reduction of the design pitch of their cells. The size of planar cells has approached the process limit, while trench cell designs have problems such as reliability and high on-resistance at high temperatures. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the technical problems in the existing technology, which can at least significantly increase the density of the channel while minimizing the cell pitch.

[0005] In a first aspect, this application provides a semiconductor structure, comprising:

[0006] A well region group extends inwardly through a first surface of a substrate, including a first well region spaced apart along a first direction and extending along a second direction, and a second well region spaced apart along the second direction and connecting adjacent first well regions; wherein the first well region and the second well region include a base region and a source region whose top surface is within the top surface of the base region;

[0007] The doped region, located within the second well region, extends through the source region via the first surface and into the substrate to form an ohmic contact.

[0008] A composite gate extending through a first well region in a direction toward the substrate includes: a first gate located between adjacent doped regions, and a second gate connected to an adjacent first gate; the second gate includes an extension covering the top surface of the first well region; the extension includes a conductive material.

[0009] The first direction and the second direction are parallel to the first surface and perpendicular to each other.

[0010] In some embodiments, the semiconductor structure further includes:

[0011] The first dielectric layer is located inside the composite gate, on the side closer to the source region;

[0012] The second dielectric layer is located on the first surface between adjacent base regions and is in contact with the extension.

[0013] The top surface of the first dielectric layer is located between the top surface of the composite gate and the first surface, and the bottom surface is flush with the bottom surface of the source region; the first dielectric layer located inside the second gate covers the top surface of the source region.

[0014] In some embodiments, the semiconductor structure further includes:

[0015] The JFET region extends into the substrate via the first surface, and its bottom surface is flush with the base region.

[0016] The third dielectric layer covers the outer surface of the composite gate;

[0017] The shielding area is located on the bottom surface of the composite grid, and the top surface is located inside the bottom surface of the composite grid.

[0018] The front metal layer, located on the third dielectric layer, includes a first plug extending toward the substrate to contact the doped region; the first plug, the doped region, and the substrate form a PiN structure.

[0019] In some embodiments, the extension is located on the outer surface of the first dielectric layer and extends along a first direction to contact an adjacent extension.

[0020] In some embodiments, the front metal layer further includes:

[0021] The second plug is arranged alternately with the first plug along the second direction and penetrates the second dielectric layer along the direction toward the substrate, so that the bottom surface forms a Schottky contact with the first surface.

[0022] In some embodiments, the composite gate includes:

[0023] A gate oxide layer is located on the inner surface of the gate trench and extends along a first direction to contact the bottom surface of the first dielectric layer, the extension, and the second dielectric layer.

[0024] The gate conductive layer includes an embedded portion and an extension portion filled in the gate trench, with the top surface higher than the first surface;

[0025] The first dielectric layer is located within the gate conductive layer.

[0026] In a second aspect, this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate;

[0027] A group of well regions extending inwardly through a first surface of a substrate is formed; the group of well regions includes first well regions spaced apart along a first direction and extending along a second direction, and second well regions spaced apart along the second direction and connecting adjacent first well regions; wherein the first well region and the second well region include a base region and a source region whose top surface is within the top surface of the base region.

[0028] A doped region is formed within the second well region, such that the doped region penetrates the source region through the first surface and extends into the substrate to form an ohmic contact.

[0029] A composite gate is formed that extends through the first well region in a direction toward the substrate; the composite gate includes: a first gate located between adjacent doped regions, and a second gate connected to an adjacent first gate; the second gate includes an extension covering the top surface of the first well region; the extension includes a conductive material;

[0030] The first direction and the second direction are parallel to the first surface and perpendicular to each other.

[0031] In some embodiments, the preparation method further includes:

[0032] In the same process steps, a first dielectric layer located inside the composite gate and close to the source region is formed simultaneously, and a second dielectric layer located on the first surface between adjacent base regions and in contact with the extension is formed.

[0033] The top surface of the first dielectric layer is located between the top surface of the composite gate and the first surface, and the bottom surface is flush with the bottom surface of the source region; the first dielectric layer located inside the second gate covers the top surface of the source region.

[0034] In some embodiments, forming the first dielectric layer and the second dielectric layer includes:

[0035] The substrate is etched to form gate trenches that are spaced apart along a first direction and extend along a second direction;

[0036] After forming a gate oxide layer covering the inner surface of the gate trench and the first surface, a first conductive layer is formed that fills the gate trench.

[0037] The first conductive layer is etched back so that its top surface is flush with the bottom surface of the source region;

[0038] A first dielectric layer is formed on the top surface of the first conductive layer near the source region, and a second dielectric layer is formed on the first surface between adjacent base regions.

[0039] In some embodiments, the preparation method further includes:

[0040] A second conductive layer is formed covering the first dielectric layer and the second dielectric layer, and a third dielectric layer is formed covering the second conductive layer;

[0041] Above the doped region, a via is formed extending in the direction toward the substrate to the substrate phase contact;

[0042] This forms a metal layer that fills the vias and covers the top surface of the third dielectric layer.

[0043] In some embodiments, the through holes are spaced apart along a first direction and extend along a second direction.

[0044] In some embodiments, through holes are spaced apart along a first direction.

[0045] The embodiments of this application may / at least have the following unexpected technical effects:

[0046] In the semiconductor structure provided in this application, first well regions are spaced apart along a first direction and extend along a second direction, and second well regions are located between adjacent first well regions, so that the well region group forms a "well" shaped arrangement. A first gate is embedded in the substrate to form a gate trench, and a second gate includes an extension located on the first surface to form a planar gate. Based on the above structure, when the semiconductor structure is in operation, electrons can flow along the well region group on both sides of the first gate and the substrate, flow laterally along the well region group in the "well" shaped grid below the extension of the second gate, and pass downwards through the substrate to complete the current path, achieving parallel conduction of three paths.

[0047] In addition, the doped regions can form good ohmic contacts, which can effectively increase the channel density without increasing the cell pitch, while improving the ultimate performance of the semiconductor structure. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic diagram of the structure of a pair of transistors provided in the example;

[0050] Figure 2 This is a schematic diagram of the semiconductor structure provided in Embodiment 1 of this application;

[0051] Figure 3 This is a schematic diagram of the electron flow direction of the semiconductor structure provided in Embodiment 1 of this application;

[0052] Figure 4 This is a schematic diagram of the semiconductor structure provided in Embodiment 2 of this application;

[0053] Figure 5 This is a schematic diagram of the semiconductor structure provided in Embodiment 3 of this application;

[0054] Figure 6 This is a schematic flowchart of the semiconductor structure fabrication method provided in Embodiment 4 of this application;

[0055] Figure 7 This is a schematic diagram of the substrate cross-section provided in Embodiment 4 of this application;

[0056] Figure 8 This is a cross-sectional schematic diagram of the structure obtained after forming the trap group in Embodiment 4 of this application;

[0057] Figure 9 This is a cross-sectional schematic diagram of the structure obtained after forming the grid trench in Embodiment 4 of this application;

[0058] Figure 10 This is a cross-sectional schematic diagram of the structure obtained after forming the shielding region and the doped region in Embodiment 4 of this application;

[0059] Figure 11 This is a cross-sectional schematic diagram of the structure obtained after forming the oxide layer and the first conductive layer in Embodiment 4 of this application;

[0060] Figure 12 This is a cross-sectional schematic diagram of the structure obtained after forming the composite gate in Embodiment 4 of this application;

[0061] Figure 13 This is a cross-sectional schematic diagram of the structure obtained after forming the first conductive layer in Embodiment 5 of this application;

[0062] Figure 14 This is a cross-sectional schematic diagram of the structure obtained after forming the first dielectric layer and the second dielectric layer in Embodiment 5 of this application;

[0063] Figure 15 This is a cross-sectional schematic diagram of the structure obtained after forming the second conductive layer in Embodiment 5 of this application;

[0064] Figure 16 This is a cross-sectional schematic diagram of the structure obtained after forming the second conductive layer in Embodiment 6 of this application.

[0065] Explanation of reference numerals in the attached figures:

[0066] 10. Substrate; 101. Base; 102. Buffer layer; 103. Epitaxial layer; 104. JFET region; 20. Well region group; 21. First well region; 22. Second well region; 201. Base region; 202. Source region; 30. Doped region; 40. Composite gate; 401. Gate oxide layer; 402. Gate conductive layer; 403. Extension; 41. First gate; 42. Second gate; 50. Shielding region; 61. First dielectric layer; 62. Second dielectric layer; 63. Third dielectric layer; 71. Front metal layer; 72. Back metal layer. Detailed Implementation

[0067] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0069] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0070] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0071] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0072] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0073] Figure 1 For a composite transistor structure provided in a pair ratio, such as Figure 1 As shown, the cell structure includes spaced-apart composite gates, each containing interconnected and perpendicular trench gates and planar gates. To improve gate reliability, a shielding region surrounding the interface between the composite gate and the substrate is provided at the lower right of the composite gate. While this structure can densify the channel to some extent, it still suffers from problems such as planar channels being effective only on one side, deep P-pillars occupying layout space, difficulty in miniaturizing cell pitch, poor parasitic diode performance, and gate-source capacitance Cgs, which limit the device's power and high-frequency performance.

[0074] Example 1

[0075] Figure 2This embodiment provides a schematic diagram of a semiconductor structure. For ease of understanding, in this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and directions toward the substrate include a third direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and second directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the Y-axis direction, the second direction as the X-axis direction, and the third direction as the Z-axis direction.

[0076] like Figure 2 As shown, this application provides a semiconductor structure, including: a substrate 10, a well region group 20, a doped region 30, and a composite gate 40 disposed within the substrate 10. Figure 2 middle, Figure 2 Image (a) shows a top view of the semiconductor structure. Figure 2 (b) in the figure is a cross-sectional view of the semiconductor structure along line A-A'. Figure 2 (c) in the figure is a cross-sectional view of the semiconductor structure along line B-B'. Figure 2 (d) in the figure is a cross-sectional view of the semiconductor structure along line C-C'. It should be understood that (a)-(d) in the other views also correspond to the top view, line A-A', line B-B' and cross-sectional views of the device in the corresponding steps, respectively. This will not be elaborated on further.

[0077] like Figure 2 As shown, the substrate 10 includes a heavily doped substrate 101, a buffer layer 102, and a lightly doped epitaxial layer 103 arranged sequentially along the OZ direction. The well region group 20 is located on the side near the first surface 10a and includes first well regions 21 spaced apart along the OY direction and extending along the OX direction, and second well regions 22 spaced apart along the OY direction between adjacent first well regions 21, forming a grid-like arrangement in the YOX plane.

[0078] The first well region 21 and the second well region 22 include a generally doped base region 201 and a heavily doped source region 202 located within the base region 201, with a width smaller than the base region 201, to form the source-body region configuration required for the MOSFET structure. Additionally, a separately provided heavily doped region 30 is provided within the second well region 22 to form a PiN diode, which can be reliably grounded through the base region 201. It should be understood that the doped region 30 shown in this example is merely illustrative and may not exceed the depth of the base region 201 as shown, or it may exceed the depth of the base region 201.

[0079] Furthermore, a JFET region 104 is provided near the first surface of the epitaxial layer 103. The doping concentration in the JFET region 104 is higher than that in the epitaxial layer 103, but not heavily doped, in order to reduce the forward on-resistance Ron and the specific on-resistance Rsp of the epitaxial layer 103.

[0080] Within the well region group 20, the substrate 101, buffer layer 102, epitaxial layer 103, and source region 202 are of the first conductivity type, while the base region 201 and doped region 30 are of the second conductivity type. The first conductivity type can be either N-type or P-type, and conversely, the second conductivity type can be either P-type or N-type.

[0081] Furthermore, the cross-sectional ratio along line A-A' to that along line BB is 1:1. If the width ratio is too large, it will increase the proportion of the source region 202 resistor in the overall device, which is not conducive to performance optimization; if the ratio is too small, its effect is no different from that of a conventional trench structure, and it is difficult to reflect the unique advantages of this solution in terms of channel density control and resistance balance.

[0082] Please continue reading. Figure 2 The composite gate 40 is located in the first well region 21 and is composed of a first gate 41 and a second gate 42 arranged alternately along the OX direction, and extends through the well region group 20 into the epitaxial layer 103 along the OZ direction.

[0083] To improve the breakdown voltage of the composite gate 40, a heavily doped second conductivity type shielding region 50 is provided at the bottom of the composite gate 40. This shielding region 50 forms a PN junction with the epitaxial layer 103. During operation, a depletion layer can be formed at its interface, thereby effectively bearing and distributing high voltage, preventing the electric field from concentrating on the bottom of the gate, and thus significantly improving the breakdown voltage and overall reliability of the device.

[0084] Please see Figure 2 In (a), the first gate 41 and the second gate 42 include a gate conductive layer 402 filled in the gate trench, and a gate oxide layer 401 located between the gate conductive layer 402 and the first surface 10a, such that the first gate 41 constitutes a trench gate structure. The difference lies in... Figure 2 As described in (b), the gate conductive layer 402 of the second gate 42 includes an extension 403 covering the second well region 22 and a portion of the first surface 10a in the OY direction, so that the second gate 42 has the function of a planar gate structure while having a vertical channel.

[0085] Please continue reading. Figure 2 The outer surface of the composite gate 40 and the first surface are further provided with a third dielectric layer 63 formed of a high dielectric material, as well as a front metal layer 71 and a back metal layer 72 for electrical connection. Since the above-mentioned film layers are conventional for MOSFETs, they will not be described in detail here.

[0086] like Figure 2 As shown, the front-side metal layer 71 includes a first plug that contacts the doped region 30 along the OX direction to form a PiN structure, and a second plug that contacts the JFET region 104 to form a Schottky contact. The Schottky structure gives the device the advantages of low reverse recovery loss and low reverse turn-off spike. When subjected to surge current, the PiN structure can be turned on and the surge current can be passed through by utilizing the conductivity modulation effect, thereby improving the ultimate performance of the device.

[0087] Furthermore, such as Figure 2 As shown, the first plug can be partially embedded in the substrate 10 along the OZ direction, and the region with the highest doping concentration is in contact with it to reduce contact resistance and improve the electrical performance of the device.

[0088] Figure 3 The current flow direction of the semiconductor structure provided in this embodiment 1 is shown. Path ① is the channel electron flow direction of the trench gate (first gate 41), path ② is the electron flow direction that first flows through the source region below the extension 403 and then adheres to the sidewall of the gate trench, and path ③ is the channel current flow direction of the planar gate (second gate 42). Through the coordinated conduction of the above three paths, the current transport capability and conduction efficiency of the device can be effectively improved.

[0089] Example 2

[0090] Please see Figure 4 In this embodiment, another semiconductor structure is provided, which is the same as that in Embodiment 1. The semiconductor structure also includes a substrate 10, a well group 20, a composite gate 40, a shielding region 50, a third dielectric layer 63, a front metal layer 71, and a back metal layer 72.

[0091] The main difference from Embodiment 1 is that the composite gate 40 further includes a first dielectric layer 61 disposed within the gate conductive layer 402, and a second dielectric layer 62 located between adjacent base regions. The outer surface of the first dielectric layer 61 is surrounded by the gate conductive layer 402 and the gate oxide layer 401, embedded within the gate conductive layer 402, and its bottom surface is flush with the bottom surface below the source region 202. The second plug of the front metal layer 71 penetrates the second dielectric layer 62 along the OZ direction and contacts the JFET region 104. It should be noted that during the fabrication process, if it cannot be guaranteed that the top surface of the first dielectric layer 61 is flush with the bottom surface of the source region 202, its top surface can be slightly higher than the bottom surface of the source region 202.

[0092] For example, the materials of the first dielectric layer 61 and the second dielectric layer 62 include high dielectric materials, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0093] like Figure 4 As shown, in Embodiment 2, compared to Embodiment 1, the first dielectric layer 61 separates the first gate 41 from the source region 202 in the OY direction; and in the OZ direction, the first dielectric layer 61 separates the extension 403 of the second gate 42 from the source region 202. This spatial isolation arrangement effectively reduces the overall gate-source capacitance Cgs of the device, which is beneficial for improving the switching speed and high-frequency performance of the device. The second dielectric layer 62 increases the spacing between the extension 403 and the front metal layer 71 along the OY direction, reducing the risk of breakdown between the gate and source electrodes and improving gate reliability.

[0094] Example 3

[0095] Please see Figure 5 This embodiment provides another semiconductor structure, which is the same as that in embodiment 2, including a first dielectric layer 61 and a second dielectric layer 62.

[0096] The main difference from Embodiment 2 is that the second dielectric layer 62 covers the first surface 10a between adjacent source regions 202, and the extension 403 extends along the OY direction to contact the adjacent extension 403 and covers the top surface of the second dielectric layer 62.

[0097] The front metal layer 71 includes only the first plugs arranged at intervals along the OX direction and in contact with the doped region 30. By adopting this plug layout, reliability problems such as gate-source short circuits caused by the introduction of the second plug in the OY direction when the cell pitch is further reduced can be effectively avoided.

[0098] Example 4

[0099] Please see Figure 6 This embodiment provides a method for fabricating a semiconductor structure, including steps S1 to S4. The following is a description of the method in conjunction with the appendix. Figure 7 To the attached Figure 12 The specific steps of the above preparation method are explained in detail:

[0100] Step S1: Provide substrate 10, specifically as follows Figure 7 As shown.

[0101] The substrate 10, from bottom to top, comprises an N+ substrate 101, an N+ buffer layer 102, and an N- epitaxial layer 103, with nitrogen as the typical doping element. In this embodiment, the typical concentration of the substrate 101 is 1e20cm⁻¹. -3 The typical concentration of buffer layer 102 is 1e18cm. -3 The typical concentration of the epitaxial layer 103 is 1e16cm³. -3 .

[0102] An N-type JFET region 104 is formed in the epitaxial layer 103 by general implantation, with nitrogen as the typical dopant. The typical implantation dose is 1e13cm. -2 .

[0103] Step S2: Form a well region group 20 extending inward through the first surface 10a of the substrate; the well region group 20 includes first well regions 21 spaced apart along the OY direction and extending along the OX direction, and second well regions 22 spaced apart along the OX direction and connecting adjacent first well regions 21; wherein, the first well region 21 and the second well region 22 include a base region 201 and a source region 202 whose top surface is within the top surface of the base region 201, as shown in the specific structure. Figure 8 As shown.

[0104] In this embodiment, the cross-sectional width along line A-A' is 2 μm, and the cross-sectional width along line BB is 2 μm. The doping concentration of base region 201 is 1e18cm. -3 The implantation depth is 1 μm; the implanted element in source region 202 is an N-type impurity ion (e.g., nitrogen, phosphorus, arsenic), with a doping concentration of 1e19cm. -3 ~5e20cm -3 For example, 1e19cm -3 1e20cm -3 Or 5e20cm -3 The implantation depth is approximately 0.02 μm to 0.3 μm, for example, 0.02 μm, 0.1 μm, 0.2 μm, or 0.3 μm. In this embodiment, the doping concentration of the source region is 1.5e20 cm⁻¹. -3 The injection depth was 0.15 μm.

[0105] Step S3: Form a doped region 30 located in the second well region 22, such that the doped region 30 penetrates the source region 202 through the first surface 10a and extends into the substrate to form an ohmic contact.

[0106] Prior to step S3, this embodiment further includes forming a gate trench extending in the OX and OZ directions within the central etching of the first well region 21, specifically as follows: Figure 9 As shown. The width of the gate trench is smaller than the width of the first well region 21, and the width ranges from 0.5 to 1.5 μm (e.g., 0.5 μm, 1 μm, or 1.5 μm, etc.), and its depth ranges from 0.5 to 1.2 μm (e.g., 0.5 μm, 1 μm, or 1.2 μm, etc.). In this embodiment, the typical values ​​for the width and depth of the gate trench are 0.8 μm and 1 μm, respectively.

[0107] Subsequently, based on the photolithography, a high-current equipment can be used to select aluminum as the dopant element, implanting P+ at the bottom of the gate trench to form a shielding region 50, and implanting P+ between adjacent gate trenches to form a doped region 30. The specific structure is as follows. Figure 10 As shown. The doping concentration is 1e20cm. -3 ~1e21cm -3 (For example, 1e20cm) -3 5e20cm -3 or 1e21cm -3 The typical injection depth is approximately 0.5 to 1.5 μm (e.g., 0.5 μm, 1 μm, or 1.5 μm).

[0108] The typical doping concentration in this embodiment is 3e20cm. -3 The typical injection depth is approximately 0.5~1.5μm, and the injection energy is adjusted according to the actual depth requirements.

[0109] After all injections are completed, high-temperature annealing is performed to activate the impurities. The process conditions are 1750°C, 30 min, and Ar atmosphere. This will not be described further as it is not the focus of this embodiment.

[0110] Step S4: Form a composite gate 40 that extends through the first well region 21 along the OZ direction; the composite gate 40 includes: a first gate 41 located between adjacent doped regions 30, and a second gate 42 connected to the adjacent first gate 41; the second gate 42 includes an extension 403 covering the top surface of the first well region 21.

[0111] Specifically, an oxidation process (e.g., thermal oxidation or high-temperature oxidation) is used to form a gate oxide layer 401 covering the gate trench and the first surface 10a to improve the flatness of the gate trench sidewalls and reduce the interface states. Then, an arbitrary deposition process is used to form a first conductive layer filling the gate trench and the first surface 10a, with the specific structure as follows: Figure 11 As shown.

[0112] The first conductive layer is partially removed using photolithography and etching processes, while the first conductive layer within the gate trench and on the top surface of the second well region 22 is retained to form the gate conductive layer 402. The specific structure is as follows: Figure 12 As shown.

[0113] After step S4, the following is also included:

[0114] In step S5, after depositing the third dielectric layer 63 covering the gate conductive layer 402 and the first surface 10a, the third dielectric layer 63 and part of the gate oxide layer 401 are etched to form a via. Preferably, the bottom surface of the via is flush with the bottom surface of the source region 202 and is at the peak concentration of the doping region 30, so as to facilitate the formation of a good P-type ohmic contact.

[0115] Furthermore, the width of the vias on both sides of the first gate is extended along the OY direction to increase the ohmic contact area between the front metal layer 71 and the source region 202. Then, conventional front metallization, back thinning, and back metallization are performed, as shown in the specific structure. Figure 2 As shown.

[0116] It should be understood that, although Figure 6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 6 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0117] Example 5

[0118] The main difference from Example 4 is that the preparation method provided in Example 5 further includes: in the same process steps, forming a first dielectric layer 61 located inside the composite gate 40, close to the source region 202, and a second dielectric layer 62 located on the first surface 10a between adjacent base regions 201, in contact with the extension 403.

[0119] In step S4, after forming the first conductive layer, the first conductive layer is etched back to ensure its depth is at least flush with the bottom surface of the source region 202. The specific structure is as follows: Figure 13 As shown.

[0120] Subsequently, a first dielectric material layer is deposited and etched (not shown), retaining only the first dielectric material layer that contacts the sidewall of the source region 202 and covers the first surface 10a between adjacent base regions 201. The remaining first dielectric material layer in contact with the source region 202 forms the first dielectric layer 61, and the first dielectric material layer covering the surface of the JFET region 104 forms the second dielectric layer 62. The specific structure is as follows: Figure 14 As shown. Furthermore, by combining deposition, photolithography, and etching processes, a second conductive layer is formed covering the first dielectric layer 61, the second dielectric layer 62, and the first conductive layer, as shown in the specific structure. Figure 15 As shown.

[0121] After performing step S5, depositing the third dielectric layer 63 covering the gate conductive layer 402 and the first surface 10a, an etching process is used to sequentially etch portions of the third dielectric layer 63, the second conductive layer, the gate oxide layer 401, and the substrate to form vias extending along the OX direction and arranged along the OY direction; after performing front and back metallization, the specific structure is as follows: Figure 4 As shown.

[0122] Example 6

[0123] The main difference from Example 5 is that a second conductive layer is formed using deposition, photolithography, and etching processes, exposing the top surface of the second dielectric layer. The specific structure is as follows: Figure 16 As shown.

[0124] Therefore, in step S5, the etching process only requires sequentially etching the third dielectric layer 63, the second dielectric layer 62, the gate oxide layer 401, and the substrate to form a via. When any two of the materials in the third dielectric layer 63, the second dielectric layer 62, and the gate oxide layer 401 are the same, a corresponding etch stop layer process can be saved, reducing the number of etching steps and lowering the process cost.

[0125] Example 7

[0126] The main difference from Example 5 is that, to avoid gate-source punch-through caused by process deviations due to the close proximity of adjacent extensions 403, vias are etched to form spaced holes along the OX and OY directions, with each via corresponding to a doped region 30. The structure obtained after performing front and back metallization is as follows: Figure 5 As shown.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: A well region group extends inwardly via a first surface of a substrate, including a first well region spaced apart along a first direction and extending along a second direction, and a second well region spaced apart along the second direction and connecting adjacent first well regions; wherein the first well region and the second well region include a base region and a source region with its top surface in the top surface of the base region; A doped region, located within the second well region, extends through the first surface through the source region and into the substrate, for forming an ohmic contact; A composite gate, extending through the first well region in a direction toward the substrate, includes: a first gate located between adjacent doped regions, and a second gate connected to the adjacent first gate; the second gate includes an extension covering the top surface of the first well region; the extension includes a conductive material; The first direction and the second direction are parallel to the first surface and perpendicular to each other.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: The first dielectric layer is located within the composite gate, on the side closer to the source region; The second dielectric layer is located on the first surface between adjacent base regions and is in contact with the extension. The top surface of the first dielectric layer is located between the top surface of the composite gate and the first surface, and the bottom surface is flush with the bottom surface of the source region; the first dielectric layer located within the second gate covers the top surface of the source region.

3. The semiconductor structure according to claim 2, characterized in that, Also includes: The JFET region extends into the substrate via the first surface, and its bottom surface is flush with the base region. A third dielectric layer covers the outer surface of the composite gate; The shielding area is located on the bottom surface of the composite grid, and the top surface is located inside the bottom surface of the composite grid; A front metal layer, located on the third dielectric layer, includes a first plug extending toward the substrate to contact the doped region; The first plug forms a PiN structure with the doped region and the substrate.

4. The semiconductor structure according to claim 2, characterized in that, The extension is located on the outer surface of the first dielectric layer and extends along the first direction to contact the adjacent extension.

5. The semiconductor structure according to claim 3, characterized in that, The front metal layer also includes: The second plug is alternately arranged with the first plug along the second direction and penetrates the second dielectric layer in the direction toward the substrate, such that the bottom surface forms a Schottky contact with the first surface.

6. The semiconductor structure according to any one of claims 2-5, characterized in that, The composite gate includes: A gate oxide layer is located on the inner surface of the gate trench and extends along the first direction to contact the bottom surface of the first dielectric layer, the extension, and the second dielectric layer. The gate conductive layer includes an embedded portion and an extension portion that are filled within the gate trench and have a top surface higher than the first surface; The first dielectric layer is located within the gate conductive layer.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A group of well regions extending inwardly through a first surface of a substrate is formed; the group of well regions includes a first well region spaced apart along a first direction and extending along a second direction, and a second well region spaced apart along the second direction and connected to adjacent first well regions; wherein the first well region and the second well region include a base region and a source region with its top surface in the top surface of the base region. A doped region is formed within the second well region, such that the doped region penetrates the source region through the first surface and extends into the substrate to form an ohmic contact; A composite gate is formed that extends through the first well region in a direction toward the substrate; the composite gate includes: a first gate located between adjacent doped regions, and a second gate connected to the adjacent first gate; the second gate includes an extension covering the top surface of the first well region; the extension includes a conductive material; The first direction and the second direction are parallel to the first surface and perpendicular to each other.

8. The preparation method according to claim 7, characterized in that, Also includes: In the same process steps, a first dielectric layer located inside the composite gate, close to the source region, and a second dielectric layer located on a first surface between adjacent base regions, in contact with the extension, are formed simultaneously. The top surface of the first dielectric layer is located between the top surface of the composite gate and the first surface, and the bottom surface is flush with the bottom surface of the source region; the first dielectric layer located within the second gate covers the top surface of the source region.

9. The preparation method according to claim 8, characterized in that, The formation of the first dielectric layer and the second dielectric layer includes: The substrate is etched to form gate trenches spaced apart along the first direction and extending along the second direction; After forming a gate oxide layer covering the inner surface of the gate trench and the first surface, a first conductive layer is formed that fills the gate trench. The first conductive layer is etched back so that its top surface is flush with the bottom surface of the source region; The first dielectric layer is formed on the top surface of the first conductive layer near the source region, and the second dielectric layer is formed on the first surface between adjacent base regions.

10. The preparation method according to claim 9, characterized in that, Also includes: A second conductive layer is formed covering the first dielectric layer and the second dielectric layer, and a third dielectric layer is formed covering the second conductive layer; Above the doped region, a via is formed extending in the direction toward the substrate to contact the substrate; A metal layer is formed to fill the via and cover the top surface of the third dielectric layer.

11. The preparation method according to claim 10, characterized in that, The through holes are spaced apart along the first direction and extend along the second direction; or The through holes are spaced apart along the first direction.

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