A high temperature resistant power device

Abstract

The application discloses a high-temperature-resistant power device, which selects a silicon carbide wafer as an N-type substrate; an N-type drift layer is epitaxially grown on the surface of the N-type substrate, N-type source active areas are formed by injecting the top of the N-type drift layer all over, a collecting area is arranged on one side of the N-type drift layer, and a gate active area and an emission area of a parasitic BJT are arranged on the other side of the N-type drift layer and are intercepted by a deep N well to be divided into two parts; the gate active area is an upper part, and the emission area of the parasitic BJT is a lower part. The device has the characteristics that the parasitic bipolar junction transistor on the device will inject base region minority carriers at high temperature, thereby showing resistance to high temperature, and only a deep well process step needs to be added compared to a traditional manufacturing process of a longitudinal power JFET.

Description

Technical Field

[0001] This invention belongs to the field of junction field-effect transistor technology, and specifically relates to a high-temperature resistant power device. Background Technology

[0002] Compared to MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), JFETs generally have a much smaller specific on-resistance. On-resistance is the ratio of specific on-resistance to device area. This means that to manufacture a high-power device chip with the same on-resistance, a JFET chip occupies a significantly smaller area. Even though a JFET must be connected in series with an additional low-voltage silicon-based MOSFET to form a normally-off composite device (Cascode JFET) to eliminate the dependence on special drive circuitry, the manufacturing cost is still a fraction of that of manufacturing a power MOSFET. On-resistance is one of the key performance indicators (KR) for power transistors. Low-dropout linear regulators (LDOs) and switch-mode power supplies (SMPS) are the main application scenarios for power transistors, both requiring the power transistor to handle a certain amount of current, the same as the load current. A low on-resistance signifies a strong current-carrying capacity of the power transistor. In a Smart Power Management System (SMPS), a stronger current-carrying capacity results in a smaller source-drain voltage difference required for the power transistor to carry the same current, lower conduction losses, and higher power conversion efficiency. If the current-carrying capacity is insufficient, the switching node voltage of the SMPS under heavy load will deviate significantly from the ideal PWM (Pulse Width Modulation) waveform, potentially leading to abnormal output voltage values. In this case, the SMPS will lose its switching characteristics, the output voltage ripple will disappear, and it will degenerate into a completely DC output consistent with an LDO. In an LDO, while the current-carrying capacity of the power transistor is unrelated to efficiency, its strength determines whether the power regulator of the LDO can carry the same current as the load current while maintaining a constant output voltage under heavy load. In conclusion, the performance of a power management circuit largely depends on the on-resistance of the power transistor. Furthermore, because its value is determined by the device area, on-resistance is a major source of cost in device development and mass production. Against this backdrop, vertical JFET devices stand out among numerous power devices and secure a place in the market solely because they can achieve the same on-resistance and current carrying capacity at a lower cost.

[0003] Existing technologies include the paper X. Song and Y. Du, "Study of the SiC JFET ReverseConduction and Reverse Blocking Characteristics," 2019 IEEE Applied PowerElectronics Conference and Exposition (APEC), Anaheim, CA, USA, 2019, Pages 2751-2756 describe a silicon carbide substrate doped with a high concentration of nitrogen atoms as donor impurities. An electrode—the drain—is led out from the back of the substrate. A low-nitrogen-atom-concentration drift layer is then epitaxially grown on this substrate, serving as the main component to withstand the high voltage across the source and drain terminals. Next, a thin layer with a high nitrogen atom doping concentration is implanted across the entire top of the epitaxial wafer, creating conditions for the formation of the ohmic contact of the source electrode. Then, a masking layer is deposited, coated with photoresist, and photolithography and etching are performed at designated locations. Gas is introduced into the gaps in the masking layer to react with the underlying silicon carbide, etching parallel trenches. Acceptor impurities, aluminum atoms, are then implanted into the same gaps, forming the active region of the gate in the area adjacent to the bottom and sidewalls of the trenches in the drift layer. At this point, the basic structure of the classic vertical silicon carbide JFET power device is fully formed.

[0004] In summary, the existing technology has an overly simple structure, and its high-temperature robustness cannot be guaranteed. High temperatures reduce carrier mobility, which in turn leads to a decrease in the current-carrying capacity of the power JFET, ultimately affecting the performance of the entire circuit. The purpose of this invention is to improve the structure of the existing classic vertical silicon carbide JFET. The specialized new structure gives it high-temperature resistance, so even when the device operates in a high-temperature environment, its current-carrying capacity only decreases slightly, or even increases, compensating for the loss caused by the decrease in carrier mobility. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a high-temperature resistant power device. This device is resistant to high temperatures because the bipolar junction transistor parasitic on it undergoes minority carrier injection in the base region at high temperatures. Moreover, compared with the traditional manufacturing process of vertical power JFET, it only requires the addition of a deep well process step.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A high-temperature resistant power device includes an N-type substrate and an N-type drift layer on the surface of the N-type substrate. The N-type drift layer has a convex structure that is high in the middle and low on both sides. The top of the middle part is fully injected to form an N-type source active region. One side is the collector region, and the other side is the gate active region and the emitter region of the parasitic BJT, which are cut off into upper and lower parts by a deep N-well. The gate active region is the upper part, and the emitter region of the parasitic BJT is the lower part.

[0007] The current collector region, the gate active region, and the emitter region of the parasitic BJT have the same composition, which is an aluminum impurity atom implantation region; The deep N-well is a region for injecting nitrogen impurity atoms.

[0008] The growth of the N-type drift layer is completed in two stages, and the top height of the epitaxial layer after the first growth is flush with the top of the deep N-well. In the second growth, the epitaxial layer reaches the designed final height, resulting in a deep N-well.

[0009] The N-type drift layer is etched into trenches, and then gas that reacts with the N-type drift layer is injected to form P-type regions. The gate active region, the emitter region of the parasitic BJT, and the P-type gate active region constitute the P-type region. The concentration of the emitter region is higher than that of the collector region. The concentration of the P-type region is set to be greater than that of the drift layer but less than that of the deep N-well. The formed P-type region is both the trench and the P-type gate active region, as well as the collector region of the parasitic BJT. Finally, the channel of the JFET is used as the base region.

[0010] The deep well is a doped region of the same type as the JFET channel inserted 0.1~0.2um below the gate active region.

[0011] The gate active region controls the pinch-off and turn-on of the JFET channel. The emitter region of the parasitic BJT is used to introduce the BJT (bipolar junction transistor). The emitter region, N-type drift layer and collector region of the parasitic BJT together constitute this BJT. At high temperature, the emitter region of the BJT is activated and injects carriers into the base region, i.e., the channel, thereby reducing the on-resistance of the JFET and compensating for the loss of current carrying capacity due to the decrease in carrier mobility at high temperature.

[0012] The N-type substrate has a height of 1~10µm, a width of 1.7~1.9µm, and a doping concentration of 1e17~1e20cm. -3 ; The N-type drift layer is 3–6 μm high, 1.7–1.9 μm wide, and has a doping concentration of 5e¹⁶–1.5e¹⁷ cm⁻¹. -3 .

[0013] The active region of the N-type source exhibits a Gaussian distribution, with an effective depth of 0.02–0.2 μm, a width of 0.7–0.9 μm, and a peak concentration of 1e18–1e20 cm⁻¹. -3 .

[0014] The deep N-well has a height of 0.2~0.3 μm, a width of 0.5~0.7 μm, a depth of 1.6~1.8 μm, and a doping concentration of 1e17~5e17 cm⁻¹. -3 .

[0015] The trench and collector area have a height of 1.4~1.7 μm, a width of 0.4~0.6 μm, and an inclination of 4~7°; the right side of the P-region is 0.1~0.2 μm from the sidewall, the bottom edge is 0.6~0.9 μm from the bottom of the trench, and the doping concentration is 5e16~1.5e17 cm⁻¹. -3 .

[0016] The trench and gate active region have a trench height of 1.4~1.7µm, a width of 0.4~0.6µm, and an inclination of 4~7°; the P-region has a left side wall distance of 0.1~0.2µm, a bottom edge distance of 0.2~0.3µm from the trench bottom, and a doping concentration of 2.5e17~3.5e17cm. -3 .

[0017] The parasitic BJT's P-type emitter region has a height of 0.2–0.3 μm, a width of 0.4–0.6 μm, and a doping concentration of 2.5e¹⁷–3.5e¹⁷ cm⁻¹. -3 .

[0018] The beneficial effects of this invention are: This invention addresses the degradation of current-carrier mobility at high temperatures due to decreased carrier mobility, based on the classic vertical silicon carbide JFET power device structure. It involves inserting a nitrogen-doped region, called a deep N-well, at a certain distance below the trench. Each pair of deep N-wells is separated by a trench without insertion, resulting in a higher concentration than the gate active region. This effectively divides the gate region in half, introducing a parasitic BJT portion. The emitter region of the parasitic BJT forms the lower part of the gate region, the base region forms the JFET channel, and the collector region forms the other half of the gate region without the deep N-well. Simultaneously, the collector region and the upper part of the original gate region still serve as the gate active region of the new structure, jointly controlling the pinch-off and opening of the channel. This dual-gate structure effectively reduces leakage current.

[0019] The improved structure achieves high-temperature resistance by injecting holes from the emitter region of the BJT into the base region (channel) at high temperatures, thereby enhancing the current-carrying capacity of the power JFET. At the same time, the manufacturing process has not become overly complex. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the improved vertical JFET overall structure of the present invention.

[0021] Figure 2 The output characteristic curves are shown for Vgs=0 at various temperatures.

[0022] Figure 3This is the first saturation region that the drain voltage enters as it increases.

[0023] Figure 4 These represent the voltage values ​​at various points on the device.

[0024] Figure 5 The electron mobility at Vds=50V is a trend of change with temperature (temperature increases sequentially from top to bottom and from left to right).

[0025] Figure 6 The trend of hole mobility with temperature when Vds=50V.

[0026] Figure 7 The trend of hole concentration with temperature when Vds=50V.

[0027] Figure 8 The hole concentration varies with drain voltage at a device temperature of 125℃ (voltage increases sequentially from top to bottom and from left to right). Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings.

[0029] like Figure 1 As shown, based on the structure of a classic vertical trench power silicon carbide JFET, a doped region of the same type as the JFET channel, namely deep well 4, is inserted 0.1~0.2um below the gate active region 6. The two wells (the two closest deep wells 4 in a series of cells) are separated by a collector region without a deep well below. 5 .

[0030] The inserted deep well 4 divides the original gate active region into the gate active region 6 and the emitter region 7 of the parasitic BJT. Part of it still serves as the gate active region 6 to control the pinch-off and turn-on of the JFET channel, while the emitter region 7 of the parasitic BJT serves to introduce the BJT (bipolar junction transistor) portion. The other half of the collector region, which is the N-type drift layer 2 of the base region and the collector region 5 without the inserted deep N-well 4, serves as the collector region. 5 Together, they constitute this BJT. At high temperatures, the emitter region of the BJT is activated and injects carriers into the base region, i.e., the channel, thereby reducing the on-resistance of the JFET and compensating for the loss of current carrying capacity due to the decrease in carrier mobility at high temperatures.

[0031] accomplish Figure 1 The required process steps for the device structure shown are as follows: First, a silicon carbide wafer with appropriate thickness and doping concentration is selected as the N-type substrate 1. Then, an N-type drift layer 2 is epitaxially grown on the surface of the N-type substrate 1. However, it needs to be grown in two stages. After the first growth, the top height of the epitaxial layer is flush with the top of the deep N-well 4, which facilitates the subsequent deposition of the masking layer, coating, photolithography, etching, and implantation at the designated position through the notch on the masking layer to form the deep N-well 4. After the second growth, the epitaxial layer reaches the designed final height, thus completing the deep N-well 4 process. Next, N-type source active region 3 is formed by full-area implantation on the top of the epitaxial wafer. This process is repeated, involving deposition and etching. Then, a gas that reacts with silicon carbide is introduced to etch trenches into the silicon carbide, followed by implantation to form P-type regions. The concentration of the emitter region 7 needs to be higher than that of the collector region. 5 The concentration of the P-type region needs to be higher than that of the drift layer, so the grooving and implantation also need to be completed in two batches. The P-type region formed by the first batch of implantation needs to meet the deep N-well 4. 2 The concentration is lower than that of the deep N-well 4. Under the coverage of the deep N-well 4, this batch of P-type regions is cut in half into two parts, and parasitic BJTs are introduced at the same time. The upper part is the gate active region 6, and the lower part is the emitter region 7 of the parasitic BJT. The second batch needs to avoid the deep N-well 4. The resulting P-type region is both the trench and the P-type gate active region 5, as well as the collector region of the parasitic BJT. Finally, the channel of the JFET is used as the base region.

[0032] The N-type substrate has a height of 1~10µm, a width of 1.7~1.9µm, and a doping concentration of 1e17~1e20cm. -3 ; The N-type drift layer has a height of 3-6 μm, a width of 1.7-1.9 μm, and a doping concentration of 5e16-1.5e17 cm⁻¹. -3 .

[0033] The active region of the N-type source exhibits a Gaussian distribution, with an effective depth of 0.02–0.2 μm, a width of 0.7–0.9 μm, and a peak concentration of 1e18–1e20 cm⁻¹. -3 .

[0034] The deep N-well 4 has a height of 0.2~0.3 μm, a width of 0.5~0.7 μm, a depth of 1.6~1.8 μm, and a doping concentration of 1e17~5e17 cm⁻¹. -3 .

[0035] Trench and P-type gate active region (left): 5. Trench height 1.4~1.7µm, width 0.4~0.6µm, tilt 4~7°; P-region penetration into sidewall 0.1~0.2µm, bottom edge distance from trench bottom 0.6~0.9µm, doping concentration 5e16~1.5e17cm. -3 .

[0036] Trench and P-type gate active region (right): 6 trenches are 1.4~1.7µm high, 0.4~0.6µm wide, and tilted at 4~7°; the P-region extends 0.1~0.2µm into the sidewall, with the bottom edge 0.2~0.3µm from the trench bottom and a doping concentration of 2.5e17~3.5e17cm. -3 .

[0037] The parasitic BJT's P-type emitter region 7 has a height of 0.2–0.3 μm, a width of 0.4–0.6 μm, and a doping concentration of 2.5e¹⁷–3.5e¹⁷ cm⁻¹. -3 .

[0038] The voltage relationships of each electrode in a JFET are as follows: Figure 4 As shown, the source voltage 3 and the voltages of the trench and P-type gate active regions (left) 5 and trench and P-type gate active regions (right) 6 on both sides are set to 0V. The parasitic BJT emitter 7 is shorted to the JFET drain 1. The voltages of the two electrodes 1 and 7 gradually increase from 0V to 50V. Since the emitter region 7 is located inside the epitaxial layer 2, in actual production, the emitter region 7 can extend forward or backward to obtain space for vias so as to contact the corresponding metal layer.

[0039] like Figure 2 As shown, at any temperature, the output characteristic curve of the JFET exhibits two saturation regions. As the drain voltage rises from 0V to a certain value, the JFET first enters the first saturation region. Figure 3 In the saturation region, the drain voltage continues to rise while the drain current remains unchanged. However, when the drain voltage is too high, the JFET will leave the saturation region again, and the drain current will start to increase again, and the rate of increase will also increase. Then the trend slows down, and eventually it will enter the second saturation region, which is like introducing a "step". The higher the temperature, the earlier the "step" will appear and the higher and steeper it will be. Therefore, the introduction of the "step" improves the current carrying capacity of the JFET at high temperatures.

[0040] Figure 5 , Figure 6 The results show that as the temperature increases (from top to bottom and from left to right), the mobility of charge carriers (including electrons and holes) at all points in the device shows a decreasing trend, which is consistent with the theoretical analysis. This also proves that the number of charge carriers in the JFET channel does indeed increase with increasing temperature, compensating for the loss of current carrying capacity caused by the mobility.

[0041] Figure 7 This shows that after the JFET enters the second saturation region, the concentration of holes injected into the JFET channel increases with the temperature. This is why the higher the temperature, the higher the "step".

[0042] like Figure 8As shown, when the operating temperature of the JFET is fixed at 125°C and the voltage difference between the source and drain is increased, it can be seen that the hole concentration in the JFET channel and the deep N-well does increase significantly. At this time, the opening degree of the parasitic BJT also increases. Before the JFET enters the second saturation region, the emitter region will continuously inject more and more holes into the base region, that is, the JFET channel.

Claims

1. A high-temperature resistant power device, characterized in that, The structure includes an N-type substrate (1) and an N-type drift layer (2) on the surface of the N-type substrate (1). The N-type drift layer (2) is a convex structure with a high middle and low sides. The top of the middle part is fully injected to form an N-type source active region (3). One side of it is a collector region (5), and the other side is a gate active region (6) and a parasitic BJT emitter region (7) that are cut in half by a deep N-well (4). The gate active region (6) is the upper part, and the parasitic BJT emitter region (7) is the lower part.

2. The high-temperature resistant power device according to claim 1, characterized in that, The current collector region (5), the gate active region (6), and the emitter region (7) of the parasitic BJT have the same composition, which is an aluminum impurity atom implantation region; The deep N-well (4) is a nitrogen impurity atom injection region.

3. The high-temperature resistant power device according to claim 1, characterized in that, The growth of the N-type drift layer (2) is completed in two stages. After the first growth, the top height of the epitaxial layer is flush with the top of the deep N-well (4). In the second growth, the epitaxial layer reaches the designed final height, resulting in a deep N-well (4).

4. A high-temperature resistant power device according to claim 3, characterized in that, The N-type drift layer (2) is etched into trenches, and then gas that reacts with the N-type drift layer (2) is injected to form P-type regions. The gate active region (6), the emitter region (7) of the parasitic BJT, and the P-type gate active region (5) constitute the P-type region. The concentration of the emitter region (7) is higher than that of the collector region (6). 5） The concentration is set such that the concentration in the P-type region is greater than that in the drift layer ( 2） The concentration is less than that of the deep N-well (4), and the resulting P-type region is both the trench and the P-type gate active region (5), as well as the collector region of the parasitic BJT. Finally, the channel of the JFET serves as the base region.

5. A high-temperature resistant power device according to claim 4, characterized in that, The deep well (4) is a doped region of the same type as the JFET channel inserted 0.1~0.2um below the gate active region (6).

6. A high-temperature resistant power device according to claim 5, characterized in that, The gate active region (6) controls the pinch-off and turn-on of the JFET channel. The emitter region (7) of the parasitic BJT is used to introduce the BJT. The emitter region (7), the N-type drift layer (2), and the collector region (5) of the parasitic BJT together constitute this BJT. At high temperature, the emitter region of the BJT is activated and injects carriers into the base region, i.e., the channel, reducing the on-resistance of the JFET and compensating for the loss of current carrying capacity due to the decrease in carrier mobility at high temperature.

7. A high-temperature resistant power device according to claim 6, characterized in that, N-type substrate (1) Height 1~10um, width 1.7~1.9um, doping concentration 1e17~1e20cm -3 ; The N-type drift layer (2) has a height of 3~6 μm, a width of 1.7~1.9 μm, and a doping concentration of 5e16~1.5e17 cm. -3 .

8. A high-temperature resistant power device according to claim 6, characterized in that, The active region of the N-type source (3) has a Gaussian distribution, an effective depth of 0.02~0.2 μm, a width of 0.7~0.9 μm, and a peak concentration of 1e18~1e20 cm⁻¹. -3 ; The deep N-well (4) has a height of 0.2~0.3 μm, a width of 0.5~0.7 μm, a depth of 1.6~1.8 μm, and a doping concentration of 1e17~5e17 cm. -3 .

9. A high-temperature resistant power device according to claim 6, characterized in that, Trench and collector area (5) Trench height 1.4~1.7um, width 0.4~0.6um, inclination 4~7°; P region enters the sidewall 0.1~0.2um, bottom edge distance from the bottom of the trench 0.6~0.9um, doping concentration 5e16~1.5e17cm -3 ; Trench and gate active region (6) Trench height 1.4~1.7um, width 0.4~0.6um, inclination 4~7°; P region enters the sidewall 0.1~0.2um, bottom edge distance from trench bottom 0.2~0.3um, doping concentration 2.5e17~3.5e17cm -3 ; The P-type emitter region (7) of the parasitic BJT has a height of 0.2~0.3 μm, a width of 0.4~0.6 μm, and a doping concentration of 2.5e17~3.5e17 cm⁻¹. -3 .

10. A method for preparing a high-temperature resistant power device according to any one of claims 1-9, comprising the following steps: A silicon carbide wafer is selected as the N-type substrate (1); an N-type drift layer (2) is epitaxially grown on the surface of the N-type substrate (1). The growth is completed in two stages. After the first growth, the top height of the epitaxial layer is flush with the top of the deep N-well (4), which facilitates the subsequent deposition of the masking layer, coating, photolithography, etching, and injection at the designated position through the gap in the masking layer to form the deep N-well (4). After a second growth, the epitaxial layer reaches the designed final height, thus completing the deep N-well (4) process; Then, an N-type source active region (3) is formed by full-area implantation on the top of the epitaxial wafer. Similarly, it is deposited and etched, and then a gas that can react with silicon carbide is introduced to etch trenches into the silicon carbide and then implanted to form each P-type region. The concentration of the emitter region (7) is higher than that of the collector region ( 5） The concentration of the P-type region formed by the first batch of injection is to meet the deep N-well (4), and the concentration of the P-type region is set to be greater than that of the drift layer (4). 2） The concentration is less than that of the deep N-well (4). Under the coverage of the deep N-well 4, the P-type region is cut in half into two parts, and parasitic BJTs are introduced at the same time. The upper part is the gate active region (6), and the lower part is the emitter region (7) of the parasitic BJT. The second batch needs to avoid the deep N-well (4). The P-type region formed is both the trench and the P-type gate active region (5), as well as the collector region of the parasitic BJT. Finally, the channel of the JFET is used as the base region.

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