Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, a gate, a source and a drain. The semiconductor body comprises a first region, a second region and a buried layer. The buried layer is arranged between the first surface and the second surface of the semiconductor body. The first region is arranged between the first surface and the second surface and penetrates through the buried layer. The second region is located on the first surface, and at least part of the second region is in contact with the buried layer. The first region is of a first conductive type, and the buried layer and the second region are of a second conductive type. The gate forms an ohmic contact with the second region. The source is located on part of the first surface. The drain is located on the second surface. The JFET resistance is reduced, the regulation ability on the current channel is strengthened, and the switching speed and reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide trench devices have advantages such as high current density and small cell pitch, and are widely used. Among them, silicon carbide JFET devices have advantages in long-term reliability. However, in existing silicon carbide JFET devices, the JFET region resistance is relatively high, which affects the device performance. Summary of the Invention

[0003] This application provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which reduces JFET resistance, enhances the control capability of the current channel, and improves the switching speed and reliability of the device.

[0004] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a first region, a second region, and a buried layer. The buried layer is disposed between the first surface and the second surface. The first region is disposed between the first surface and the second surface and penetrates the buried layer. The second region is located on the first surface and at least part of the second region is in contact with the buried layer. The first region is of a first conductivity type, and the buried layer and the second region are of a second conductivity type. A gate is located on a portion of the first surface and at least covers the second region, forming an ohmic contact with the second region; The source electrode is located on a portion of the first surface; The drain electrode is located on the second surface.

[0005] Optionally, the semiconductor body further includes a third region of the first conductivity type, the third region being located on the first surface and not overlapping with the second region; the orthographic projection of the first region on the second surface is at least within the orthographic projection of the third region on the second surface; in the thickness direction of the semiconductor body, the third region and the first region are spaced apart; the thickness direction is the direction from the first surface to the second surface. The source electrode is located on a portion of the first surface and at least covers the third region, forming an ohmic contact with the third region.

[0006] Optionally, the second region includes a first sub-region and a second sub-region disposed along the thickness direction; the first sub-region is located on the first surface, and the second sub-region is located on the side of the first sub-region away from the first surface; the second sub-region is in contact with the first sub-region and the buried layer, respectively. In a first direction, the width of the second sub-region is smaller than the width of the first sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the interval and the projection of the second region in the first direction overlap.

[0007] Optionally, the second region includes a first sub-region, a second sub-region, and a third sub-region disposed along the thickness direction; the first sub-region is located on the first surface, the second sub-region is in contact with the first sub-region and the third sub-region respectively; the third sub-region is in contact with the buried layer; In a first direction, the width of the second sub-region is smaller than the width of the third sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the interval and the projection of the second region in the first direction overlap.

[0008] Optionally, along the thickness direction, the width of the second sub-region in the first direction is set to be non-uniform.

[0009] Optionally, along the thickness direction, the width of the second sub-region gradually increases in the first direction.

[0010] Optionally, the third region includes at least two sub-regions disposed along the thickness direction, wherein the at least two sub-regions include a fourth sub-region and a fifth sub-region; the fourth sub-region is located on the first surface, and the fifth sub-region is located on the side closest to the second surface; The width of the fifth sub-region in the first direction is greater than the width of the fourth sub-region in the first direction; or, the width of the fifth sub-region in the first direction is less than the width of the fourth sub-region in the first direction; the first direction is the direction from the second region to the third region, and is perpendicular to the thickness direction.

[0011] Optionally, the at least two sub-regions further include at least one sixth sub-region; the sixth sub-region is located between the fourth sub-region and the fifth sub-region; In the thickness direction, the widths of the fourth sub-region, the sixth sub-region, and the fifth sub-region are arranged in an increasing or decreasing manner in the first direction.

[0012] Optionally, the orthographic projection of the fifth sub-region on the second surface at least covers the orthographic projection of the first region on the second surface.

[0013] In a second aspect, embodiments of the present invention provide a power module, including a substrate and at least one semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0014] Thirdly, embodiments of the present invention provide a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0015] Fourthly, embodiments of the present invention provide a vehicle including a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0016] Fifthly, embodiments of the present invention provide a method for fabricating a semiconductor device, comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a first region, a second region and a buried layer; the buried layer is disposed between the first surface and the second surface; the first region is disposed between the first surface and the second surface and penetrates the buried layer; the second region is located on the first surface and at least part of the second region is in contact with the buried layer; the first region is of a first conductivity type, and the buried layer and the second region are of a second conductivity type; A source and a gate are formed on the first surface; wherein the gate at least covers the second region and forms an ohmic contact with the second region; A drain electrode is formed on the second surface.

[0017] Optionally, the semiconductor body further includes a third region of the first conductivity type; Provide semiconductor bodies, including: Provide substrate; A first semiconductor layer is formed on one side of the substrate; The buried layer is formed on the surface of the first semiconductor layer; A second semiconductor layer is formed on the surface of the buried layer away from the first semiconductor layer; The surface of the second semiconductor layer away from the first semiconductor layer is used as the first surface, and a second region is formed on a portion of the first surface; A third region is formed on a portion of the first surface, and the third region does not overlap with the second region; A first region is formed within the second semiconductor layer, the first region penetrating the buried layer; the orthographic projection of the first region onto the second surface lies at least within the orthographic projection of the third region onto the second surface; the third region is spaced from the first region in the thickness direction of the semiconductor body; the thickness direction is the direction from the first surface to the second surface.

[0018] Optionally, the second region includes a first sub-region and a second sub-region disposed along the thickness direction; Forming a second region on a portion of the first surface includes: A first sub-region is formed on a portion of the first surface, and a second sub-region is formed on the side of the first sub-region away from the first surface; the second sub-region is in contact with the first sub-region and the buried layer, respectively; in a first direction, the width of the second sub-region is less than the width of the first sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the second sub-region overlaps at least with the orthographic projection of the second region.

[0019] Optionally, the second region includes a first sub-region, a second sub-region, and a third sub-region disposed along the thickness direction; Forming a second region on a portion of the first surface includes: The first sub-region is formed on a portion of the first surface; The third sub-region is formed on the side of the first sub-region away from the first surface; the third sub-region is in contact with the buried layer; A second sub-region is formed between the first sub-region and the third sub-region; the second sub-region is in contact with both the first sub-region and the third sub-region; in a first direction, the width of the second sub-region is less than the width of the third sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the interval and the projection of the second region in the first direction overlap.

[0020] Optionally, the third region includes at least two sub-regions disposed along the thickness direction, wherein the at least two sub-regions include a fourth sub-region, a fifth sub-region, and a sixth sub-region; Forming a third region on a portion of the first surface includes: The fourth, fifth, and sixth sub-regions are formed by multiple injections on the first surface. The fourth sub-region is located on the first surface, and the fifth sub-region is located on the side closest to the second surface. The sixth sub-region is located between the fifth and fourth sub-regions. In the thickness direction, the widths of the fourth, sixth, and fifth sub-regions increase or decrease in a first direction. The orthographic projection of the fifth sub-region on the second surface at least covers the orthographic projection of the first region on the second surface. The first direction is the direction from the second region to the third region and is perpendicular to the thickness direction.

[0021] The semiconductor device provided in this embodiment includes a semiconductor body, which comprises a first region, a second region, and a buried layer. The buried layer is disposed between the first surface and the second surface, and the first region penetrates the buried layer. By providing the first region penetrating the buried layer as a current channel, a direct carrier injection path is provided to the source side, effectively reducing the JFET resistance. Furthermore, the second region forms direct contact with the buried layer, allowing the control electric field of the gate to act more directly on the entire channel region, enhancing the control capability of the current channel and improving the switching speed and reliability of the device. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 7 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figure 8 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figures 9-10 A schematic diagram of an intermediate process for fabricating a semiconductor device provided in an embodiment of this application; Figure 11 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figures 12-13A schematic diagram of an intermediate process for fabricating a semiconductor device provided in an embodiment of this application; Figure 14 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figures 15-16 A schematic diagram of an intermediate process for fabricating a semiconductor device provided in an embodiment of this application; Figure 17 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figure 18 This is a schematic diagram of the intermediate process structure for the fabrication of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. See also... Figure 1 The system includes a semiconductor body 110, a gate 120, a source 130, and a drain 140. The semiconductor body 110 includes a first surface and a second surface disposed opposite to each other. The semiconductor body 110 also includes a first region 111, a second region 112, and a buried layer 113. The buried layer 113 is disposed between the first surface and the second surface. The first region 111 is disposed between the first surface and the second surface and extends through the buried layer 113. The second region 112 is located on the first surface and at least partially contacts the buried layer 113. The first region 111 has a first conductivity type, and the buried layer 113 and the second region 112 have a second conductivity type. The gate 120 is located on a portion of the first surface and at least covers the second region 112, forming an ohmic contact with the second region 112. The source 130 is located on a portion of the first surface. The drain 140 is located on the second surface.

[0025] Specifically, in the embodiments of this application, the semiconductor devices include, but are not limited to, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), JFETs (Junction Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and HEMTs (High Electron Mobility Transistors). The semiconductor body 110 may include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor body 110 and gallium nitride semiconductor body 110. Exemplarily, the MOSFET includes an N-type MOSFET or a P-type MOSFET. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For regions with an N-type conductivity type, N-type doping can be used, and the dopant ions can be phosphorus (P) ions or nitrogen (N) ions. For regions with a P-type conductivity type, P-type doping can be used, and the dopant ions can be aluminum (Al) ions or boron (B) ions. The embodiments described below use an example where the first conductivity type is N-type and the second conductivity type is P-type.

[0026] For example, in the structure of the device, the semiconductor body 110 may include a substrate 114, a semiconductor layer 115, a buried layer 113, a first region 111, and a second region 112. The semiconductor layer 115 may be formed on one side of the substrate 114 by processes such as epitaxial growth. The surface of the semiconductor layer 115 away from the substrate 114 is defined as the first surface, and the surface of the substrate 114 away from the semiconductor layer 115 is defined as the second surface. The buried layer 113 is disposed within the semiconductor layer 115 between the first surface and the second surface. The first region 111 is also disposed within the semiconductor layer 115 and penetrates the buried layer 113 in the thickness direction Y, i.e., in the direction from the first surface to the second surface. This penetration can be understood as the first region 111 being in contact with both sides of the semiconductor layer 115 on both sides of the buried layer 113. This forms a continuous current path extending from the source 130 side to the drain 140 side.

[0027] The second region 112 can be formed on the first surface by an ion implantation process and extends into the buried layer 113 in the thickness direction Y, at least partially contacting the buried layer 113. In some embodiments, the second region 112 can be located on one or both sides of the first region 111 in the first direction X. When the second region 112 is provided on both sides of the first region 111, the two second regions 112 can be arranged symmetrically or asymmetrically with respect to the first region 111. Since the second region 112 can directly act on the buried layer 113 region, the control efficiency of the gate 120 on the carriers in the channel can be improved.

[0028] A source 130 and a gate 120 are disposed on a portion of the first surface of the semiconductor body 110, and a drain 140 is disposed on the second surface. In the first direction X, an insulating layer 150 is further included between the source 130 and the gate 120. The insulating layer 150 can be an inter-layer dielectric (ILD), which isolates the gate 120 and the source 130. The source 130 forms an ohmic contact with the semiconductor layer 115. The gate 120 forms an ohmic contact with the second region 112. For example, the source 130 and the gate 120 can be formed in the same layer by sputtering or other methods, and the material can be selected from titanium (Ti), nickel (Ni), silver (Ag), or other suitable conductive metals. The drain 140 can also be formed on the second surface by sputtering or other methods. Before forming the drain 140, the substrate 114 can be thinned to reduce parasitic resistance.

[0029] In this embodiment of the application, the working principle of the semiconductor device is as follows: When a forward bias is applied to the gate 120, the depletion region between the first region 111 and the buried layer 113 is compressed under the action of the electric field, widening the conductive channel. At this time, the first region 111, which penetrates the buried layer 113, forms a low-resistance path between the source 130 and the drain 140, and the device is turned on. Since the first region 111 can provide abundant majority carriers, it effectively assists the current to pass through the current path, thereby significantly reducing the JFET region resistance when the device is turned on and increasing the on-current density of the device. When a reverse bias is applied to the gate 120, the depletion region between the first region 111 and the buried layer 113 expands outward, the conductive channel formed by the first region 111 is gradually pinched off, the drain current 140 decreases until it is cut off, realizing the device's turn-off function.

[0030] The semiconductor device provided in this embodiment includes a semiconductor body 110, which includes a first region 111, a second region 112, and a buried layer 113. The buried layer 113 is disposed between a first surface and a second surface, and the first region 111 penetrates the buried layer 113. By providing the first region 111 penetrating the buried layer 113 as a current channel, a direct carrier injection path is provided to the source 130 side, effectively reducing the JFET resistance. Furthermore, the second region 112 forms direct contact with the buried layer 113, allowing the control electric field of the gate 120 to act more directly on the entire channel region, enhancing the control capability of the current channel and improving the switching speed and reliability of the device.

[0031] Figure 2 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 2The semiconductor body 110 also includes a third region 116 of a first conductivity type, the third region 116 being located on the first surface and not overlapping with the second region 112. The orthographic projection of the first region 111 on the second surface lies at least within the orthographic projection of the third region 116 on the second surface. In the thickness direction Y of the semiconductor body 110, the third region 116 and the first region 111 are spaced apart. The thickness direction Y is the direction from the first surface to the second surface.

[0032] The source electrode 130 is located on a portion of the first surface and at least covers the third region 116, forming an ohmic contact with the third region 116.

[0033] Specifically, the difference between this embodiment and the previous embodiment is that a third region 116 of a first conductivity type is formed on the first surface. The third region 116 is spaced from the first region 111, meaning that the third region 116 and the first region 111 do not contact each other within the semiconductor layer 115. The orthographic projection of the first region 111 on the second surface lies at least within the orthographic projection of the third region 116 on the second surface, meaning that the orthographic projection of the third region 116 on the second surface can completely cover the first region 111. The source 130 at least covers the third region 116, forming an ohmic contact with the third region 116.

[0034] When the device is turned on, current flows from the source 130, is injected through the third region 116, initially diverges within the semiconductor layer 115, then gradually converges and flows into the first region 111, finally flowing to the drain 140. Due to the gap between the third region 116 and the first region 111, the third region 116 provides a larger contact area. This increased contact area effectively reduces the contact resistance on the source 130 side, allowing the device to carry a larger current. The first region 111, serving as a current path on the buried layer 113, has a relatively small area design, enabling the control electric field of the gate 120 to more effectively control the depletion region of the first region 111. This enhances the gate 120's ability to pinch off and turn on current, improving the device's switching speed and turn-off reliability. Furthermore, the current converges from the large-area third region 116 to the first region 111, forming a carrier injection and convergence path, reducing the congestion effect when current flows within the semiconductor layer 115, thereby further reducing the overall conduction loss of the device.

[0035] Figure 3 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 3The second region 112 includes a first sub-region 1121 and a second sub-region 1122 disposed along the thickness direction Y. The first sub-region 1121 is located on the first surface, and the second sub-region 1122 is located on the side of the first sub-region 1121 away from the first surface. The second sub-region 1122 is in contact with the first sub-region 1121 and the buried layer 113.

[0036] In the first direction X, the width of the second sub-region 1122 is smaller than the width of the first sub-region 1121. The first direction X is the direction from the second region 112 to the third region 116, and is perpendicular to the thickness direction Y. The projection of the interval and the second region 112 in the first direction X overlaps.

[0037] Specifically, the difference between this embodiment and the above embodiments is that the second region 112 includes a first sub-region 1121 and a second sub-region 1122. In the first direction X, the widths of the first sub-region 1121 and the second sub-region 1122 are different. In this embodiment, the width of the second sub-region 1122 is smaller than the width of the first sub-region 1121, allowing the first sub-region 1121 to provide a larger surface area. This increases the contact area between the first sub-region 1121 and the gate 120, reducing contact resistance and enabling the gate 120 to inject control charge into the channel more efficiently, thus improving the device's response speed.

[0038] Positionally, the projections of the spacing and the second region 112 in the first direction X overlap. Therefore, when the width of the second region 112 is reduced, the width between adjacent second regions 112 in the first direction X can be correspondingly increased, which is equivalent to increasing the diffusion space of current in the first direction X within the semiconductor layer 115. After current is injected from the source 130, it can diffuse uniformly within a wider area of ​​the semiconductor layer 115, effectively mitigating the current congestion effect under high current density, thereby allowing the device to carry a larger operating current.

[0039] Figure 4 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 4 The second region 112 includes a first sub-region 1121, a second sub-region 1122, and a third sub-region 1123 disposed along the thickness direction Y. The first sub-region 1121 is located on the first surface, and the second sub-region 1122 contacts the first sub-region 1121 and the third sub-region 1123, respectively. The third sub-region 1123 contacts the buried layer 113.

[0040] In the first direction X, the width of the second sub-region 1122 is smaller than the width of the third sub-region 1123. The projections of the interval and the second region 112 in the first direction X overlap.

[0041] Specifically, the difference between this embodiment and the above embodiments is that the second region 112 includes a first sub-region 1121, a second sub-region 1122, and a third sub-region 1123. In the first direction X, the widths of the first sub-region 1121 and the second sub-region 1122 are different, and the widths of the second sub-region 1122 and the third sub-region 1123 are different. In this embodiment, the width of the second sub-region 1122 is smaller than the width of the first sub-region 1121, and the width of the second sub-region 1122 is smaller than the width of the third sub-region 1123, forming a dumbbell-shaped or hourglass-shaped structure that is wide at both ends and narrow in the middle. This allows the first sub-region 1121 located on the first surface to provide a larger surface area, thereby increasing the contact area between the first sub-region 1121 and the gate 120. This reduces the contact resistance between the first sub-region 1121 and the gate 120, enabling the gate 120 to inject control charge into the channel more efficiently, thus improving the device's response speed.

[0042] Meanwhile, the third sub-region 1123 can also have a large surface area, which can form a more sufficient contact with the buried layer 113, so that the control electric field of the gate 120 can act more directly on the entire channel region, which enhances the control capability of the current channel and is conducive to improving the switching speed and reliability of the device.

[0043] The spacing between the first region 111 and the third region 116 overlaps with the orthographic projection of the second region 112 in the first direction X. That is, the width of the second sub-region 1122 is narrowed, and the lateral spacing between adjacent second regions 112 in the first direction X is correspondingly increased. This effectively increases the diffusion space of current in the first direction X within the semiconductor layer 115. After current is injected from the source 130, it can diffuse uniformly within a wider area of ​​the semiconductor layer 115, effectively mitigating the current congestion effect under high current density, thereby allowing the device to carry a larger operating current.

[0044] See Figure 3 and Figure 4 Along the thickness direction Y, the width of the second sub-region 1122 in the first direction X is not uniform. That is, by adjusting the width variation trend of the second sub-region 1122 in the first direction X, the lateral spacing between adjacent second regions 112 in the first direction X can be adjusted accordingly, thereby realizing the control of the lateral diffusion space of current in the semiconductor layer 115.

[0045] Optionally, along the thickness direction Y, the width of the second sub-region 1122 gradually increases in the first direction X. In this structure, the lateral spacing between adjacent second regions 112 gradually decreases. Therefore, when the device is turned on, current starts from the source 130, is injected through the third region 116, and first diverges within the semiconductor layer 115, then gradually converges and flows into the first region 111, finally flowing to the drain 140. The gradually increasing width of the second sub-region 1122 in the first direction X gradually narrows the diffusion space between adjacent second regions 112. Through the diffusion width design of divergence followed by convergence, the current can be guided to smoothly transition within the semiconductor layer 115 and naturally converge to the first region 111, forming a carrier injection and convergence path. This alleviates the current congestion effect inside the semiconductor layer 115 under high current density, thereby further reducing the overall conduction loss of the device.

[0046] Figure 5 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 5 The third region 116 includes at least two sub-regions disposed along the thickness direction Y, wherein the at least two sub-regions include a fourth sub-region 1161 and a fifth sub-region 1162. The fourth sub-region 1161 is located on the first surface, and the fifth sub-region 1162 is located on the side closest to the second surface. The width of the fifth sub-region 1162 in the first direction X is greater than the width of the fourth sub-region 1161 in the first direction X.

[0047] Specifically, the fourth sub-region 1161 and the fifth sub-region 1162 are the two outermost regions of the third region 116 in the thickness direction Y. The fourth sub-region 1161 and the fifth sub-region 1162 form a stepped structure with gradually increasing width. The bent stepped interface that can be formed between the fourth sub-region 1161 and the fifth sub-region 1162 increases the contact area between the entire third region 116 and the surrounding semiconductor layer 115. This increased contact area allows current injected from the source 130 to diffuse more uniformly into the semiconductor layer 115, effectively reducing the ohmic contact resistance on the source 130 side, thereby allowing the device to carry a larger operating current.

[0048] As another alternative implementation method, Figure 6 For a schematic diagram of another semiconductor device provided in the embodiments of this application, see [link to schematic diagram]. Figure 6 The width of the fifth sub-region 1162 in the first direction X is smaller than the width of the fourth sub-region 1161 in the first direction X. The fourth sub-region 1161 and the fifth sub-region 1162 form a stepped structure with gradually decreasing width. Although the lateral dimension of the third region 116 changes in a similar trend... Figure 5The embodiment shown is the opposite, but a bent stepped interface is also formed between the fourth sub-region 1161 and the fifth sub-region 1162. Therefore, the contact area between the third region 116 and the semiconductor layer 115 can also be effectively increased, thereby reducing the contact resistance on the source 130 side and improving the device current transport capability.

[0049] See Figure 5 and Figure 6 At least two sub-regions further include at least one sixth sub-region 1163. The sixth sub-region is located between the fourth sub-region 1161 and the fifth sub-region 1162. In the thickness direction Y, the widths of the fourth sub-region 1161, the sixth sub-region 1163, and the fifth sub-region 1162 are arranged in an increasing or decreasing manner in the first direction X. For example, in one embodiment, starting from the fourth sub-region 1161 near the first surface, through one or more intermediate sixth sub-regions 1163, to the fifth sub-region 1162 closest to the second surface, the width of each sub-region in the first direction X increases sequentially, forming a multi-level stepped or approximately conical lateral expansion structure. In another embodiment, the width of each sub-region decreases sequentially, forming a multi-level stepped or approximately inverted conical lateral contraction structure. By introducing one or more intermediate sixth sub-regions 1163, the width of the third region 116 exhibits a continuous variation trend in the thickness direction Y, thereby providing a smoother and more continuous interface transition. This gradient width variation increases the contact area between the third region 116 and the semiconductor layer 115, which not only reduces the overall contact resistance on the source 130 side, but also avoids local electric field concentration caused by interface abrupt changes, thus improving the reliability of the device.

[0050] When the overall width of the third region 116 is set to increase, after the current is injected from the source 130, it can diffuse outward step by step along the thickness direction Y within the semiconductor layer 115, effectively alleviating lateral congestion under high-density current. When the overall width of the third region 116 is set to decrease, it can guide the current to gradually contract during its transmission towards the drain 140, forming a low-resistance, high-efficiency carrier transport path.

[0051] It should be noted that in the above embodiment, the orthographic projection of the fifth sub-region 1162 on the second surface at least covers the orthographic projection of the first region 111 on the second surface. That is, the extension range of the fifth sub-region 1162 in the first direction X is greater than the width of the first region 111 in the first direction X, so that the electric field lines can be evenly distributed in the first region 111, avoiding abnormal increase in local electric field intensity at the corner of the first region 111, and improving the withstand voltage capability and long-term reliability of the device.

[0052] This application provides a power module based on the above embodiments, including a substrate and a semiconductor device according to any embodiment of this application, wherein the substrate is used to support the semiconductor device. The power module provided by this application has the same beneficial effects as the semiconductor device according to any embodiment of this application.

[0053] This application provides a power conversion circuit based on the above embodiments. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, with the semiconductor device electrically connected to the circuit board. The power conversion circuit provided by this application has the same beneficial effects as the semiconductor device in any embodiment of this application.

[0054] Based on the above embodiments, this application provides a vehicle including a load and a power conversion circuit as described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0055] This application provides a method for fabricating a semiconductor device based on the above embodiments. Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application, combined with... Figure 1 See Figure 7 The preparation methods include: S110. A semiconductor body 110 is provided. The semiconductor body 110 includes a first surface and a second surface disposed opposite to each other. The semiconductor body 110 also includes a first region 111, a second region 112, and a buried layer 113. The buried layer 113 is disposed between the first surface and the second surface. The first region 111 is disposed between the first surface and the second surface and extends through the buried layer 113. The second region 112 is located on the first surface, and at least a portion of the second region 112 is in contact with the buried layer 113. The first region 111 is of a first conductivity type, and the buried layer 113 and the second region 112 are of a second conductivity type.

[0056] In this embodiment, the semiconductor device includes, but is not limited to, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), JFET (Junction Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and HEMT (High Electron Mobility Transistor). The semiconductor body 110 may include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor body 110 or gallium nitride semiconductor body 110. Exemplarily, the MOSFET includes an N-type MOSFET or a P-type MOSFET. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. Regions with N-type conductivity can be formed by N-type doping, where the dopant ions can be phosphorus (P) ions or nitrogen (N) ions. Regions with P-type conductivity can be formed by P-type doping, where the dopant ions can be aluminum (Al) ions or boron (B) ions. The following embodiments use an example where the first conductivity type is N-type and the second conductivity type is P-type.

[0057] Specifically, in terms of device structure, the semiconductor body 110 may include a substrate 114, a semiconductor layer 115, a buried layer 113, a first region 111, and a second region 112. The semiconductor layer 115 is formed on one side of the substrate 114 through processes such as epitaxial growth. The surface of the semiconductor layer 115 away from the substrate 114 is defined as the first surface, and the surface of the substrate 114 away from the semiconductor layer 115 is defined as the second surface. The buried layer 113 is disposed within the semiconductor layer 115 between the first and second surfaces. The first region 111 is also disposed within the semiconductor layer 115 and penetrates the buried layer 113 in the thickness direction Y, i.e., in the direction from the first surface to the second surface. This penetration can be understood as the first region 111 being in contact with the semiconductor layers 115 on both sides of the buried layer 113. This forms a continuous current path extending from the source 130 side to the drain 140 side.

[0058] The second region 112 can be formed on the first surface by an ion implantation process and extends into the buried layer 113 in the thickness direction Y, at least partially contacting the buried layer 113. In some embodiments, the second region 112 can be located on one or both sides of the first region 111 in the first direction X. When the second region 112 is provided on both sides of the first region 111, the two second regions 112 can be arranged symmetrically or asymmetrically with respect to the first region 111. Since the second region 112 can directly act on the buried layer 113 region, the control efficiency of the gate 120 on the carriers in the channel can be improved.

[0059] S120, a source 130 and a gate 120 are formed on a portion of the first surface, wherein the gate 120 at least covers the second region 112 and forms an ohmic contact with the second region 112.

[0060] Specifically, a source 130 and a gate 120 are disposed on a portion of the first surface of the semiconductor body 110, and a drain 140 is disposed on the second surface. In the first direction X, an insulating layer 150 is further included between the source 130 and the gate 120. The insulating layer 150 can be an interlayer dielectric (ILD), which isolates the gate 120 and the source 130. The source 130 forms an ohmic contact with the semiconductor layer 115. The gate 120 forms an ohmic contact with the second region 112. For example, the source 130 and the gate 120 can be formed in the same layer by means of sputtering, and the material can be selected from titanium (Ti), nickel (Ni), silver (Ag), or other suitable conductive metals.

[0061] S130, Drain 140 is formed on the second surface.

[0062] Specifically, the drain 140 can also be formed on the second surface by sputtering or other methods. Before forming the drain 140, the substrate 114 can be thinned to reduce parasitic resistance.

[0063] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figures 9-10 This is a schematic diagram of an intermediate process for fabricating a semiconductor device according to an embodiment of this application. (Refer to the diagram for further details.) Figures 8-10 The semiconductor body 110 also includes a third region 116 of a first conductivity type.

[0064] Preparation methods include: S210, providing substrate 114.

[0065] S220. A first semiconductor layer 1151 is formed on one side of the substrate 114. The first semiconductor layer 1151 can be formed on the surface of the substrate 114 by epitaxial growth. The first semiconductor layer 1151 can serve as a drift region or a buffer layer.

[0066] S230, a buried layer 113 is formed on the surface of the first semiconductor layer 1151. The buried layer 113 can be formed on the surface of the first semiconductor layer 1151 by ion implantation, selective epitaxial growth or diffusion process.

[0067] S240, A second semiconductor layer 1152 is formed on the surface of the buried layer 113 away from the first semiconductor layer 1151. The second semiconductor layer 1152 can be formed on the surface of the buried layer 113 by epitaxial growth.

[0068] S250, a second region 112 is formed on a portion of the surface of the second semiconductor layer 1152 away from the first semiconductor layer 1151 as the first surface.

[0069] Specifically, a first mask layer 210, such as a silicon dioxide hard mask, is deposited on the surface of the second semiconductor layer 1152, and a first opening 211 is formed in the first mask layer 210 to expose the implantation site of the second region 112. Subsequently, ion implantation is performed through the first opening 211 to form the second region 112. The second region 112 extends at least partially into the buried layer 113, forming a contact with the buried layer 113. The second region 112 is used to subsequently form an ohmic contact with the gate 120 and constitutes the control region of the conductive channel. Its structure is as follows... Figure 9 As shown.

[0070] S260, A third region 116 is formed on a portion of the first surface.

[0071] Specifically, after removing the first mask layer 210, a second mask layer 220, such as another silicon dioxide hard mask, is formed on the surface of the second semiconductor layer 1152. The second mask layer 220 has a second opening 221 to define the implantation location of the third region 116. Implantation parameters, such as energy, dose, and angle, are adjusted according to the required doping depth and concentration, and ion implantation is performed through the second opening 221 to form the third region 116. The third region 116 does not overlap with the second region 112.

[0072] S270, A first region 111 is formed within the second semiconductor layer 1152.

[0073] Specifically, a sidewall structure is formed on the inner wall of the retained second opening 221. The central area enclosed by the sidewall structure is the injection window of the first region 111. Injection is performed by adjusting the injection parameters according to the sidewall structure, forming the first region 111 within the second semiconductor layer 1152. The first region 111 penetrates the buried layer 113. The orthographic projection of the first region 111 on the second surface is at least within the orthographic projection of the third region 116 on the second surface. In the thickness direction Y of the semiconductor body 110, there is a gap between the third region 116 and the first region 111, thereby ensuring the current diffusion space of the third region 116. Its structure is as follows: Figure 10 As shown.

[0074] S280, a source 130 and a gate 120 are formed on a portion of the first surface, wherein the gate 120 at least covers the second region 112 and forms an ohmic contact with the second region 112.

[0075] S290, Drain 140 is formed on the second surface.

[0076] Figure 11 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figures 12-13 This is a schematic diagram of an intermediate process for fabricating a semiconductor device, provided in an embodiment of this application. Figure 3 See Figure 11 , Figure 12 and Figure 13 The second region 112 includes a first sub-region 1121 and a second sub-region 1122 disposed along the thickness direction Y.

[0077] Preparation methods include: S310, provides substrate 114.

[0078] S320. A first semiconductor layer 1151 is formed on one side of the substrate 114. The first semiconductor layer 1151 can be formed on the surface of the substrate 114 by epitaxial growth.

[0079] S330, a buried layer 113 is formed on the surface of the first semiconductor layer 1151. The buried layer 113 can be formed on the surface of the first semiconductor layer 1151 by ion implantation, selective epitaxial growth or diffusion process.

[0080] S340, A second semiconductor layer 1152 is formed on the surface of the buried layer 113 away from the first semiconductor layer 1151. The second semiconductor layer 1152 can be formed on the surface of the buried layer 113 by epitaxial growth.

[0081] S350, a first sub-region 1121 is formed on a portion of the first surface of the second semiconductor layer 1152 away from the first semiconductor layer 1151, and a second sub-region 1122 is formed on the side of the first sub-region 1121 away from the first surface.

[0082] Specifically, a first mask layer 210 is formed on the surface of the second semiconductor layer 1152. This first hard mask layer can be silicon dioxide. The first mask layer 210 has a first opening 211, which exposes the implantation location of the second region 112. Implantation is performed through the first opening 211 to form a first sub-region 1121. Its structure is as follows... Figure 12 As shown.

[0083] A sidewall structure 310 is formed within the first opening 211. Ion implantation is then performed again to form a second sub-region 1122 within the second semiconductor layer 1152. The second sub-region 1122 is in contact with the buried layer 113. The width of the second sub-region 1122 is smaller than the width of the first sub-region 1121. Its structure is as follows: Figure 13 As shown.

[0084] S360, A third region 116 is formed on a portion of the first surface.

[0085] Specifically, the first hard mask layer is removed, and a second mask layer is formed on the surface of the second semiconductor layer 1152. The second hard mask layer can be silicon dioxide. The second mask layer has a second opening that exposes the implantation location of the third region 116. Implantation is performed by adjusting the implantation parameters according to the second opening to form the third region 116, which does not overlap with the second region 112. The second sub-region 1122 overlaps at least with the orthographic projection of the second region 112.

[0086] S370, A first region 111 is formed within the second semiconductor layer 1152.

[0087] Specifically, a sidewall structure is formed within the second opening. The area enclosed by the sidewall structure is defined as the injection location of the first region 111. Injection parameters are adjusted according to the sidewall structure to form the first region 111. The first region 111 penetrates the buried layer 113. The orthographic projection of the first region 111 on the second surface lies at least within the orthographic projection of the third region 116 on the second surface. In the thickness direction Y of the semiconductor body 110, there is a gap between the third region 116 and the first region 111.

[0088] S380, a source 130 and a gate 120 are formed on a portion of the first surface, wherein the gate 120 at least covers the second region 112 and forms an ohmic contact with the second region 112.

[0089] S390, Drain 140 is formed on the second surface.

[0090] Figure 14 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figures 15-16 This is a schematic diagram of an intermediate process for fabricating a semiconductor device, provided in an embodiment of this application. Figure 4 See Figures 14-16 The second region 112 includes a first sub-region 1121, a second sub-region 1122 and a third sub-region 1123 arranged along the thickness direction Y.

[0091] Preparation methods include: S410 provides substrate 114.

[0092] S420, A first semiconductor layer 1151 is formed on one side of the substrate 114. The first semiconductor layer 1151 can be formed on the surface of the substrate 114 by epitaxial growth.

[0093] S430, a buried layer 113 is formed on the surface of the first semiconductor layer 1151. The buried layer 113 can be formed on the surface of the first semiconductor layer 1151 by ion implantation, selective epitaxial growth or diffusion process.

[0094] S440, A second semiconductor layer 1152 is formed on the surface of the buried layer 113 away from the first semiconductor layer 1151. The second semiconductor layer 1152 can be formed on the surface of the buried layer 113 by epitaxial growth.

[0095] S450, a first sub-region 1121 is formed on a portion of the second semiconductor layer 1152 away from the first semiconductor layer 1151 as a first surface.

[0096] Specifically, a first mask layer 210 is formed on the surface of the second semiconductor layer 1152. The first hard mask layer can be silicon dioxide. The first mask layer 210 has a first opening 211, which exposes the implantation location of the second region 112. Implantation is performed according to the first opening 211 to form a first sub-region 1121.

[0097] S460, a third sub-region 1123 is formed on the side of the first sub-region 1121 away from the first surface. The third sub-region 1123 is in contact with the buried layer 113.

[0098] Specifically, implantation is performed again through the first opening 211 to form a third sub-region 1123 within the second semiconductor layer 1152. Its structure is as follows: Figure 15 As shown.

[0099] S470, a second sub-region 1122 is formed between the first sub-region 1121 and the third sub-region 1123. The second sub-region 1122 is in contact with both the first sub-region 1121 and the third sub-region 1123. In the first direction X, the width of the second sub-region 1122 is smaller than the width of the third sub-region 1123.

[0100] Specifically, a sidewall structure 310 is formed within the first opening 211, and implantation is performed again to form a second sub-region 1122 within the second semiconductor layer 1152. The second sub-region 1122 is in contact with the buried layer 113. The width of the second sub-region 1122 is smaller than the width of the first sub-region 1121. Its structure is as follows: Figure 16 As shown.

[0101] S480, A third region 116 is formed on a portion of the first surface.

[0102] Specifically, the first hard mask layer is removed, and a second mask layer is formed on the surface of the second semiconductor layer 1152. The second hard mask layer can be silicon dioxide. The second mask layer has a second opening that exposes the implantation location of the third region 116. Implantation is performed by adjusting the implantation parameters according to the second opening to form the third region 116, which does not overlap with the second region 112. The second sub-region 1122 overlaps at least with the orthographic projection of the second region 112.

[0103] S490, a first region 111 is formed within the second semiconductor layer 1152.

[0104] Specifically, a sidewall structure is formed within the second opening. The area enclosed by the sidewall structure is defined as the injection location of the first region 111. Injection parameters are adjusted according to the sidewall structure to form the first region 111. The first region 111 penetrates the buried layer 113. The orthographic projection of the first region 111 on the second surface lies at least within the orthographic projection of the third region 116 on the second surface. In the thickness direction Y of the semiconductor body 110, there is a gap between the third region 116 and the first region 111.

[0105] S500, a source 130 and a gate 120 are formed on a portion of the first surface, wherein the gate 120 at least covers the second region 112 and forms an ohmic contact with the second region 112.

[0106] S510, Drain 140 is formed on the second surface.

[0107] Figure 17 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 18 This is a schematic diagram of an intermediate process for fabricating a semiconductor device, provided in an embodiment of this application. Figure 5 See Figure 17 and Figure 18 The third region 116 includes at least two sub-regions arranged along the thickness direction Y, wherein the at least two sub-regions include a fourth sub-region 1161, a fifth sub-region 1162 and a sixth sub-region 1163.

[0108] Preparation methods include: S610 provides substrate 114.

[0109] S620, A first semiconductor layer 1151 is formed on one side of the substrate 114. The first semiconductor layer 1151 can be formed on the surface of the substrate 114 by epitaxial growth.

[0110] S630, a buried layer 113 is formed on the surface of the first semiconductor layer 1151. The buried layer 113 can be formed on the surface of the first semiconductor layer 1151 by ion implantation, selective epitaxial growth or diffusion process.

[0111] S640, A second semiconductor layer 1152 is formed on the surface of the buried layer 113 away from the first semiconductor layer 1151. The second semiconductor layer 1152 can be formed on the surface of the buried layer 113 by epitaxial growth.

[0112] S650, a first sub-region 1121 is formed on a portion of the second semiconductor layer 1152 away from the first semiconductor layer 1151 as a first surface.

[0113] Specifically, a first mask layer is formed on the surface of the second semiconductor layer 1152. The first hard mask layer can be silicon dioxide. The first mask layer has a first opening that exposes the implantation location of the second region 112. Implantation is performed according to the first opening to form a first sub-region 1121.

[0114] S660, a third sub-region 1123 is formed on the side of the first sub-region 1121 away from the first surface. The third sub-region 1123 is in contact with the buried layer 113.

[0115] Specifically, injection is performed again according to the first opening to form a third sub-region 1123 within the second semiconductor layer 1152.

[0116] S670, a second sub-region 1122 is formed between the first sub-region 1121 and the third sub-region 1123. The second sub-region 1122 is in contact with both the first sub-region 1121 and the third sub-region 1123. In the first direction X, the width of the second sub-region 1122 is smaller than the width of the third sub-region 1123.

[0117] Specifically, a sidewall structure is formed within the first opening, and implantation is performed again to form a second sub-region 1122 within the second semiconductor layer 1152. The second sub-region 1122 is in contact with the buried layer 113. The width of the second sub-region 1122 is smaller than the width of the first sub-region 1121.

[0118] S680, a fourth sub-region 1161, a fifth sub-region 1162, and a sixth sub-region 1163 are formed by multiple injections on the first surface. The fourth sub-region 1161 is located on the first surface, and the fifth sub-region 1162 is located on the side closest to the second surface. The sixth sub-region 1163 is located between the fifth sub-region 1162 and the fourth sub-region 1161. In the thickness direction Y, the widths of the fourth sub-region 1161, the sixth sub-region 1163, and the fifth sub-region 1162 increase or decrease in the first direction X. The orthographic projection of the fifth sub-region 1162 on the second surface at least covers the orthographic projection of the first region 111 on the second surface.

[0119] Specifically, the first hard mask layer is removed, and a second mask layer 220 is formed on the surface of the second semiconductor layer 1152. The second mask layer 220 can be silicon dioxide. The second mask layer 220 has a second opening 221, which exposes the injection position of the second region 112. Multiple injections are performed according to the injection parameters adjusted based on the second opening 221 to form multi-level sub-regions. In this embodiment, a fourth sub-region 1161, a sixth sub-region 1163, and a fifth sub-region 1162 are formed. In the thickness direction Y, the widths of the fourth sub-region 1161, the sixth sub-region 1163, and the fifth sub-region 1162 increase or decrease in the first direction X. The third region 116 does not overlap with the second region 112. The second sub-region 1122 overlaps at least with the orthographic projection of the second region 112. Its structure is as follows... Figure 18 As shown.

[0120] S690, a first region 111 is formed within the second semiconductor layer 1152.

[0121] Specifically, a sidewall structure is formed within the second opening 221. The area enclosed by the sidewall structure is defined as the injection location of the first region 111. Injection parameters are adjusted according to the sidewall structure to form the first region 111. The first region 111 penetrates the buried layer 113. The orthographic projection of the first region 111 on the second surface lies at least within the orthographic projection of the third region 116 on the second surface. In the thickness direction Y of the semiconductor body 110, there is a gap between the third region 116 and the first region 111.

[0122] S700, a source 130 and a gate 120 are formed on a portion of the first surface, wherein the gate 120 at least covers the second region 112 and forms an ohmic contact with the second region 112.

[0123] S710, Drain 140 is formed on the second surface.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other, and the semiconductor body further includes a first region, a second region, and a buried layer; the buried layer is disposed between the first surface and the second surface; the first region is disposed between the first surface and the second surface and penetrates the buried layer; The second region is located on the first surface and at least partially contacts the buried layer; The first region is of a first conductivity type, and the buried layer and the second region are of a second conductivity type; A gate is located on a portion of the first surface and at least covers the second region, forming an ohmic contact with the second region; The source electrode is located on a portion of the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a third region of the first conductivity type, the third region being located on the first surface and not overlapping with the second region; the orthographic projection of the first region on the second surface is at least within the orthographic projection of the third region on the second surface; In the thickness direction of the semiconductor body, the third region is spaced from the first region; the thickness direction is the direction from the first surface to the second surface. The source electrode is located on a portion of the first surface and at least covers the third region, forming an ohmic contact with the third region.

3. The semiconductor device according to claim 2, characterized in that, The second region includes a first sub-region and a second sub-region disposed along the thickness direction; the first sub-region is located on the first surface, and the second sub-region is located on the side of the first sub-region away from the first surface; the second sub-region is in contact with the first sub-region and the buried layer, respectively. In a first direction, the width of the second sub-region is smaller than the width of the first sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the interval and the projection of the second region in the first direction overlap.

4. The semiconductor device according to claim 2, characterized in that, The second region includes a first sub-region, a second sub-region, and a third sub-region disposed along the thickness direction; the first sub-region is located on the first surface, the second sub-region is in contact with the first sub-region and the third sub-region respectively; the third sub-region is in contact with the buried layer; In the first direction, the width of the second sub-region is smaller than the width of the third sub-region; The first direction is the direction from the second region to the third region, and is perpendicular to the thickness direction; the interval and the projection of the second region in the first direction overlap.

5. The semiconductor device according to any one of claims 3-4, characterized in that, Along the thickness direction, the width of the second sub-region in the first direction is not uniform.

6. The semiconductor device according to claim 5, characterized in that, Along the thickness direction, the width of the second sub-region gradually increases in the first direction.

7. The semiconductor device according to claim 2, characterized in that, The third region includes at least two sub-regions disposed along the thickness direction, wherein the at least two sub-regions include a fourth sub-region and a fifth sub-region; the fourth sub-region is located on the first surface, and the fifth sub-region is located on the side closest to the second surface; The width of the fifth sub-region in the first direction is greater than the width of the fourth sub-region in the first direction; or, the width of the fifth sub-region in the first direction is less than the width of the fourth sub-region in the first direction; the first direction is the direction from the second region to the third region, and is perpendicular to the thickness direction.

8. The semiconductor device according to claim 7, characterized in that, The at least two sub-regions further include at least one sixth sub-region; the sixth sub-region is located between the fourth sub-region and the fifth sub-region; In the thickness direction, the widths of the fourth sub-region, the sixth sub-region, and the fifth sub-region are arranged in an increasing or decreasing manner in the first direction.

9. The semiconductor device according to any one of claims 7-8, characterized in that, The orthographic projection of the fifth sub-region onto the second surface at least covers the orthographic projection of the first region onto the second surface.

10. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-9, wherein the substrate is used to support the semiconductor device.

11. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-9, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 11, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

13. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a first region, a second region and a buried layer; the buried layer is disposed between the first surface and the second surface; the first region is disposed between the first surface and the second surface and penetrates the buried layer; The second region is located on the first surface and at least partially contacts the buried layer; The first region is of a first conductivity type, and the buried layer and the second region are of a second conductivity type; A source and a gate are formed on the first surface; wherein the gate at least covers the second region and forms an ohmic contact with the second region; A drain electrode is formed on the second surface.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The semiconductor body also includes a third region of the first conductivity type; Provide semiconductor bodies, including: Provide substrate; A first semiconductor layer is formed on one side of the substrate; The buried layer is formed on the surface of the first semiconductor layer; A second semiconductor layer is formed on the surface of the buried layer away from the first semiconductor layer; The surface of the second semiconductor layer away from the first semiconductor layer is used as the first surface, and a second region is formed on a portion of the first surface; A third region is formed on a portion of the first surface, and the third region does not overlap with the second region; A first region is formed within the second semiconductor layer, the first region penetrating the buried layer; the orthographic projection of the first region onto the second surface lies at least within the orthographic projection of the third region onto the second surface; the third region is spaced from the first region in the thickness direction of the semiconductor body; the thickness direction is the direction from the first surface to the second surface.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The second region includes a first sub-region and a second sub-region disposed along the thickness direction; Forming a second region on a portion of the first surface includes: A first sub-region is formed on a portion of the first surface, and a second sub-region is formed on the side of the first sub-region away from the first surface; the second sub-region is in contact with the first sub-region and the buried layer, respectively; In a first direction, the width of the second sub-region is smaller than the width of the first sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the second sub-region overlaps at least with the orthographic projection of the interval onto the second region.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that, The second region includes a first sub-region, a second sub-region, and a third sub-region disposed along the thickness direction; Forming a second region on a portion of the first surface includes: The first sub-region is formed on a portion of the first surface; The third sub-region is formed on the side of the first sub-region away from the first surface; the third sub-region is in contact with the buried layer; A second sub-region is formed between the first sub-region and the third sub-region; the second sub-region is in contact with both the first sub-region and the third sub-region; in a first direction, the width of the second sub-region is less than the width of the third sub-region; the first direction is the direction from the second region to the third region and is perpendicular to the thickness direction; the interval and the projection of the second region in the first direction overlap.

17. The method for fabricating a semiconductor device according to claim 14, characterized in that, The third region includes at least two sub-regions disposed along the thickness direction, wherein the at least two sub-regions include a fourth sub-region, a fifth sub-region, and a sixth sub-region; Forming a third region on a portion of the first surface includes: The fourth, fifth, and sixth sub-regions are formed by multiple injections on the first surface. The fourth sub-region is located on the first surface, and the fifth sub-region is located on the side closest to the second surface. The sixth sub-region is located between the fifth and fourth sub-regions. In the thickness direction, the widths of the fourth, sixth, and fifth sub-regions increase or decrease in a first direction. The orthographic projection of the fifth sub-region on the second surface at least covers the orthographic projection of the first region on the second surface. The first direction is the direction from the second region to the third region and is perpendicular to the thickness direction.

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