Semiconductor power device with magnetoelectric synergistic vertical type electric field regulation and preparation method thereof
CN122995217APending Publication Date: 2026-10-27SHENZHEN DIANMO SEMICONDUCTOR TECHNOLOGY CO LTD
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Patent Information
- Application Number
- CN202611171783.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-03
- Publication Date
- 2026-10-27
AI Technical Summary
Technical Problem
本发明摒弃传统PN结、栅极沟道调控机制,解决现有器件米勒效应、少子存储、反向恢复损耗大、高低频工况适配性差的问题;同时解决现有磁控器件工艺复杂、量产成本高、集成难度大、低频性能短板的缺陷,实现单芯片整流、功率开关双重功能,兼具高速开关、低导通电阻、高关断电阻、极低静态功耗的特性,且全程兼容标准CMOS平面工艺,适配多场景产业化应用
Benefits of technology
1、本发明功率器件物理机制革新,损耗降低:本发明摒弃传统PN结、栅极沟道调控机制,依托磁电协同环形载流子回路自主构建可控“高阻墙”,从根源上消除少子存储效应、米勒效应、反向恢复损耗,无开关拖尾、无驱动寄生损耗。
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Figure CN122995217A_ABST
Abstract
The application discloses a magnetoelectric cooperative vertical type electric field regulated semiconductor power device and a preparation method thereof. + low-resistance substrate region, N ‑ transition region, N ‑ high-resistance region, and a Schottky junction formed by arranging a Schottky metal contact in the center of the high-resistance region, wherein a permanent magnet is arranged in the width direction of the device to form a constant magnetic field orthogonal to the main current, and a ring-shaped carrier loop is constructed by relying on the difference in doping concentration, the Schottky junction and the orthogonal magnetic field, so that the rectification and power switching dual working modes can be adaptively realized. In the power switching mode, the insulating layer and the metal control plate are symmetrically arranged on the upper and lower sides of the device to form a vertical electric field driving structure, and the conduction and turn-off of the device are regulated by the vertical electric field. The application discloses a preparation method of the device, which discards the traditional PN junction and gate channel regulation mechanism, eliminates inherent defects such as the Miller effect, minority carrier storage and reverse recovery loss, and is prepared by using a standard CMOS planar epitaxial process, and has the characteristics of high-speed switching, low conduction resistance and high turn-off resistance.
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