Semiconductor structure and method of manufacturing the same

Abstract

The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof, the preparation method comprising: depositing a semiconductor sacrificial layer on the surface of a semiconductor substrate, the formation energy of vacancies in the semiconductor sacrificial layer being lower than that in the semiconductor substrate; pre-amorphization implantation is performed on the semiconductor substrate to form an amorphous region in the semiconductor substrate; first annealing is performed on the semiconductor substrate; and the semiconductor sacrificial layer is removed. In the first annealing process, part of the vacancies in the amorphous region migrate from the semiconductor substrate to the semiconductor sacrificial layer with lower formation energy, and the vacancies migrated into the semiconductor sacrificial layer are separated from the semiconductor substrate with the removal of the semiconductor sacrificial layer, thereby reducing the total amount of vacancies in the semiconductor substrate, and further reducing the risk of vacancy aggregation to form crystal structure defects such as cavities and dislocations, and improving the performance and yield of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, the feature size of devices is becoming smaller and smaller. Therefore, the fabrication process typically requires the formation of ultra-shallow junctions (USJs). However, if ion implantation and annealing are performed directly on the semiconductor substrate to form an USJ, the implanted impurity ions diffuse during annealing, leading to a deeper junction and increasing the likelihood of short-channel effects (SCEs). To suppress short-channel effects, pre-amorphization implantation is usually performed on the semiconductor substrate before forming the USJ to transform the shallow layer of the semiconductor substrate into an amorphous region.

[0003] However, pre-amorphization implantation can damage the semiconductor substrate, resulting in a large number of vacancies in the amorphous region. These vacancies may subsequently aggregate to form crystal structure defects such as voids and dislocations, leading to localized collapse of the semiconductor substrate (e.g., Figure 1 Permanent physical damage (as shown in the box) can adversely affect the performance and yield of devices. Summary of the Invention

[0004] This invention provides a semiconductor structure and its fabrication method to reduce the risk of crystal structure defects in the semiconductor substrate after pre-amorphization implantation.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor structure, comprising: A semiconductor sacrificial layer is deposited on the surface of a semiconductor substrate, wherein the formation energy of vacancies in the semiconductor sacrificial layer is lower than that of vacancies in the semiconductor substrate; The semiconductor substrate is pre-amorphized by implantation to form an amorphous region in the semiconductor substrate; After depositing the semiconductor sacrificial layer and performing the pre-amorphization implantation, the semiconductor substrate undergoes a first annealing. After the first annealing, the semiconductor sacrificial layer is removed.

[0006] In some alternative implementations, the thickness of the semiconductor sacrificial layer is 25nm-150nm.

[0007] In some alternative implementations, the thickness of the amorphous region is 90 nm to 200 nm.

[0008] In some alternative embodiments, the pre-amorphization implanted ions include germanium ions.

[0009] In some alternative embodiments, the semiconductor substrate includes one of a single-crystal silicon wafer and silicon-on-insulator, the semiconductor sacrificial layer is made of germanium silicon, the semiconductor sacrificial layer is removed by a wet etching process, and the etching solution contains hydrofluoric acid, hydrogen peroxide and acetic acid.

[0010] In some alternative implementations, during the first annealing process, a solid-phase epitaxial growth process is performed on the semiconductor substrate.

[0011] In some optional embodiments, the solid-phase epitaxial regeneration process is carried out at a temperature of 500°C-650°C for a time of 10 min-60 min.

[0012] In some optional embodiments, the first annealing process further includes: after performing the solid-phase epitaxial regeneration process, performing laser spike annealing or flash lamp annealing on the semiconductor substrate, wherein the temperature of the laser spike annealing or the flash lamp annealing is higher than the temperature of the solid-phase epitaxial regeneration process.

[0013] In some optional embodiments, the laser spike annealing temperature is 700℃-900℃, the flash lamp annealing temperature is 650-850℃, and the pulse width of the laser spike annealing or the flash lamp annealing is 100μs-800μs.

[0014] In some optional embodiments, the fabrication method further includes: performing a first ion implantation on the semiconductor substrate before the first annealing to form a vacancy-fixing buried layer, the vacancy-fixing buried layer being located below the amorphous region.

[0015] In some alternative embodiments, the ions implanted by the first ion implantation include carbon ions.

[0016] In some alternative embodiments, the thickness of the vacancy fixing layer is 150nm-350nm.

[0017] In some alternative embodiments, the spacing between the vacancy-fixing buried layer and the amorphous region is 0-30 nm.

[0018] In some optional embodiments, the energy of the first ion implantation is 150 keV-250 keV, and the dose of the first ion implantation is 1 × e15 ions / cm². 2 -9×e15 ions / cm 2 .

[0019] In some optional embodiments, the preparation method further includes: Prior to depositing the semiconductor sacrificial layer and performing the pre-amorphization implantation, a gate dielectric layer and a gate layer covering the gate dielectric layer are formed on a local surface on one side of the semiconductor substrate; the amorphous region and the semiconductor sacrificial layer are both formed on both sides of the gate layer; After removing the semiconductor sacrificial layer, a lightly doped source region and a lightly doped drain region are formed in the amorphous region, the lightly doped source region and the lightly doped drain region being located on both sides of the gate layer, respectively; sidewalls are formed on the sidewalls of the gate dielectric layer and the gate layer; a heavily doped source region and a heavily doped drain region are formed in the semiconductor substrate, the heavily doped source region and the heavily doped drain region being located on both sides of the gate layer covering the sidewalls, respectively; and a second annealing is performed on the semiconductor substrate.

[0020] In a second aspect, the present invention provides a semiconductor structure prepared by the preparation method described in the first aspect.

[0021] As described above, the present invention provides a semiconductor structure and its fabrication method. By depositing a semiconductor sacrificial layer on the surface of a semiconductor substrate, and the formation energy of vacancies in the semiconductor sacrificial layer is lower than that of vacancies in the semiconductor substrate, some vacancies in the amorphous region migrate from the semiconductor substrate to the semiconductor sacrificial layer with a lower formation energy during the first annealing process. The vacancies that migrate to the semiconductor sacrificial layer are removed from the semiconductor substrate as the semiconductor sacrificial layer is removed, thereby reducing the total amount of vacancies in the semiconductor substrate. This reduces the risk of vacancies agglomerating and forming crystal structure defects such as voids and dislocations, and improves the performance and yield of the device. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram illustrating the formation of localized collapse in a semiconductor substrate; Figure 2 This is a process flow diagram of the method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of forming an amorphous region and a vacancy-fixing buried layer in a semiconductor substrate, and forming a semiconductor sacrificial layer on the surface of the semiconductor substrate, according to an embodiment of the present invention. Figure 4 This is a schematic diagram of vacancy migration in the amorphous region during the first annealing process according to an embodiment of the present invention; Figure 5This is a schematic diagram of the structure after removing the semiconductor sacrificial layer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a structure in which an amorphous region, a vacancy-fixing buried layer, and a semiconductor sacrificial layer are formed on the side of the gate layer according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure of removing the semiconductor sacrificial layer on the side of the gate layer according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a lightly doped source region and a lightly doped drain region formed in a semiconductor substrate according to an embodiment of the present invention. Figure 9 This is a schematic diagram of a structure in which sidewalls are formed on the sidewalls of the gate layer and the gate dielectric layer according to an embodiment of the present invention; Figure 10 This is a schematic diagram of a heavily doped source region and a heavily doped drain region formed in a semiconductor substrate according to an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures: 100 - Semiconductor substrate; 101 - Semiconductor sacrificial layer; 110 - Amorphous region; 111 - Vacancy; 120 - Vacancy-fixing buried layer; 200 - Gate dielectric layer; 300 - Gate layer; 401 - Lightly doped source region; 402 - Lightly doped drain region; 500 - Sidewall; 601 - Heavily doped source region; 602 - Heavily doped drain region. Detailed Implementation

[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0027] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0028] Firstly, reference Figure 2 This invention provides a method for preparing a semiconductor structure, comprising: Step S1, Reference Figure 3 A semiconductor sacrificial layer 101 is deposited on the surface of a semiconductor substrate 100, wherein the formation energy of a vacancy in the semiconductor sacrificial layer 101 is lower than the formation energy of a vacancy in the semiconductor substrate 100. Step S2, continue to refer to Figure 3 The semiconductor substrate 100 is pre-amorphized by implantation to form an amorphous region 110 in the semiconductor substrate 100. Step S3, Reference Figure 4 After depositing the semiconductor sacrificial layer 101 and performing the pre-amorphization implantation, the semiconductor substrate 100 is subjected to a first annealing. Step S4, Reference Figure 5 After the first annealing, the semiconductor sacrificial layer 101 is removed.

[0029] It should be noted that there is no strict order restriction on the deposition of the semiconductor sacrificial layer 101 and the pre-amorphization implantation. In some optional embodiments, the semiconductor sacrificial layer 101 can be deposited on the surface of the semiconductor substrate 100 first, and then the semiconductor substrate 100 can be pre-amorphized implanted; in other optional embodiments, the semiconductor substrate 100 can be pre-amorphized implanted first, and then the semiconductor sacrificial layer 101 can be deposited on the surface of the semiconductor substrate 100. This execution order can avoid the interference of the semiconductor sacrificial layer 101 with the pre-amorphization implantation, which is beneficial to controlling the formation area and formation depth of the amorphous region 110, and avoids the generation of a small number of vacancies in the semiconductor sacrificial layer 101 during the pre-amorphization implantation process, which is beneficial to ensure that the semiconductor sacrificial layer 101 has sufficient vacancy capacity.

[0030] The following is combined with Figures 3-10 The fabrication methods for semiconductor structures are described in detail.

[0031] Step S1, Reference Figure 3 A semiconductor sacrificial layer 101 is deposited on the surface of a semiconductor substrate 100, wherein the formation energy of a vacancy in the semiconductor sacrificial layer 101 is lower than the formation energy of a vacancy in the semiconductor substrate 100.

[0032] Specifically, the semiconductor substrate 100 is a single-crystal substrate, or the semiconductor substrate 100 has a single-crystal semiconductor material layer on one side, and a semiconductor sacrificial layer 101 is deposited on the surface of the single-crystal semiconductor material layer. The semiconductor substrate 100 includes, but is not limited to, a single-crystal silicon wafer and silicon-on-insulator (SOI).

[0033] The semiconductor sacrificial layer 101 can be formed using chemical vapor deposition, physical vapor deposition, molecular beam epitaxy, or atomic layer deposition.

[0034] The materials of the semiconductor sacrificial layer 101 include, but are not limited to, germanium and silicon.

[0035] The thickness of the semiconductor sacrificial layer 101 can be 25nm-150nm, such as 50nm, 75nm, 100nm, 125nm, etc. The thickness of the semiconductor sacrificial layer 101 directly affects its capacity to accommodate vacancies, thereby affecting the amount of residual vacancies in the semiconductor substrate 100. If the thickness of the semiconductor sacrificial layer 101 is too small, the capacity to accommodate vacancies will be too small, and the amount of residual vacancies in the semiconductor substrate 100 cannot be effectively reduced. The total number of vacancies migrating from the semiconductor substrate 100 to the semiconductor sacrificial layer 101 during the first annealing process is limited. Therefore, the thickness of the semiconductor sacrificial layer 101 does not need to be too thick. Moreover, if the thickness of the semiconductor sacrificial layer 101 is too large, the workload of subsequently removing the semiconductor sacrificial layer 101 will be too large, thereby affecting the overall fabrication efficiency of the semiconductor structure. By limiting the thickness of the semiconductor sacrificial layer 101 to the above range, the workload of subsequently removing the semiconductor sacrificial layer 101 can be limited while ensuring that the semiconductor sacrificial layer 101 has sufficient capacity to accommodate vacancies, thereby effectively reducing the amount of residual vacancies in the semiconductor substrate 100.

[0036] Step S2, continue to refer to Figure 3 The semiconductor substrate 100 is pre-amorphized by implantation to form an amorphous region 110 in the semiconductor substrate 100.

[0037] Specifically, the amorphous region 110 is located in the shallow layer of the semiconductor substrate 100 and exposed on the surface of the semiconductor substrate 100. The amorphous region 110 and the semiconductor sacrificial layer 101 are located on the same side of the semiconductor substrate 100, and the semiconductor sacrificial layer 101 covers at least a portion of the amorphous region 110. The semiconductor sacrificial layer 101 can extend to the surface of the semiconductor substrate 100 beyond the amorphous region 110. Preferably, the semiconductor sacrificial layer 101 covers the entire area of ​​the amorphous region 110 to promote the migration of vacancies 111 in the amorphous region 110 to the semiconductor sacrificial layer 101 during the first annealing process, which helps to reduce the residual amount of vacancies in the semiconductor substrate 100.

[0038] In some alternative embodiments, the ions implanted during pre-amorphization include, but are not limited to, germanium ions.

[0039] In some optional embodiments, the thickness of the amorphous region 110 can be 90nm-200nm, such as 100nm, 120nm, 140nm, 160nm, 180nm, etc. The ultra-shallow junction is formed in the amorphous region 110, and the thickness of the amorphous region 110 directly affects the depth of the ultra-shallow junction.

[0040] In some optional embodiments, the pre-amorphization implantation energy can be 25keV-200keV, such as 50keV, 75keV, 100keV, 125keV, 150keV, 175keV, etc., and the pre-amorphization implantation energy affects the thickness of the amorphous region 110. Specifically, if the semiconductor sacrificial layer 101 is deposited after pre-amorphization implantation, then a lower energy of 25keV-120keV can be used for pre-amorphization implantation; if pre-amorphization implantation is performed after the deposition of the semiconductor sacrificial layer 101, the presence of the semiconductor sacrificial layer 101 will hinder the pre-amorphization implantation, so it is necessary to appropriately increase the pre-amorphization implantation energy to a higher energy of 120keV-200keV.

[0041] In some alternative embodiments, the dose of the pre-amorphization implantation can be 5e13 ions / cm². 2 -1e16ions / cm 2 For example, 7.5e13ions / cm 2 1e14ions / cm 2 5e14ions / cm 2 1e15ions / cm 2 5e15ions / cm 2 7.5e15ions / cm 2 The dosage of pre-amorphization implantation affects the degree of amorphization and the total amount of vacancy generation in the amorphous region 110.

[0042] Step S3: After depositing the semiconductor sacrificial layer 101 and performing the pre-amorphization implantation, the semiconductor substrate 100 is subjected to a first annealing.

[0043] For details, please refer to Figure 4 The first annealing is used to activate the impurity ions implanted by the pre-amorphization and to cause some of the vacancies 111 in the amorphous region 110 to migrate into the semiconductor sacrificial layer 101.

[0044] In some alternative embodiments, during the first annealing process, a solid-state epitaxial regeneration (SPER) process is performed on the semiconductor substrate 100. During SPER, a single-crystal material below the amorphous region 110 in the semiconductor substrate 100 is used as a seed crystal, and the amorphous region 110 recrystallizes from bottom to top to restore a portion or even all of its thickness to a crystalline state. (Refer to...) Figure 4 The directionality of the recrystallization process drives the vacancies 111 in the amorphous region 110 to migrate upwards, causing most of the vacancies 111 to migrate to the semiconductor sacrificial layer 101, thereby further reducing the residual amount of vacancies in the semiconductor substrate 100, and further reducing the risk of vacancies agglomerating to form crystal structure defects such as voids and dislocations, thereby further improving the performance and yield of the device.

[0045] The solid-phase epitaxial regeneration process can be carried out at temperatures ranging from 500℃ to 650℃, such as 525℃, 550℃, 575℃, 600℃, and 625℃, and for times ranging from 10min to 60min, such as 15min, 30min, 45min, and 55min. The solid-phase epitaxial regeneration process can be performed in a low-temperature annealing furnace or a low-temperature rapid heat treatment furnace. In a low-temperature annealing furnace, the processing temperature can be 500℃-650℃, and in a low-temperature rapid heat treatment furnace, the processing temperature can be 500℃-575℃.

[0046] In some optional embodiments, the first annealing process may further include: after performing the solid-phase epitaxial regeneration process, performing laser-spike annealing or flash annealing on the semiconductor substrate 100, wherein the temperature of the laser-spike annealing or flash annealing is higher than the temperature of the solid-phase epitaxial regeneration process. Both laser-spike annealing and flash annealing are instantaneous high-temperature annealing methods. Performing laser-spike annealing or flash annealing after the solid-phase epitaxial regeneration process, its high-temperature characteristics can promote the activation effect of the implanted impurity ions, and its instantaneous characteristics can reduce the risk of lateral diffusion of residual vacancies in the semiconductor substrate 100 during the annealing process, thereby reducing the impact on the channel length.

[0047] The temperature for laser peak annealing can be 700℃-900℃, the temperature for flash lamp annealing can be 650-850℃, and the pulse width for laser peak annealing or flash lamp annealing can be 100μs-800μs, which corresponds to the annealing time of laser peak annealing or flash lamp annealing.

[0048] Step S4, Reference Figure 5 After the first annealing, the semiconductor sacrificial layer 101 is removed.

[0049] Specifically, the semiconductor sacrificial layer 101 can be removed using a wet etching process. For example, the semiconductor substrate 100 is a single-crystal silicon wafer or silicon-on-insulator, and the semiconductor sacrificial layer 101 is a germanium-silicon layer. The etching solution may contain hydrofluoric acid, hydrogen peroxide, and acetic acid. Hydrogen peroxide and acetic acid react to generate peracetic acid, a strong oxidizing agent. Peracetic acid oxidizes the germanium-silicon layer much faster than it oxidizes single-crystal silicon. Peracetic acid preferentially oxidizes the germanium-silicon layer to form germanium-silicon oxide, which is then dissolved by hydrofluoric acid. This allows for the complete removal of the semiconductor sacrificial layer 101 with minimal or no damage to the semiconductor substrate 100. If the hydrogen peroxide and acetic acid in the etching solution are replaced with other oxidizing agents, and these other oxidizing agents have limited differences in oxidation rates between the germanium-silicon layer and single-crystal silicon, although the semiconductor sacrificial layer 101 can still be completely removed, it may damage the semiconductor substrate 100, affecting the device yield and performance.

[0050] Specifically, the etching solution can be prepared in the following ratio: hydrofluoric acid aqueous solution (49wt%), hydrogen peroxide (30wt%) and glacial acetic acid in a volume ratio of 1:(2-3):(4-6). This etching solution can achieve a high selectivity ratio of germanium silicon to silicon (the selectivity ratio can reach (20~500):1).

[0051] In some alternative implementations, refer to Figure 3 The preparation method may further include: performing a first ion implantation on the semiconductor substrate 100 before performing the first annealing to form a vacancy-fixing buried layer 120, the vacancy-fixing buried layer 120 being located below the amorphous region 110.

[0052] During the first annealing process, vacancies 111 in the amorphous region 110 migrate. Some vacancies 111 migrate upwards to the semiconductor sacrificial layer 101, while others migrate downwards to the vacancy-fixing buried layer 120. The vacancy-fixing buried layer 120 can form a stable structure with the vacancies 111, further reducing the risk of vacancy agglomeration forming crystal structure defects such as voids and dislocations, thereby further improving the device performance and yield. Preferably, [further details to be added]. Figure 4In conjunction with the solid-phase epitaxial growth process, a vacancy-fixed buried layer 120 is formed, in which most of the vacancies 111 migrate to the semiconductor sacrificial layer 101, and a small portion of the vacancies 111 migrate downwards to the vacancy-fixed buried layer 120, thereby effectively reducing the risk of vacancy agglomeration forming crystal structure defects such as voids and dislocations.

[0053] It should be noted that if the vacancy-fixing buried layer 120 overlaps or partially overlaps with the amorphous region 110, the vacancy-fixing buried layer 120 will affect the outward migration ability of vacancy in the amorphous region 110 during the first annealing process due to the vacancy-fixing buried layer 120 fixing the vacancy, thereby limiting the amount of vacancy that migrates to the semiconductor sacrificial layer 101 and limiting the vacancy removal effect of the semiconductor sacrificial layer 101.

[0054] The first annealing is also used to activate the impurity ions implanted by the first ion implantation.

[0055] It should be noted that there is no strict order restriction on the formation of the vacancy-fixing buried layer 120, the deposition of the semiconductor sacrificial layer 101, and the pre-amorphization implantation. In some optional embodiments, the vacancy-fixing buried layer 120 can be formed first, followed by the deposition of the semiconductor sacrificial layer 101 and the pre-amorphization implantation; in other optional embodiments, the semiconductor sacrificial layer 101 can be deposited first and the pre-amorphization implantation can be performed, followed by the formation of the vacancy-fixing buried layer 120; in still other optional embodiments, the formation of the vacancy-fixing buried layer 120 can be an intermediate step between the deposition of the semiconductor sacrificial layer 101 and the pre-amorphization implantation, and the order of the deposition of the semiconductor sacrificial layer 101 and the pre-amorphization implantation is not limited.

[0056] Preferably, the vacancy-fixing buried layer 120 is formed before the pre-amorphization implantation. This execution sequence can avoid the interference of the amorphous region 110 on the formation step of the vacancy-fixing buried layer 120, which is beneficial to control the formation area and formation depth of the vacancy-fixing buried layer 120, and makes it easy for the vacancy-fixing buried layer 120 to be formed below the amorphous region 110 and not to overlap with the amorphous region 110.

[0057] Preferably, the vacancy fixing buried layer 120 is formed before the semiconductor sacrificial layer 101 is deposited. This execution sequence can avoid the interference of the semiconductor sacrificial layer 101 on the vacancy fixing buried layer 120 formation step, and is beneficial to control the formation area and formation depth of the vacancy fixing buried layer 120.

[0058] In some alternative embodiments, the ions implanted by the first ion implantation include, but are not limited to, carbon ions.

[0059] In some optional embodiments, the thickness of the vacancy-fixing buried layer 120 can be 150nm-350nm, such as 175nm, 200nm, 225nm, 250nm, 275nm, 300nm, 325nm, etc. The thickness of the vacancy-fixing buried layer 120 affects its ability to fix vacancies. By limiting the thickness of the vacancy-fixing buried layer 120 to the above range, the vacancy-fixing buried layer 120 can have sufficient vacancy-fixing ability, thereby fully fixing the vacancies migrating downward from the amorphous region 110, reducing the number of unfixed vacancies, and further reducing the risk of vacancy agglomeration forming crystal structure defects such as voids and dislocations.

[0060] In some optional embodiments, the spacing between the vacancy-fixing buried layer 120 and the amorphous region 110 can be 0-30 nm. The spacing between the vacancy-fixing buried layer 120 and the amorphous region 110 affects the difficulty of vacancy migration from the amorphous region 110 to the vacancy-fixing buried layer 120. By limiting the spacing within the aforementioned range, the difficulty of vacancy migration from the amorphous region 110 to the vacancy-fixing buried layer 120 can be reduced, thereby reducing the number of unfixed vacancies and further reducing the risk of vacancy aggregation forming crystal structure defects such as voids and dislocations. The spacing between the vacancy-fixing buried layer 120 and the amorphous region 110 is preferably 10 nm-20 nm.

[0061] In some optional embodiments, the energy of the first ion implantation can be 150 keV-250 keV, such as 175 keV, 200 keV, 225 keV, etc., and the energy of the first ion implantation affects the thickness and depth of the vacancy-fixing buried layer 120; the dose of the first ion implantation can be 1×e15 ions / cm 2 -9×e15 ions / cm 2 For example, 1.5 × e15 ions / cm 2 2×e15 ions / cm 2 3×e15 ions / cm 2 4×e15 ions / cm 2 5×e15 ions / cm 2 6×e15 ions / cm 2 7×e15 ions / cm 2 8×e15 ions / cm 2 8.5×e15 ions / cm 2The dosage of the first ion implantation affects the doping concentration of the vacancy-fixing buried layer 120, thereby affecting the vacancy-fixing buried layer 120's ability to fix vacancies. By limiting the dosage of the first ion implantation within the aforementioned range, the vacancy-fixing buried layer 120 can have sufficient vacancy-fixing ability, thereby fully fixing the vacancies migrating downward from the amorphous region 110, reducing the number of unfixed vacancies, and further reducing the risk of vacancy agglomeration forming crystal structure defects such as voids and dislocations.

[0062] In some optional embodiments, the preparation method further includes: refer to Figure 6 Before depositing the semiconductor sacrificial layer 101 and performing the pre-amorphization implantation, a gate dielectric layer 200 and a gate layer 300 covering the gate dielectric layer 200 are formed on a local surface of one side of the semiconductor substrate 100; the amorphous region 110 and the semiconductor sacrificial layer 101 are both formed on both sides of the gate layer 300. Figure 7 A schematic diagram of the structure after removing the semiconductor sacrificial layer 101 is shown; refer to Figure 8 After removing the semiconductor sacrificial layer 101, a lightly doped source region 401 and a lightly doped drain region 402 are formed in the amorphous region 110 to form an ultra-shallow junction. The lightly doped source region 401 and the lightly doped drain region 402 are located on opposite sides of the gate layer 300, respectively. Figure 9 Sidewalls 500 are formed on the sidewalls of the gate dielectric layer 200 and the gate layer 300; Reference Figure 10 A heavily doped source region 601 and a heavily doped drain region 602 are formed in the semiconductor substrate 100, the heavily doped source region 601 and the heavily doped drain region 602 being located on both sides of the gate layer 300 covering the sidewalls 500; the semiconductor substrate 100 is then subjected to a second annealing. At this time, the resulting semiconductor structure is a field-effect transistor or a device containing a field-effect transistor.

[0063] refer to Figure 6 A vacancy-fixing buried layer 120 is also formed on both sides of the gate layer 300; Reference Figure 8 The thickness of the lightly doped source region 401 and the lightly doped drain region 402 may be less than or equal to the thickness of the amorphous region 110. The heavily doped source region 601 and the heavily doped drain region 602 are located above the vacancy-fixing buried layer 120 and do not overlap with the vacancy-fixing buried layer 120.

[0064] Specifically, the gate dielectric layer 200 is made of silicon oxide or a high dielectric material, and the gate layer 300 is made of undoped polysilicon or doped polysilicon.

[0065] The sidewall 500 is a silicon oxide layer, a silicon nitride layer, or a stacked structure of both. For example, when the sidewall 500 is a stacked structure of silicon oxide and silicon nitride, the fabrication steps of the sidewall 500 are as follows: depositing a silicon oxide material layer over the entire surface, the silicon oxide material layer covering the surface of the semiconductor substrate 100, the surface of the gate layer 300, and the sides of the gate layer 300 and the gate dielectric layer 200; depositing a silicon nitride material layer over the entire surface of the silicon oxide material layer; and patterning the silicon oxide and silicon nitride material layers using a dry etching process to form the sidewall 500 on the sides of the gate layer 300 and the gate dielectric layer 200.

[0066] A lightly doped source region 401 and a lightly doped drain region 402 are formed in the amorphous region 110 by performing a second ion implantation on the semiconductor substrate 100. Specifically, a patterned photoresist layer is formed on the surface of the semiconductor substrate 100, covering the gate layer 300. Using the photoresist layer as a mask, impurity ions are implanted into the semiconductor substrate 100 on both sides of the gate layer 300. When the field-effect transistor is an NMOS transistor, the impurity ions implanted into the semiconductor substrate 100 in the second ion implantation include phosphorus ions or arsenic ions; when the field-effect transistor is a PMOS transistor, the impurity ions implanted into the semiconductor substrate 100 in the second ion implantation include boron ions.

[0067] A third ion implantation is performed on the semiconductor substrate 100 to form a heavily doped source region 601 and a heavily doped drain region 602 on both sides of the gate layer 300 covered with sidewalls 500. A second annealing is used to activate the impurity ions in the lightly doped source region 401 and lightly doped drain region 402, as well as the heavily doped source region 601 and heavily doped drain region 602.

[0068] In some optional embodiments, the fabrication method further includes forming a trench isolation structure in the semiconductor substrate 100 before forming the gate dielectric layer 200. The trench isolation structure is a shallow trench isolation structure and / or a deep trench isolation structure to isolate the field-effect transistor from other devices. The resulting semiconductor structure is an integrated structure of the field-effect transistor and other devices, such as an integrated structure of HBT (heterojunction bipolar transistor) and CMOS, a memory chip (e.g., DRAM, NAND), or a logic chip (e.g., CPU, FPGA programmable logic chip).

[0069] In a second aspect, the present invention provides a semiconductor structure prepared by the preparation method described in the first aspect.

[0070] It should be noted that the features (such as materials, thickness, etc.) and effects described in the semiconductor structure preparation method in the first aspect also apply to this semiconductor structure, and will not be repeated here.

[0071] In summary, the semiconductor structure fabrication method provided by this invention involves depositing a semiconductor sacrificial layer 101 on the surface of a semiconductor substrate 100, wherein the formation energy of vacancies in the semiconductor sacrificial layer 101 is lower than that of vacancies in the semiconductor substrate 100. This allows some vacancies in the amorphous region 110 to migrate from the semiconductor substrate 100 to the semiconductor sacrificial layer 101, which has a lower formation energy, during the first annealing process. The vacancies that migrate to the semiconductor sacrificial layer 101 are removed from the semiconductor substrate 100 as the semiconductor sacrificial layer 101 is removed, thereby reducing the total number of vacancies in the semiconductor substrate 100. This reduces the risk of vacancies agglomerating and forming crystal structure defects such as voids and dislocations, and improves the performance and yield of the device.

[0072] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0073] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "too large" means greater than the upper limit of the defined numerical range, and "too small" means greater than the lower limit of the defined numerical range.

[0074] In the description of this specification, references to terms such as "some alternative embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described; however, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0075] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor sacrificial layer is deposited on the surface of a semiconductor substrate, wherein the formation energy of vacancies in the semiconductor sacrificial layer is lower than that of vacancies in the semiconductor substrate; The semiconductor substrate is pre-amorphized by implantation to form an amorphous region in the semiconductor substrate; After depositing the semiconductor sacrificial layer and performing the pre-amorphization implantation, the semiconductor substrate undergoes a first annealing. After the first annealing, the semiconductor sacrificial layer is removed.

2. The preparation method according to claim 1, characterized in that, The thickness of the semiconductor sacrificial layer is 25nm-150nm; And / or, the thickness of the amorphous region is 90nm-200nm; And / or, the ions implanted in the pre-amorphization process include germanium ions; And / or, the semiconductor substrate includes one of single-crystal silicon wafer and silicon-on-insulator, the material of the semiconductor sacrificial layer includes germanium silicon, the semiconductor sacrificial layer is removed by a wet etching process, and the etching solution contains hydrofluoric acid, hydrogen peroxide and acetic acid.

3. The preparation method according to claim 1, characterized in that, During the first annealing process, a solid-phase epitaxial growth process is performed on the semiconductor substrate.

4. The preparation method according to claim 3, characterized in that, The solid-phase epitaxial regeneration process is carried out at a temperature of 500℃-650℃ for a time of 10min-60min.

5. The preparation method according to claim 3, characterized in that, The first annealing process further includes: after performing the solid-phase epitaxial regeneration process, performing laser spike annealing or flash lamp annealing on the semiconductor substrate, wherein the temperature of the laser spike annealing or the flash lamp annealing is higher than the temperature of the solid-phase epitaxial regeneration process.

6. The preparation method according to claim 5, characterized in that, The laser peak annealing temperature is 700℃-900℃, the flash lamp annealing temperature is 650-850℃, and the pulse width of the laser peak annealing or the flash lamp annealing is 100μs-800μs.

7. The preparation method according to any one of claims 1 to 6, characterized in that, Also includes: Prior to the first annealing, the semiconductor substrate is subjected to a first ion implantation to form a vacancy-fixing buried layer, which is located below the amorphous region.

8. The preparation method according to claim 7, characterized in that, The first ion implanted ions include carbon ions; And / or, the thickness of the vacancy-fixing buried layer is 150nm-350nm; And / or, the spacing between the vacancy-fixing buried layer and the amorphous region is 0-30 nm; And / or, the energy of the first ion implantation is 150 keV-250 keV, and the dose of the first ion implantation is 1 × e15 ions / cm. 2 -9×e15 ions / cm 2 .

9. The preparation method according to claim 1, characterized in that, Also includes: Prior to depositing the semiconductor sacrificial layer and performing the pre-amorphization implantation, a gate dielectric layer and a gate layer covering the gate dielectric layer are formed on a local surface on one side of the semiconductor substrate; the amorphous region and the semiconductor sacrificial layer are both formed on both sides of the gate layer; After removing the semiconductor sacrificial layer, a lightly doped source region and a lightly doped drain region are formed in the amorphous region, the lightly doped source region and the lightly doped drain region being located on both sides of the gate layer, respectively; sidewalls are formed on the sidewalls of the gate dielectric layer and the gate layer; a heavily doped source region and a heavily doped drain region are formed in the semiconductor substrate, the heavily doped source region and the heavily doped drain region being located on both sides of the gate layer covering the sidewalls, respectively; and a second annealing is performed on the semiconductor substrate.

10. A semiconductor structure, characterized in that, It is prepared by any one of the preparation methods described in claims 1 to 9.

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