Power device integrated with overvoltage protection function, manufacturing method and chip

Abstract

The application discloses a power device integrated with overvoltage protection function, a manufacturing method and a chip, and belongs to the technical field of semiconductors. The power device integrated with overvoltage protection function comprises an N-type drift region, a groove, a first P-type ring, a first P-type well region, a second P-type ring, an oxide layer, a polysilicon layer, a P+ region, an N+ region, a first dielectric layer, a control electrode, an emitter metal, an N-type cutoff layer, a P-type collector region and a collector metal. When the control electrode is floating, the overvoltage protection function is activated; when voltage overshoot occurs, the potential of the P-type ring is raised along with the potential of the collector metal, the floating groove potential is raised at the same time, and an electron channel is generated in the first P-type well region on both sides of the floating groove, so that the voltage of the collector metal is clamped at a preset clamping voltage; when the control electrode is grounded, the potential of the P-type ring is clamped at zero potential, the overvoltage protection function is closed, and the switch control of the power device integrated with the overvoltage protection function is realized.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a power device with integrated overvoltage protection function, a manufacturing method, and a chip. Background Technology

[0002] In current power device designs, most IGBT (Insulated Gate Bipolar Transistor) power modules still rely on external drive circuits to achieve overvoltage protection. When a switching transient causes an overshoot in the collector voltage, the external protection circuit needs to trigger clamping through discrete components to prevent device breakdown. However, this approach not only increases the cost of packaging design and the size of the module, but also weakens the reliability of overvoltage protection due to signal delay in the circuit.

[0003] Related technologies use integrated avalanche diodes for overvoltage clamping within power devices. However, integrating an avalanche diode into the IGBT permanently locks the IGBT's breakdown voltage at a lower level than the avalanche diode, preventing it from recovering to the original device's rated breakdown voltage. This results in an irreversible and permanent decrease in the device's rated voltage capability. Therefore, it is difficult to meet the requirement of overvoltage protection without affecting the IGBT's fundamental parameters. Summary of the Invention

[0004] The purpose of this application is to provide a power device, manufacturing method, and chip with integrated overvoltage protection function, which can solve the problems of low reliability and uncontrollable function of existing power device overvoltage protection functions.

[0005] In a first aspect, embodiments of this application provide a power device with integrated overvoltage protection function, including: N-type drift region; the N-type drift region includes an overpressure protection zone; The trenches are located within the N-type drift zone and are flush with the upper surface of the N-type drift zone; the trenches are arranged laterally at intervals and are parallel to each other; the trenches include multiple dummy grid trenches and multiple floating trenches located in the overpressure protection zone, the dummy grid trenches are divided into two groups and arranged at both ends of the overpressure protection zone, and the floating trenches are arranged between the two groups of dummy grid trenches. The first P-type ring is located within the overvoltage protection zone, between and below the dummy grid trenches in each group; The first P-type trap region is located on both sides of the floating trench; The second P-ring is located below the floating groove; the second P-rings are in contact with each other, and the second P-rings at both ends are in contact with the first P-ring, but not with the first P-shaped trap area; An oxide layer is provided on the bottom and sidewalls of the trench; A polycrystalline silicon layer is disposed within an oxide layer inside the trench; the sides and bottom of the polycrystalline silicon layer are in contact with the oxide layer; The P+ region is located on both sides of each trench, within the N-type drift region, and flush with the upper surface of the N-type drift region. The N+ region is located on both sides of the floating groove, within the N-type drift region, and flush with the upper surface of the N-type drift region; one side of the N+ region is connected to the P+ region, and the other side is connected to the side of the floating groove. The first dielectric layer is disposed on the upper surface of the two sets of dummy grid trenches in the overvoltage protection zone; The control electrode is located on the upper surface of the P+ region between the dummy gate trenches in each group of the overvoltage protection zone within the first dielectric layer. An emitter metal is disposed on the upper surface of the N-type drift region, the upper surface of the first dielectric layer, and its side; the emitter metal is isolated from the control electrode through the first dielectric layer. An N-type cutoff layer is disposed below the N-type drift region; The P-type collector region is located below the N-type cutoff layer; The collector metal is disposed below the P-type collector region; When the control electrode is floating, the potential of the first P-ring and the second P-ring increases as the potential of the collector metal increases, which in turn increases the potential of the floating trench and generates an electron channel in the first P-type well region on both sides of the floating trench, so that the voltage of the collector metal is clamped at a preset clamping voltage; when the control electrode is grounded, the potential of the first P-ring and the second P-ring is zero.

[0006] Optionally, the preset clamping voltage is determined based on the doping concentration of the first P-type well region.

[0007] Optionally, the N-type drift region further includes: a cell region and a transition region; one side of the overvoltage protection zone is connected to the cell region, and the other side is connected to the transition region; the trench further includes multiple dummy gate trenches and at least one true gate trench located in the cell region, and multiple dummy gate trenches located in the transition region; the dummy gate trenches in the cell region are close to the overvoltage protection zone; the dummy gate trenches in the transition region are divided into a group of dummy gate trenches close to the overvoltage protection zone and a group of dummy gate trenches far from the overvoltage protection zone; the N+ region is also disposed on both sides of the true gate trench, within the N-type drift region, and flush with the upper surface of the N-type drift region, and the other side of the N+ region is connected to the P+ region; the emitter metal is also disposed on the upper surface of the N-type drift region of the cell region and the transition region; the power device with integrated overvoltage protection function further includes: The second P-type well region is located on both sides of the true gate trench, on both sides of the false gate trench in the cell region, and on both sides of the false gate trench group near the overvoltage protection zone in the transition region. The third P-type ring is located below the dummy grid trench group in the transition zone, which is far from the overpressure protection zone, and below the P+ area of ​​the transition zone.

[0008] Optionally, the doping concentration of the first P-type well region is less than the doping concentration of the second P-type well region.

[0009] Optionally, the area of ​​the overpressure protection zone is smaller than the area of ​​the cell region.

[0010] Optionally, the N-type drift region further includes: a terminal region; one side of the terminal region is connected to the side of the transition region away from the overvoltage protection zone; the third P-type ring is also disposed in the N-type drift region of the terminal region that contacts the transition region and is flush with the upper surface of the N-type drift region, and the third P-type ring in the terminal region contacts the third P-type ring in the transition region; the power device with integrated overvoltage protection function further includes: The terminal stop ring is located within the N-type drift region of the terminal area and is flush with the upper surface of the N-type drift region; the terminal stop ring does not contact the third P-type ring; The second dielectric layer is disposed on the upper surface of the terminal area, excluding the terminal cutoff ring. A metal field plate is disposed on the upper surface of the second dielectric layer; A stop ring metal is disposed on the upper surface of the terminal stop ring; the side of the stop ring metal is in contact with the side of the second dielectric layer.

[0011] Secondly, embodiments of this application provide a method for manufacturing a power device with integrated overvoltage protection function, used to manufacture the aforementioned power device with integrated overvoltage protection function, the method comprising: An N-type drift region is provided; the N-type drift region includes an overpressure protection zone; Etching is performed in the area within the N-type drift region and flush with the upper surface of the N-type drift region to form trenches; the trenches are arranged laterally at intervals and parallel to each other; the trenches include multiple dummy gate trenches and multiple floating trenches located in the overpressure protection zone, the dummy gate trenches are divided into two groups and arranged at both ends of the overpressure protection zone, and the floating trenches are arranged between the two groups of dummy gate trenches; P-type ions are injected into the overvoltage protection zone, between and below the dummy grid trenches in each group, to form a first P-type ring; P-type ions are injected into both sides of the floating trench to form a first P-type trap region; P-type ions are injected below the floating trench to form a second P-type ring; the second P-type rings are in contact with each other, and the second P-type rings at both ends are in contact with the first P-type ring, but not with the first P-type well region; An oxide layer is formed on the bottom and sidewalls of the trench; Polycrystalline silicon is deposited within the oxide layer inside the trench to form a polycrystalline silicon layer; the sides and bottom of the polycrystalline silicon layer are in contact with the oxide layer; N-type ions are injected into the areas on both sides of the floating trench, within the N-type drift region, and flush with the upper surface of the N-type drift region to form an N+ region; one side of the N+ region is connected to the side of the floating trench. P-type ions are injected into the areas on both sides of each trench, within the N-type drift region and flush with the upper surface of the N-type drift region, excluding the N+ region, to form the P+ region; A first dielectric layer is formed on the upper surface of the two sets of dummy grid trenches in the overvoltage protection zone; The first dielectric layer is etched, and metal is deposited on the upper surface of the P+ region between the dummy gate trenches in each group of the overvoltage protection zone to form a control electrode; Metal is deposited on the upper surface of the N-type drift region, the upper surface of the first dielectric layer, and the side region to form an emitter metal; the emitter metal is isolated from the control electrode through the first dielectric layer. N-type ions are injected below the N-type drift region to form an N-type cutoff layer; P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; Metal is deposited below the P-type collector region to form a collector metal; When the control electrode is floating, the potential of the first P-ring and the second P-ring increases as the potential of the collector metal increases, which in turn increases the potential of the floating trench and generates an electron channel in the first P-type well region on both sides of the floating trench, so that the voltage of the collector metal is clamped at a preset clamping voltage; when the control electrode is grounded, the potential of the first P-ring and the second P-ring is zero.

[0012] Optionally, the preset clamping voltage is determined based on the doping concentration of the first P-type well region.

[0013] Optionally, the N-type drift region further includes: a cell region and a transition region; one side of the overvoltage protection zone is connected to the cell region, and the other side is connected to the transition region; the trench further includes a plurality of dummy gate trenches and at least one true gate trench located in the cell region, and a plurality of dummy gate trenches located in the transition region; the dummy gate trenches in the cell region are close to the overvoltage protection zone; the dummy gate trenches in the transition region are divided into a group of dummy gate trenches close to the overvoltage protection zone and a group of dummy gate trenches far from the overvoltage protection zone; the N+ region is also disposed on both sides of the true gate trench, within the N-type drift region, and flush with the upper surface of the N-type drift region, and the other side of the N+ region is connected to the P+ region; the emitter metal is also disposed on the upper surface of the N-type drift region of the cell region and the transition region; the method further includes: P-type ions are injected on both sides of the true gate trench, both sides of the false gate trench in the cell region, and both sides of the false gate trench group near the overvoltage protection zone in the transition region to form a second P-type trap region. A third P-shaped ring is formed below the dummy grid trench group in the transition zone, away from the overpressure protection zone, and below the P+ zone of the transition zone.

[0014] Optionally, the doping concentration of the first P-type well region is less than the doping concentration of the second P-type well region.

[0015] Optionally, the area of ​​the overpressure protection zone is smaller than the area of ​​the cell region.

[0016] Optionally, the N-type drift region further includes: a terminal region; one side of the terminal region is connected to the side of the transition region away from the overpressure protection zone; the third P-type ring is also disposed in the N-type drift region of the terminal region that contacts the transition region and is flush with the upper surface of the N-type drift region, and the third P-type ring in the terminal region contacts the third P-type ring in the transition region; the method further includes: A terminal stop ring is formed in the N-type drift region of the terminal area and in a region flush with the upper surface of the N-type drift region; the terminal stop ring does not contact the third P-type ring; A second dielectric layer is formed on the upper surface of the terminal region, excluding the terminal stop ring; Metal is deposited on the upper surface of the second dielectric layer to form a metal field plate; Metal is deposited on the upper surface of the terminal stop ring, forming the stop ring metal; the side of the stop ring metal contacts the side of the second dielectric layer.

[0017] Thirdly, embodiments of this application provide a chip including the aforementioned power device with integrated overvoltage protection function.

[0018] The embodiments of this application have the following advantages: The power device with integrated overvoltage protection function in this application embodiment includes: an N-type drift region, a trench, a first P-type ring, a first P-type well region, a second P-type ring, an oxide layer, a polysilicon layer, a P+ region, an N+ region, a first dielectric layer, a control electrode, an emitter metal, an N-type cutoff layer, a P-type collector region, and a collector metal.

[0019] The N-type drift region includes an overvoltage protection zone; by integrating the overvoltage protection function into the power device, the system cost and size are reduced without relying on external discrete components, and signal delay is also avoided.

[0020] The trenches are located within the N-type drift region and are flush with the upper surface of the N-type drift region. The trenches are arranged laterally at intervals and are parallel to each other. The trenches include multiple dummy gate trenches and multiple floating trenches located in the overvoltage protection zone. The dummy gate trenches are divided into two groups and arranged at both ends of the overvoltage protection zone, and the floating trenches are arranged between the two groups of dummy gate trenches. The combination of the P-type ring, the first P-type well region, and the floating trenches forms an internal MOS structure, which can control the opening of the channel.

[0021] The first P-ring is located within the overvoltage protection zone, between and below the dummy gate trenches in each group; the first P-well area is located on both sides of the floating trench; the second P-ring is located below the floating trench; the second P-rings are in contact with each other, and the second P-rings at both ends are in contact with the first P-rings but not with the first P-well area; the first and second P-rings together constitute the main body of the protection structure, ensuring that when the protection function is activated, the overvoltage current can be guided to an independent, low-impedance path and will not flow through the main power device area, thereby avoiding thermal damage to the main device.

[0022] An oxide layer is located at the bottom and sidewalls of the trench; a polysilicon layer is located within the oxide layer inside the trench; the sides and bottom of the polysilicon layer are in contact with the oxide layer; the MOS structure can use the potential change of the floating polysilicon to control the opening of the channel, which is the basis for realizing self-turn-on and overvoltage protection.

[0023] The P+ region is located on both sides of each trench, within the N-type drift region, and flush with the upper surface of the N-type drift region; the N+ region is located on both sides of the floating trench, within the N-type drift region, and flush with the upper surface of the N-type drift region; one side of the N+ region is connected to the P+ region, and the other side is connected to the side of the floating trench; the N+ region, as an electron emission region, provides electronic current for the opening of the overvoltage protection structure, while the P+ region helps to form a good ohmic contact, suppressing device latch-up and ensuring the stability and reliability of the protection structure when it is opened.

[0024] The control electrode is located on the upper surface of the P+ region between the dummy gate trenches in each group of the overvoltage protection zone within the first dielectric layer; the emitter metal is located on the upper surface of the N-type drift region, the upper surface of the first dielectric layer, and the side; the emitter metal is isolated from the control electrode through the first dielectric layer; this ensures that the control electrode can be led out independently of the main emitter and can be reliably connected to the internal P-type ring, while also ensuring electrical insulation.

[0025] The N-type cutoff layer is located below the N-type drift region; the P-type collector region is located below the N-type cutoff layer; the collector metal is located below the P-type collector region; the overvoltage protection structure shares the same back structure (drift region, N-type cutoff layer, P-type collector region, collector metal) as the IGBT, achieving high integration without affecting the normal characteristics of the IGBT.

[0026] When the control electrode is floating, the potentials of the first and second P-rings increase as the collector metal potential increases, simultaneously raising the potential of the floating trench and generating electron channels in the first P-well regions on both sides of the floating trench, thus clamping the collector metal voltage to a preset clamping voltage. When the control electrode is grounded, the potentials of the first and second P-rings are zero. When the control electrode is floating, the overvoltage protection function is activated, and the gate potential of the floating trench automatically rises as the collector voltage increases. It automatically activates when a voltage overshoot occurs without any external drive signal, clamping the collector voltage within a safe range with a fast response. By grounding the control electrode, the potential of the P-rings can be clamped to zero potential, thereby disabling the overvoltage protection function and restoring the device's breakdown voltage to its unclamped rated value. This switchability improves the device's flexibility and enables controllable switching of the integrated overvoltage protection function within the power device. Attached Figure Description

[0027] Figure 1 This is a structural block diagram of a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 2 This is an overvoltage protection BV curve diagram according to an embodiment of this application; Figure 3 This is a structural block diagram of a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 4 This is a schematic diagram of the current path during overvoltage protection according to an embodiment of this application; Figure 5 This is a schematic diagram of the layout structure of a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 6 This is a flowchart illustrating the steps of a method for manufacturing a power device with integrated overvoltage protection according to an embodiment of this application. Figure 7This is a process structure diagram of a manufacturing method for a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 8 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 9 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 10 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 11 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 12 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 13 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 14 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 15 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 16 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 17 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application; Figure 18 This is a process structure diagram of another method for manufacturing a power device with integrated overvoltage protection function according to an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures: N-type drift region 01, trench 02, dummy gate trench E, floating trench F, real gate trench G, first P-type ring 03, first P-type well region 04, second P-type ring 05, oxide layer 06, polysilicon layer 07, P+ region 08, N+ region 09, first dielectric layer 10, control electrode 11, emitter metal 12, N-type cutoff layer 13, P-type collector region 14, collector metal 15, second P-type well region 16, third P-type ring 17, termination cutoff ring 18, second dielectric layer 19, metal field plate 20, cutoff ring metal 21, overvoltage protection zone 100, cell region 200, transition region 300, termination region 400, gate pad region 500. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0031] The power device with integrated overvoltage protection provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0032] Reference Figure 1 This diagram illustrates a structural block diagram of a power device with integrated overvoltage protection according to an embodiment of this application. The power device with integrated overvoltage protection includes: N-type drift zone 01; the N-type drift zone 01 includes an overpressure protection zone 100; The trench 02 is disposed within the N-type drift zone 01 and is flush with the upper surface of the N-type drift zone 01; the trench 02 is arranged laterally at intervals and parallel to each other; the trench 02 includes a plurality of dummy grid trenches E and a plurality of floating trenches F located in the overpressure protection zone 100, the dummy grid trenches E are divided into two groups and arranged at both ends of the overpressure protection zone 100 respectively, and the floating trenches F are arranged between the two groups of dummy grid trenches E; The first P-type ring 03 is located within the overvoltage protection zone 100, between and below the dummy grid trenches E in each group; The first P-type trap region 04 is located on both sides of the floating trench F; The second P-type ring 05 is located below the floating groove F; the second P-type rings 05 are in contact with each other, and the second P-type rings 05 at both ends are in contact with the first P-type ring 03, but not in contact with the first P-type trap area 04. Oxide layer 06 is provided on the bottom and sidewalls of the trench; A polysilicon layer 07 is disposed within the oxide layer 06 inside the trench; the sides and bottom of the polysilicon layer 07 are in contact with the oxide layer 06. P+ area 08 is located on both sides of each groove, inside the N-type drift area 01, and flush with the upper surface of the N-type drift area 01. N+ region 09 is located on both sides of the floating groove F, inside the N-type drift region 01, and flush with the upper surface of the N-type drift region 01; one side of N+ region 09 is connected to P+ region 08, and the other side is connected to the side of the floating groove F. The first dielectric layer 10 is disposed on the upper surface of the two sets of dummy grid trenches E in the overvoltage protection zone 100; The control electrode 11 is disposed on the upper surface of the P+ region 08 between the dummy gate trenches E in each group of the overvoltage protection zone 100 within the first dielectric layer 10; Emitter metal 12 is disposed on the upper surface of the N-type drift region 01, the upper surface of the first dielectric layer 10, and the side; the emitter metal 12 is isolated from the control electrode 11 through the first dielectric layer 10; The N-type cutoff layer 13 is disposed below the N-type drift region 01; The P-type collector region 14 is located below the N-type cutoff layer 13; Collector metal 15 is disposed below the P-type collector region 14; When the control electrode 11 is floating, the potentials of the first P-ring 03 and the second P-ring 05 increase as the potential of the collector metal 15 increases, which in turn increases the potential of the floating trench F and generates electron channels in the first P-type well regions 04 on both sides of the floating trench F, so that the voltage of the collector metal 15 is clamped at a preset clamping voltage; when the control electrode 11 is grounded, the potentials of the first P-ring 03 and the second P-ring 05 are zero.

[0033] In this embodiment, the core structure of the power device is built on an N-type drift region. The N-type drift region is the main area that bears the operating voltage of the device, and it includes an overvoltage protection zone, which has an overvoltage protection function for the power device.

[0034] Within the N-type drift region, and in an area flush with the upper surface of the N-type drift region, a series of trenches are formed through an etching process. These trenches are laterally uniformly distributed on the chip plane and remain parallel to each other. Within the overvoltage protection zone, these trenches are designed in two different types: dummy gate trenches (E) and floating trenches (F). Specifically, the dummy gate trenches are divided into two groups, located at the left and right ends of the overvoltage protection zone, respectively; while the floating trenches are located between these two groups of dummy gate trenches. This special arrangement is key to achieving the voltage clamping function.

[0035] Within the overvoltage protection zone, a first P-ring (Ring 1) was formed by ion implantation in the region between each set of dummy gate trenches and at the bottom of the trenches.

[0036] On both sides of each floating trench (i.e., at the junction of the trench and the N-type drift region), a first P-type well region (Pwell1) is formed by ion implantation. The doping concentration of the first P-type well region can be lower than that of the P-type well in the main functional region of the device to achieve a specific turn-on voltage.

[0037] Directly beneath each floating trench, a second P-ring (Ring 2) is formed via ion implantation. All these second P-rings are horizontally interconnected, forming a continuous P-type region. The second P-rings at both ends contact the corresponding first P-rings (Ring 1), thus connecting all the P-rings into a single unit. This unified P-ring region is not in direct contact with the first P-well regions (Pwell 1) on either side of the floating trench.

[0038] Oxygen is introduced into a high-temperature environment of 1100℃ to grow an oxide layer of about 0.1 μm on the bottom and sidewalls of the trench as the oxide layer of the IGBT.

[0039] A polysilicon layer is filled on top of the oxide layer inside the trench. Due to the trench structure, the polysilicon layer is laterally encased by the oxide layer inside the trench, forming a conductor structure surrounded by an insulator. In dummy gate trenches, the polysilicon layer is grounded; while in floating trenches, the polysilicon layer is electrically floating.

[0040] On both sides of each trench, within the N-type drift region adjacent to the trench edge and flush with the upper surface of the N-type drift region, a P+ region was formed through high-concentration ion implantation. On both sides of the floating trench, in addition to the P+ region, an N+ region was also formed, with one side of the N+ region overlapping or closely connected to the P+ region.

[0041] A dielectric layer, namely the first dielectric layer, is grown or deposited on the entire surface of the device and on the upper surface of the N-type drift region that is not covered by the trench. The first dielectric layer may be composed of silicon dioxide.

[0042] The control electrode (G2) is located on the upper surface of the P+ region between the dummy gate trenches in each group of the overvoltage protection zone within the first dielectric layer, and is directly connected to the first P-ring (Ring 1).

[0043] At the top of the device, there is an emitter metal layer that connects all the P+ and N+ regions, serving as the emitter of the device. Directly above the dummy gate trench group in the overvoltage protection zone, the emitter metal has a cutout, meaning there is no metal layer here, providing space for the lead-out and isolation of the control electrode.

[0044] Below the N-type drift region, a highly doped N-type cutoff layer (N+ buffer) is implanted. Below the N-type cutoff layer, a P-type collector region (P+ collector) is formed. At the bottom of the P-type collector region, collector metal is deposited as the collector of the device.

[0045] The overvoltage protection function can be controlled to be turned on and off by adjusting the floating or grounded potential of G2. Specifically, when the control electrode (G2) is in a floating state, the potentials of the first P-ring (Ring 1) and the second P-ring (Ring 2) automatically rise as the collector voltage increases, and the potential of the floating trench gate also increases with the collector voltage. When the collector voltage rises high enough to induce an electron channel in the first P-well region 04 on both sides of the floating trench, a low-impedance discharge path is formed, clamping the collector voltage at a preset safe voltage value (Vclamp, preset clamping voltage), thereby achieving overvoltage protection. When the control electrode (G2) is connected to ground (GND), it locks the potentials of the first P-ring (Ring 1) and the second P-ring (Ring 2) at 0V. In this way, no matter how high the collector voltage rises, an electron channel cannot be induced in the first P-well region 04 on both sides of the floating trench, and the overvoltage protection function is disabled. At this point, the device's breakdown voltage will return to its original design rating and will not be reduced due to the presence of the protective structure.

[0046] Reference Figure 2 The diagram illustrates an overvoltage protection BV curve according to an embodiment of this application. Figure 2 As shown, when the G2 electrode is grounded, the overvoltage protection function is not activated, and the breakdown voltage of the device is the original rated breakdown voltage of the IGBT, 724V. When the G2 electrode is floating, the overvoltage protection zone will work normally and clamp the breakdown voltage of the device at 650V.

[0047] The power device with integrated overvoltage protection in this embodiment includes: an N-type drift region, a trench, a first P-type ring, a first P-type well region, a second P-type ring, a dielectric layer, a polysilicon layer, a P+ region, an N+ region, an emitter metal, a control electrode, an N-type cutoff layer, a P-type collector region, and a collector metal. The N-type drift region includes an overvoltage protection zone. By integrating the overvoltage protection function within the power device, it eliminates the need for external discrete components, reducing system cost and size, and avoiding signal delay. The combination of P-type rings (03, 05), the first P-type well region 04, and the floating trench forms an internal MOS structure, which can control the channel's opening. The first and second P-type rings together constitute the main body of the protection structure, ensuring that when the protection function is activated, the overvoltage current can be guided to an independent, low-impedance path, rather than flowing through the main power device region, thereby avoiding thermal damage to the main device. The MOS structure can utilize the potential change of the floating polysilicon to control the channel's opening, which is the physical basis for achieving self-turn-on and potential lockout functions. The N+ region, acting as the electron emitter region, provides the electron current for the overvoltage protection structure to activate. The P+ region helps form a good ohmic contact, suppressing device latch-up and ensuring the stability and reliability of the protection structure during activation. By creating a hole in the emitter metal and using a dielectric layer for isolation, the control electrode can be led out independently of the main emitter and reliably connected to the internal P-ring, while ensuring electrical insulation. The overvoltage protection structure shares the same back-side structure (drift region, N-type cutoff layer, P-type collector region, collector metal) as the IGBT, achieving high integration without affecting the normal characteristics of the IGBT. When the control electrode is floating, the overvoltage protection function is activated. Utilizing the potential change of the floating trench, it automatically turns on when a voltage overshoot occurs without any external drive signal, clamping the collector voltage within a safe range with a fast response speed. By grounding the control electrode, the potential of the P-ring can be clamped to zero potential, thereby turning off the overvoltage protection function and restoring the device's breakdown voltage to its unclamped rated value. This switchability improves the device's flexibility and enables the switch controllable integration of overvoltage protection function within the power device.

[0048] Reference Figure 3This diagram illustrates a structural block diagram of a power device integrating overvoltage protection according to an embodiment of this application. The N-type drift region 01 further includes: a cell region 200 and a transition region 300; one side of the overvoltage protection zone 100 is connected to the cell region 200, and the other side is connected to the transition region 300; the trench further includes a plurality of dummy gate trenches E and at least one true gate trench G located in the cell region 200, and a plurality of dummy gate trenches E located in the transition region 300; the dummy gate trenches E in the cell region 200 are close to the overvoltage protection zone 100; the dummy gate trenches E in the transition region 300 are divided into those adjacent to... The dummy gate trenches E group near the overvoltage protection zone 100 and the dummy gate trenches E group away from the overvoltage protection zone 100; the N+ region 09 is also disposed on both sides of the true gate trench G, within the N-type drift region 01 and flush with the upper surface of the N-type drift region 01, and the other side of the N+ region 09 is connected to the P+ region 08; the emitter metal 12 is also disposed on the upper surface of the N-type drift region 01 of the cell region 200 and the transition region 300; the power device integrating overvoltage protection function further includes: The second P-type well region 16 is located on both sides of the true gate trench G, on both sides of the false gate trench E of the cell region 200, and on both sides of the false gate trench E group of the transition region 300 near the overvoltage protection zone 100. The third P-type ring 17 is located below the dummy grid trench E group in the transition zone 300, which is far from the overpressure protection zone 100, and below the P+ zone 08 of the transition zone 300.

[0049] In this embodiment, the N-drift region includes: a cell region, an overvoltage protection zone, and a transition region arranged horizontally in sequence. The cell region is a region integrating a large number of IGBT cells, responsible for the main current conduction function of the device. The overvoltage protection zone is located between the cell region and the transition region, enabling the overvoltage protection zone to effectively protect the internal cell region and smoothly connect with the external termination structure.

[0050] Within the cell region, in addition to the special structure of the overvoltage protection zone, there are also true gate trenches G that constitute the IGBT cell, and dummy gate trenches E used to optimize parasitic capacitance. In the transition region, multiple sets of dummy gate trenches E are densely arranged to isolate the operating current from the cell region and the overvoltage protection zone from entering the termination region, improving device reliability. The dummy gate trenches E in the transition region are divided into two groups: one group is close to the overvoltage protection zone, and the other group is far away from the overvoltage protection zone.

[0051] On both sides of the true gate trench in the cell region, N+ regions are formed. One side of the N+ region is connected to the P+ region, together forming the emitter contact of the cell.

[0052] The emitter metal is a conductive metal layer covering the cell region and transition region. It is connected to all the P+ and N+ regions below through contact holes, serving as the common emitter lead of all IGBT cells.

[0053] The second P-type well region (Pwell2) is the P-type region that constitutes the IGBT cell and part of the terminal structure. It is distributed on both sides of the true gate trench G and the dummy gate trench E in the cell region, as well as on both sides of the dummy gate trench E near the overvoltage protection zone in the transition region.

[0054] The third P-type ring is the P-type doped region located on the outermost side of the transition region (far from the overvoltage protection zone), below the pseudo-gate trench E and below the P+ region in this region.

[0055] This embodiment of the application seamlessly integrates the overvoltage protection zone between the cell region and the transition region, ensuring high compatibility of the overvoltage protection structure with existing IGBT process platforms. Conventional IGBT chip structures are used in the cell region, transition region, and termination region. The cell region structure (such as the true gate trench G, dummy gate trench E, and second P-type well region 15) ensures the parameter requirements of the power device during normal operation. Multiple sets of dummy gate trenches E in the transition region isolate the operating current from the cell region and the overvoltage protection zone from entering the termination region. Simultaneously, the third P-type ring below the transition region effectively mitigates the electric field concentration effect at the bottom of the transition region trench, preventing premature breakdown due to electric field concentration at high voltages, thus reducing the device's withstand voltage. Under normal operating conditions, the IGBT operates normally as a whole across all regions. When an overvoltage event occurs, the overvoltage protection zone is preferentially activated, clamping the voltage within a safe range, thereby protecting the cell region from damage.

[0056] In one embodiment, such as Figure 3 As shown, the N-type drift region 01 further includes: a terminal region 400; one side of the terminal region 400 is connected to the side of the transition region 300 away from the overvoltage protection zone 100; the third P-type ring 17 is also disposed in the N-type drift region 01 in the terminal region 400 that contacts the transition region 300 and is flush with the upper surface of the N-type drift region 01, and the third P-type ring 17 in the terminal region 400 contacts the third P-type ring 17 in the transition region 300; the power device with integrated overvoltage protection function further includes: The terminal stop ring 18 is located within the N-type drift region 01 of the terminal region 400 and is flush with the upper surface of the N-type drift region 01; the terminal stop ring 18 is not in contact with the third P-type ring 17; The second dielectric layer 19 is disposed on the upper surface of the terminal region 400, excluding the terminal stop ring 18. Metal field plate 20 is disposed on the upper surface of the second dielectric layer 19; A stop ring metal 21 is disposed on the upper surface of the terminal stop ring 18; the side of the stop ring metal 21 is in contact with the side of the second dielectric layer 19.

[0057] In this embodiment, the N-drift region includes, in addition to the cell region, overvoltage protection region, and transition region, an outermost termination region. The termination region is a critical area in power devices used to protect chip edges and prevent premature breakdown caused by concentrated surface electric fields. The termination region is located on the side of the transition region furthest from the overvoltage protection region, i.e., on the outermost side of the entire chip layout.

[0058] In the terminal region, a third P-type ring is also placed at the interface adjacent to the transition region. The third P-type ring in the terminal region and the third P-type ring in the transition region are in direct physical contact, forming a continuous P-type doped ring. This design can effectively alleviate the electric field concentration phenomenon at the bottom of the pseudo-gate trench in the transition region and prevent premature breakdown in the transition region.

[0059] A second dielectric layer 19 is formed on the upper surface of a portion of the N-type drift region 01 in the terminal region 400. Above the second dielectric layer, a metal field plate is formed by depositing metal and etching a specific pattern. This field plate structure can effectively control the electric field distribution on the surface of the third P-type ring, improving device reliability.

[0060] In the terminal region, a stop ring metal layer is also disposed on the upper surface of the N-type drift region 01, excluding the second dielectric layer 19. The side of the stop ring metal 21 is in contact with the side of the second dielectric layer 19. The stop ring metal is directly electrically connected to the N-type drift region below through a contact hole.

[0061] A terminal stop ring is set in the N-type drift region of the terminal area, directly below the stop ring metal. The terminal stop ring does not contact the third P-type ring, and the stop ring is usually N+ doped.

[0062] This application embodiment forms a JTE termination with a metal field plate through the collaborative design of the third P-type ring in the termination region, the metal field plate, the metal stop ring, and the termination stop ring. This structure can shorten the termination length, save chip area, and ensure high breakdown voltage, thus ensuring device reliability. The third P-type ring in the termination region is in continuous contact with the third P-type ring in the transition region, reducing the electric field concentration at the bottom of the trench in the transition region. This design avoids abrupt changes in the electric field at the region boundary, thereby reducing the risk of premature breakdown caused by electric field concentration.

[0063] Reference Figure 4 The diagram illustrates a current path during overvoltage protection according to an embodiment of this application. Figure 4As shown, when a voltage overshoot occurs, the overvoltage protection zone channel opens to form a current path. The current will not pass through the IGBT cell region and the terminal region, and will not affect the device.

[0064] In one embodiment, the preset clamping voltage is determined based on the doping concentration of the first P-type well region O4.

[0065] In this embodiment, the preset clamping voltage refers to a specific safe threshold value that the power device with integrated overvoltage protection function clamps the voltage to through the overvoltage protection zone when an overvoltage event occurs. This voltage value is achieved by adjusting the doping concentration of the first P-type well region. By adjusting the concentration of the first P-type well region, the threshold value of the MOS structure channel formed by it and the floating trench can be adjusted. The lower the concentration, the smaller the threshold value of the MOS structure, the easier it is for the protection structure to be activated, and the easier it is to clamp the collector voltage. Therefore, under the condition that the overvoltage protection function is activated (i.e., G2 floating state), the lower the concentration of the first P-type well region, the lower the breakdown voltage. Therefore, by precisely controlling the doping concentration of the first P-type well region, the breakdown voltage of the overvoltage protection zone can be quantitatively adjusted, thereby setting the required preset clamping voltage value. This design enables the device to reliably trigger the breakdown protection mechanism when the preset overvoltage threshold is reached, clamping the voltage within a safe range and protecting the internal cell region from overvoltage damage.

[0066] By adjusting the doping concentration of the first P-type well region, a preset clamping voltage can be flexibly and quantitatively designed to precisely match the protection requirements of the application circuit. Precisely controlling the doping concentration to set the clamping voltage ensures that the overvoltage protection zone remains in a blocking state under normal operating voltage, while rapidly and reliably triggering breakdown in the event of an overvoltage event, clamping the voltage to the preset value. This mechanism effectively prevents permanent device damage caused by overvoltage, significantly improving device reliability and lifespan. By designing the preset clamping voltage in association with the doping concentration of the first P-type well region, precise control of the overvoltage protection threshold is achieved, balancing process compatibility, design flexibility, and protection reliability. This provides an efficient and customizable solution for overvoltage protection of power devices in different application scenarios, while simplifying system design and manufacturing costs.

[0067] In one embodiment, the doping concentration of the first P-type well region 04 is less than the doping concentration of the second P-type well region 15.

[0068] In this embodiment, the first P-type well region is located in the overvoltage protection zone and is the core region that determines the preset clamping voltage of the device. The second P-type well region is distributed on both sides of the true gate trench in the cell region and on both sides of the dummy gate trench group near the overvoltage protection zone in the transition region. The first P-type well region has a lower doping concentration, thus reliably triggering breakdown at the preset voltage during an overvoltage event, clamping the voltage to a safe value, and protecting the internal cell region. The second P-type well region has a higher doping concentration than the first P-type well region, and can be used to adjust the threshold voltage of the IGBT cell region and to form a PN junction between the cell region and the N-type substrate to bear the breakdown voltage of the cell region.

[0069] Reference Figure 5 This diagram illustrates a layout structure of a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 5 The section shown along line A-A1 is... Figure 3 The structure shown. (As illustrated) Figure 5 As shown, the power device includes: a cell region 200, an overvoltage protection zone 100, a transition region 300, a termination region 400, and a gate pad region 500. The area of ​​the overvoltage protection zone 100 is smaller than the area of ​​the cell region 200.

[0070] In this embodiment, the cell region occupies most of the total device area, effectively ensuring the device's power requirements. The overvoltage protection zone is located at the edge of the cell region and occupies only a small portion of the device area, ensuring that it does not affect the normal operation of the power IGBT device area and maintains high integration.

[0071] The power cell region, as the main functional area of ​​a device, consists of a large number of periodically arranged power cells responsible for withstanding high current densities and performing switching functions. Its area directly affects the device's conduction capability, power handling capability, and efficiency, typically occupying a large portion of the chip area to meet application requirements. The overvoltage protection zone is used to clamp the voltage to a safe threshold through a preset breakdown mechanism in the event of an overvoltage event, preventing high voltage from damaging the power cell region and sensitive structures. Since the overvoltage protection zone only needs to provide sufficient protection capabilities and does not participate in high-power handling, its area is designed to be much smaller than that of the power cell region. This maximizes the effective working area of ​​the power cell region while ensuring protection functions, thereby optimizing the overall device performance and cost.

[0072] This application embodiment designs the overvoltage protection area to be much smaller than the cell region, which significantly improves the chip's power density, cost-effectiveness, switching performance and thermal reliability while ensuring reliable overvoltage protection. It also gives the design greater flexibility and failure controllability, enabling the device to have both high performance and economy in high-voltage and high-power applications.

[0073] Reference Figure 6This document illustrates a flowchart of a method for manufacturing a power device with integrated overvoltage protection, according to an embodiment of this application. The method is used to manufacture the aforementioned power device with integrated overvoltage protection. Specifically, the manufacturing method may include the following steps: Step 301, providing an N-type drift region 01; the N-type drift region 01 includes a cell region 200, an overpressure protection zone 100, a transition zone 300 and a terminal zone 400 arranged horizontally in sequence; Reference Figure 7 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 7 As shown, an N-type doped drift region (N-drift) is first prepared as the substrate of the device.

[0074] Step 302: Etching is performed in the area within the N-type drift region 01 and flush with the upper surface of the N-type drift region 01 to form trenches; the trenches are arranged laterally at intervals and parallel to each other; the trenches include multiple dummy gate trenches E and multiple floating trenches F located in the overpressure protection zone 100, multiple dummy gate trenches E and at least one true gate trench G located in the cell region 200, and multiple dummy gate trenches E located in the transition region 300; the dummy gate trenches E in the overpressure protection zone 100 are divided into two groups and arranged at both ends of the overpressure protection zone 100, and the floating trenches F are arranged between the two groups of dummy gate trenches E; the dummy gate trenches E in the cell region 200 are close to the overpressure protection zone 100; the dummy gate trenches E in the transition region 300 are divided into a group of dummy gate trenches E close to the overpressure protection zone 100 and a group of dummy gate trenches E far from the overpressure protection zone 100; Reference Figure 8 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 8 As shown, silicon is etched to form trenches. The N-type drift region is divided into four functional regions from left to right: cell region, overvoltage protection region, transition region, and terminal region. Photolithography and etching processes are performed on the surface of the N-type drift region to form a series of parallel trenches.

[0075] The overvoltage protection zone comprises two sets of dummy gate trenches and a floating trench located between the two sets. The cell region contains at least one true gate trench and multiple dummy gate trenches (near the overvoltage protection zone). The transition region contains two sets of dummy gate trenches, one set near the overvoltage protection zone and the other set away (near the terminal region). The dummy gate trenches are used for parasitic capacitance regulation, the true gate trenches are used for cell region switching control, and the floating trenches are used to activate the overvoltage protection structure.

[0076] Step 303: P-type ions are injected into the overvoltage protection zone 100, between and below the dummy gate trenches E in each group, to form a first P-type ring 03; Step 304: In the transition zone 300, below the dummy grid trench E group away from the overvoltage protection zone 100, below the P+ region 08 of the transition zone 300, and within the N-type drift region 01 in the terminal zone 400 that contacts the transition zone 300 and is flush with the upper surface of the N-type drift region 01, a third P-type ring 17 is formed; the third P-type ring 17 in the terminal zone 400 contacts the third P-type ring 17 in the transition zone 300; Reference Figure 9 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 9 As shown, P-type ring ion implantation is performed in the pseudo-gate trench, transition region, and terminal region, followed by high-temperature annealing, to form a first P-type ring Ring1 and a third P-type ring GRing.

[0077] Within the overvoltage protection zone, P-type ion implantation (such as boron doping) is performed on the region between each set of dummy gate trenches and below them to form a continuous first P-type ring. The first P-type ring surrounds each set of dummy gate trenches, forming a PN junction array with the N-type drift region.

[0078] P-type ions are implanted below the pseudo-grid trench group in the transition zone, away from the overpressure protection zone, below the P+ region in the transition zone, and on the upper surface where the terminal region contacts the transition zone to form a third P-type ring. The third P-type ring in the terminal region is in physical contact with the third P-type ring in the transition region.

[0079] Step 305: P-type ions are injected into both sides of the floating trench F to form the first P-type trap region 04; Step 306: P-type ions are injected below the floating trench F to form a second P-type ring 05; the second P-type rings 05 are in contact with each other, and the second P-type rings 05 at both ends are in contact with the first P-type ring 03, but not with the first P-type trap region 04. Reference Figure 10 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 10 As shown, P-type ion implantation is performed in the floating trench region, followed by high-temperature annealing, simultaneously forming a first P-type well region (Pwell1) and a second P-type ring (Ring2) at the bottom of the floating trench. A relatively lower concentration of P-type ions is implanted in the two sides of the floating trench to form the first P-type well region.

[0080] Step 307: An oxide layer 06 is formed at the bottom and sidewalls of the trench; Reference Figure 11 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 11As shown, in the gate oxide process, oxygen is introduced into a high-temperature environment of 1100℃ to grow an oxide layer of about 0.1um on the sidewall and surface of the trench as the oxide layer of the IGBT.

[0081] Step 308: A terminal stop ring 18 is formed in the N-type drift region 01 of the terminal region 400 and in the region flush with the upper surface of the N-type drift region 01; the terminal stop ring 18 is not in contact with the third P-type ring 17. Reference Figure 12 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 12 As shown, N-type ions are implanted and annealed at high temperature to form a terminal cutoff ring.

[0082] Step 309: Polysilicon is deposited in the oxide layer 06 inside the trench to form a polysilicon layer 07; the sides and bottom of the polysilicon layer 07 are in contact with the oxide layer 06. Reference Figure 13 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 13 As shown, polysilicon is deposited within trenches where a gate oxide dielectric layer has already grown, filling the trenches with polysilicon. The polysilicon layer is then encapsulated by the gate oxide, forming a trench gate structure.

[0083] Step 310: P-type ions are injected on both sides of the true gate trench G, both sides of the false gate trench E of the cell region 200, and both sides of the false gate trench E group near the overvoltage protection zone 100 in the transition region 300 to form a second P-type trap region 16. Reference Figure 14 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 14 As shown, the second P-type well region Pwell2 is injected and annealed, forming Pwell2 on both sides of the true gate trench and on both sides of the dummy gate trench in the transition region. Because the injection dose of Pwell2 is more concentrated than that of Pwell1, the junction depth of Pwell2 is deeper.

[0084] Step 311: N-type ions are injected into the areas on both sides of the floating trench, within the N-type drift region, and flush with the upper surface of the N-type drift region to form an N+ region; one side of the N+ region is connected to the side of the floating trench. Step 312: P-type ions are injected into both sides of each trench, within the N-type drift region and flush with the upper surface of the N-type drift region, excluding the N+ region, to form the P+ region; Reference Figure 15This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 15 As shown, N-type ions and P-type ions are implanted using N+Mask and P+Mask respectively to form N+ regions and P+ regions.

[0085] Step 313: Deposit and etch dielectric layers to obtain first dielectric layer 10 and second dielectric layer 19; deposit and etch metal to obtain control electrode 11, emitter metal 12, metal field plate 20 and cutoff ring metal 21; Reference Figure 16 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 16 As shown, the isolation between the control electrode 11 and the emitter metal 12 is achieved through the deposition and etching processes of the dielectric layer and the metal.

[0086] Step 314: N-type ions are injected below the N-type drift region 01 to form an N-type cutoff layer 13; Step 315: P-type ions are implanted below the N-type cutoff layer 13 to form a P-type current collector region 14; Reference Figure 17 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 17 As shown, N-type ions and P-type ions are implanted on the back side, respectively, and after laser annealing, an N-type cutoff layer and a P-type collector region are formed. N-type ions are implanted below the N-type drift region (on the substrate side) to form an N-type cutoff layer.

[0087] P-type ions are injected below the N-type cutoff layer to form a P-type collector region.

[0088] Step 316: Deposit metal below the P-type collector region 14 to form collector metal 15; when the control electrode 11 is floating, the potential of the first P-type ring 03 and the second P-type ring 05 increases as the potential of the collector metal 15 increases, causing the floating trench gate potential to rise, and the overvoltage protection structure to be activated so that the voltage of the collector metal 15 is clamped at a preset clamping voltage; when the control electrode 11 is grounded, the potential of the first P-type ring 03 and the second P-type ring 05 is zero.

[0089] Reference Figure 18 This diagram illustrates the process structure of a manufacturing method for a power device with integrated overvoltage protection provided in an embodiment of this application. Figure 18As shown, metal is finally deposited on the back side to form the collector metal. Metal is deposited below the P-type collector region to form the collector metal. When the control electrode is floating, the potentials of the first and second P-type rings increase with the collector potential, and the gate potential of the floating trench increases. When the collector voltage exceeds a preset threshold, the overvoltage protection zone (the first P-type ring and the N-type drift region) breaks down, clamping the voltage to the preset value. When the control electrode is connected to zero potential, the potentials of the first and second P-type rings are fixed at zero, the device operates normally, and the overvoltage protection function is disabled.

[0090] In one embodiment, the preset clamping voltage is determined based on the doping concentration of the first P-type well region.

[0091] In one embodiment, the doping concentration of the first P-type well region is less than the doping concentration of the second P-type well region.

[0092] In one embodiment, the area of ​​the overpressure protection zone is smaller than the area of ​​the cell region.

[0093] This embodiment of the application establishes a self-turn-on MOS structure at the edge of the IGBT cell region, consisting of a low-doped Pwell1 region, a floating polysilicon trench F, and P-type rings (Ring1 / Ring2). This eliminates the need for external sampling circuits and drive intervention. It automatically turns on when the voltage exceeds a preset value Vclamp, clamping the collector voltage and achieving monolithic integrated protection, thus reducing module size and design cost. A control electrode G2 is introduced and connected to the P-type rings (Ring1 / Ring2). The connection method of G2 (floating or grounded) controls the activation or deactivation of the protection function. When G2 is grounded, the protection function is off, and the IGBT can recover to its original rated breakdown voltage without affecting the device's performance in non-overvoltage scenarios. When an overvoltage occurs, the current forms a path through the MOS channel of the overvoltage protection zone, bypassing the main IGBT cell region and termination region. This avoids the protection current flowing through the main device region, preventing localized thermal stress accumulation and material degradation caused by frequent overvoltage events, and extending the device's lifespan.

[0094] This application also provides a chip, including the power device with integrated overvoltage protection function described above.

[0095] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0097] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A power device with integrated overvoltage protection function, characterized in that, include: N-type drift zone; The N-type drift region includes an overpressure protection zone; The trenches are located within the N-type drift zone and are flush with the upper surface of the N-type drift zone; the trenches are arranged laterally at intervals and are parallel to each other; the trenches include multiple dummy grid trenches and multiple floating trenches located in the overpressure protection zone, the dummy grid trenches are divided into two groups and arranged at both ends of the overpressure protection zone, and the floating trenches are arranged between the two groups of dummy grid trenches. The first P-type ring is located within the overvoltage protection zone, between and below the dummy grid trenches in each group; The first P-type trap region is located on both sides of the floating trench; The second P-ring is located below the floating groove; the second P-rings are in contact with each other, and the second P-rings at both ends are in contact with the first P-ring, but not with the first P-shaped trap area; An oxide layer is provided on the bottom and sidewalls of the trench; A polycrystalline silicon layer is disposed within an oxide layer inside the trench; the sides and bottom of the polycrystalline silicon layer are in contact with the oxide layer; The P+ region is located on both sides of each trench, within the N-type drift region, and flush with the upper surface of the N-type drift region. The N+ region is located on both sides of the floating groove, within the N-type drift region, and flush with the upper surface of the N-type drift region; one side of the N+ region is connected to the P+ region, and the other side is connected to the side of the floating groove. The first dielectric layer is disposed on the upper surface of the two sets of dummy grid trenches in the overvoltage protection zone; The control electrode is located on the upper surface of the P+ region between the dummy gate trenches in each group of the overvoltage protection zone within the first dielectric layer. An emitter metal is disposed on the upper surface of the N-type drift region, the upper surface of the first dielectric layer, and its side; the emitter metal is isolated from the control electrode through the first dielectric layer. An N-type cutoff layer is disposed below the N-type drift region; The P-type collector region is located below the N-type cutoff layer; The collector metal is disposed below the P-type collector region; When the control electrode is floating, the potential of the first P-ring and the second P-ring increases as the potential of the collector metal increases, which in turn increases the potential of the floating trench and generates an electron channel in the first P-type well region on both sides of the floating trench, so that the voltage of the collector metal is clamped at a preset clamping voltage; when the control electrode is grounded, the potential of the first P-ring and the second P-ring is zero.

2. The power device with integrated overvoltage protection function according to claim 1, characterized in that, The preset clamping voltage is determined based on the doping concentration of the first P-type well region.

3. The power device with integrated overvoltage protection function according to claim 1, characterized in that, The N-type drift region further includes: a cell region and a transition region; one side of the overvoltage protection zone is connected to the cell region, and the other side is connected to the transition region; the trench further includes multiple dummy gate trenches and at least one true gate trench located in the cell region, and multiple dummy gate trenches located in the transition region; the dummy gate trenches in the cell region are close to the overvoltage protection zone; the dummy gate trenches in the transition region are divided into a group of dummy gate trenches close to the overvoltage protection zone and a group of dummy gate trenches far from the overvoltage protection zone; the N+ region is also disposed on both sides of the true gate trench, within the N-type drift region, and flush with the upper surface of the N-type drift region, and the other side of the N+ region is connected to the P+ region; the emitter metal is also disposed on the upper surface of the N-type drift region of the cell region and the transition region; the power device with integrated overvoltage protection function further includes: The second P-type well region is located on both sides of the true gate trench, on both sides of the false gate trench in the cell region, and on both sides of the false gate trench group near the overvoltage protection zone in the transition region. The third P-type ring is located below the dummy grid trench group in the transition zone, which is far from the overpressure protection zone, and below the P+ area of ​​the transition zone.

4. The power device with integrated overvoltage protection function according to claim 3, characterized in that, The doping concentration of the first P-type well region is less than that of the second P-type well region.

5. The power device with integrated overvoltage protection function according to claim 3, characterized in that, The area of ​​the overpressure protection zone is smaller than the area of ​​the cell region.

6. The power device with integrated overvoltage protection function according to claim 3, characterized in that, The N-type drift region further includes: a terminal region; one side of the terminal region is connected to the side of the transition region away from the overvoltage protection zone; the third P-type ring is also disposed in the N-type drift region in the terminal region that contacts the transition region and is flush with the upper surface of the N-type drift region, and the third P-type ring in the terminal region contacts the third P-type ring in the transition region; the power device with integrated overvoltage protection function further includes: The terminal stop ring is located within the N-type drift region of the terminal area and is flush with the upper surface of the N-type drift region; the terminal stop ring does not contact the third P-type ring; The second dielectric layer is disposed on the upper surface of the terminal area, excluding the terminal cutoff ring. A metal field plate is disposed on the upper surface of the second dielectric layer; A stop ring metal is disposed on the upper surface of the terminal stop ring; the side of the stop ring metal is in contact with the side of the second dielectric layer.

7. A method for manufacturing a power device with integrated overvoltage protection function, characterized in that, The method for manufacturing a power device with integrated overvoltage protection as described in any one of claims 1-6 includes: An N-type drift region is provided; the N-type drift region includes an overpressure protection zone; Etching is performed in the area within the N-type drift region and flush with the upper surface of the N-type drift region to form trenches; the trenches are arranged laterally at intervals and parallel to each other; the trenches include multiple dummy gate trenches and multiple floating trenches located in the overpressure protection zone, the dummy gate trenches are divided into two groups and arranged at both ends of the overpressure protection zone, and the floating trenches are arranged between the two groups of dummy gate trenches; P-type ions are injected into the overvoltage protection zone, between and below the dummy grid trenches in each group, to form a first P-type ring; P-type ions are injected into both sides of the floating trench to form a first P-type trap region; P-type ions are injected below the floating trench to form a second P-type ring; the second P-type rings are in contact with each other, and the second P-type rings at both ends are in contact with the first P-type ring, but not with the first P-type well region; An oxide layer is formed on the bottom and sidewalls of the trench; Polycrystalline silicon is deposited within the oxide layer inside the trench to form a polycrystalline silicon layer; the sides and bottom of the polycrystalline silicon layer are in contact with the oxide layer; N-type ions are injected into the areas on both sides of the floating trench, within the N-type drift region, and flush with the upper surface of the N-type drift region to form an N+ region; one side of the N+ region is connected to the side of the floating trench. P-type ions are injected into the areas on both sides of each trench, within the N-type drift region and flush with the upper surface of the N-type drift region, excluding the N+ region, to form the P+ region; A first dielectric layer is formed on the upper surface of the two sets of dummy grid trenches in the overvoltage protection zone; The first dielectric layer is etched, and metal is deposited on the upper surface of the P+ region between the dummy gate trenches in each group of the overvoltage protection zone to form a control electrode; Metal is deposited on the upper surface of the N-type drift region, the upper surface of the first dielectric layer, and the side region to form an emitter metal; the emitter metal is isolated from the control electrode through the first dielectric layer. N-type ions are injected below the N-type drift region to form an N-type cutoff layer; P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; Metal is deposited below the P-type collector region to form a collector metal; When the control electrode is floating, the potential of the first P-ring and the second P-ring increases as the potential of the collector metal increases, which in turn increases the potential of the floating trench and generates an electron channel in the first P-type well region on both sides of the floating trench, so that the voltage of the collector metal is clamped at a preset clamping voltage; when the control electrode is grounded, the potential of the first P-ring and the second P-ring is zero.

8. The method for manufacturing a power device with integrated overvoltage protection function according to claim 7, characterized in that, The preset clamping voltage is determined based on the doping concentration of the first P-type well region.

9. The method for manufacturing a power device with integrated overvoltage protection function according to claim 7, characterized in that, The N-type drift region further includes: a cell region and a transition region; one side of the overvoltage protection zone is connected to the cell region, and the other side is connected to the transition region; the trench further includes multiple dummy gate trenches and at least one true gate trench located in the cell region, and multiple dummy gate trenches located in the transition region; the dummy gate trenches in the cell region are close to the overvoltage protection zone; the dummy gate trenches in the transition region are divided into a group of dummy gate trenches close to the overvoltage protection zone and a group of dummy gate trenches far from the overvoltage protection zone; the N+ region is also disposed on both sides of the true gate trench, within the N-type drift region, and flush with the upper surface of the N-type drift region, and the other side of the N+ region is connected to the P+ region; the emitter metal is also disposed on the upper surface of the N-type drift region of the cell region and the transition region; the method further includes: P-type ions are injected on both sides of the true gate trench, both sides of the false gate trench in the cell region, and both sides of the false gate trench group near the overvoltage protection zone in the transition region to form a second P-type trap region. A third P-shaped ring is formed below the dummy grid trench group in the transition zone, away from the overpressure protection zone, and below the P+ zone of the transition zone.

10. The method for manufacturing a power device with integrated overvoltage protection function according to claim 9, characterized in that, The doping concentration of the first P-type well region is less than that of the second P-type well region.

11. The method for manufacturing a power device with integrated overvoltage protection function according to claim 9, characterized in that, The area of ​​the overpressure protection zone is smaller than the area of ​​the cell region.

12. The method for manufacturing a power device with integrated overvoltage protection function according to claim 9, characterized in that, The N-type drift region further includes: a terminal region; one side of the terminal region is connected to the side of the transition region away from the overpressure protection zone; the third P-type ring is also disposed in the N-type drift region of the terminal region that contacts the transition region and is flush with the upper surface of the N-type drift region, and the third P-type ring in the terminal region contacts the third P-type ring in the transition region; the method further includes: A terminal stop ring is formed in the N-type drift region of the terminal area and in a region flush with the upper surface of the N-type drift region; the terminal stop ring does not contact the third P-type ring; A second dielectric layer is formed on the upper surface of the terminal region, excluding the terminal stop ring; Metal is deposited on the upper surface of the second dielectric layer to form a metal field plate; Metal is deposited on the upper surface of the terminal stop ring, forming the stop ring metal; the side of the stop ring metal contacts the side of the second dielectric layer.

13. A chip, characterized in that, Including power devices with integrated overvoltage protection as described in any one of claims 1-6.

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