A trench power device

Abstract

The application discloses a trench power device, which comprises a semiconductor layer, a trench gate, a well region, a source region, a protective layer, a conductive channel, a well contact region and a super junction column. The protective layer is located below the trench gate. The conductive channel is located in the protective layer below the trench gate. The well contact region is located in the source region and the well region and extends from the upper surface of the source region to the well region. The super junction column is located below the well contact region and connected with the well contact region. The trench power device provided by the application integrates the super junction structure and the electric field balance structure, expands the one-dimensional electric field cell structure of the traditional structure into a two-dimensional structure, and thus simultaneously obtains the cell design of low specific on-resistance and high withstand voltage capacity.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a trench power device. Background Technology

[0002] Silicon carbide (SiC) power devices, due to their superior material properties such as high voltage withstand, low on-resistance, and high temperature resistance, have been widely used in industrial control, power supplies, automotive electronics, and aerospace. However, the cost of SiC wafers is currently high. Increasing the number of devices on a single wafer can effectively reduce the production cost. But increasing the number of devices means reducing the device area. In other words, under the same voltage withstand conditions, the specific on-resistance of the device needs to be smaller. Existing SiC power devices, whether planar gate structure or trench gate structure, have already approached the theoretical limit of silicon carbide material in terms of specific on-resistance. Summary of the Invention

[0003] This application provides a trench power device that integrates a superjunction structure and an electric field balance structure, extending the traditional one-dimensional electric field cell structure into a two-dimensional structure, thereby simultaneously achieving a cell design with low specific on-resistance and high withstand voltage capability.

[0004] According to an embodiment of the present invention, a trench power device is provided, comprising a semiconductor layer, a trench gate, a well region, a source region, a guard layer, a conductive channel, a well contact region, and a superjunction pillar. The semiconductor layer includes a substrate and an epitaxial layer. The trench gate extends from the upper surface of the semiconductor layer into the epitaxial layer. The well region is located in the epitaxial layer between the trench gates and is adjacent to the sidewalls of the trench gate. The source region is located in the well region between the trench gates and is adjacent to the sidewalls of the trench gate. The guard layer is located below the trench gate and maintains a certain distance from the bottom of the trench gate. The conductive channel is located in the guard layer below the trench gate and has a top surface higher than the upper surface of the guard layer and a bottom surface lower than the lower surface of the guard layer. The well contact region is located within the source region and the well region, extending at least from the upper surface of the source region into the well region. The superjunction pillar is located in the epitaxial layer below the well contact region and is connected to the well contact region.

[0005] In one embodiment, the bottom of the well contact region is located within the well region, and the superjunction pillar is connected to the bottom of the well contact region.

[0006] In one embodiment, the trap contact area extends downward to the upper surface of the protective layer, the superstructure is in contact with the lower surface of the protective layer, and the trap contact area and the superstructure are connected through the protective layer.

[0007] In one embodiment, the superstructure column includes at least two parts, the first part being in contact with the protective layer, the second part being located below the first part, and the width of the first part being greater than the width of the second part.

[0008] In one embodiment, on the first side of the trench gate, the trap contact area extends downward to the upper surface of the protective layer; on the second side of the trench gate, the bottom of the trap contact area is located in the trap area; and the superstructure pillar is in contact with the lower surface of the protective layer.

[0009] In one embodiment, the well contact area is located on both sides of the trench gate, and on each side of the trench gate, the well contact area is discontinuously distributed along the length of the trench gate.

[0010] In one embodiment, the trench power device further includes a connection region extending downward from the upper surface of the semiconductor layer until it connects to the protective layer. The connection region is strip-shaped in a direction perpendicular to the length of the trench gate and is distributed between adjacent well contact regions.

[0011] In one embodiment, along the length of the trench gate, the well contact regions between adjacent trench gates alternately connect to adjacent trench gates. The trench power device further includes a connection region distributed below the well contact region, covered by the well contact region, and extending downward from the bottom of the well contact region until it connects to the protective layer.

[0012] In one embodiment, at least one trench gate is distributed between adjacent well contact areas in a direction perpendicular to the length of the trench gate. Attached Figure Description

[0013] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:

[0014] Figure 1 This is a cross-sectional schematic diagram of a trench power device 100 according to an embodiment of this application;

[0015] Figure 2 This is a schematic planar layout of the upper surface 101a of the semiconductor layer of a trench power device 100 according to an embodiment of this application;

[0016] Figure 3 This is a schematic cross-sectional view of a trench power device 300 according to an embodiment of this application;

[0017] Figure 4 This is a schematic cross-sectional view of a trench power device 400 according to an embodiment of this application;

[0018] Figure 5 This is a cross-sectional schematic diagram of a trench power device 500 according to an embodiment of this application;

[0019] Figure 6 This is a schematic cross-sectional view of a trench power device 600 according to an embodiment of this application;

[0020] Figure 7 This is another cross-sectional view of a trench power device 600 according to an embodiment of this application;

[0021] Figure 8 This is a schematic planar layout of the upper surface 601a of the semiconductor layer of a trench power device 600 according to an embodiment of this application;

[0022] Figure 9 This is a schematic cross-sectional view of a trench power device 900 according to an embodiment of this application;

[0023] Figure 10 This is a schematic planar layout of the upper surface 901a of the semiconductor layer of a trench power device 900 according to an embodiment of this application;

[0024] Figure 11 This is a schematic cross-sectional view of a trench power device 1100 according to an embodiment of this application;

[0025] Figure 12 This is a cross-sectional schematic diagram of a trench power device 1200 according to an embodiment of this application. Detailed Implementation

[0026] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0027] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0028] The terms “having,” “comprising,” “including,” “include,” etc., are open-ended, and these terms indicate the presence of the said structure, element, or feature, but do not exclude additional elements or features.

[0029] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0030] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0031] Figure 1 This is a schematic cross-sectional view of a trench power device 100 according to an embodiment of this application. Figure 1 As shown, the trench power device 100 includes a semiconductor layer 101, a trench gate 104, a well region 105, a source region 106, a well contact region 107, a superjunction pillar 108, a protective layer 109, and a conductive channel 110. The semiconductor layer 101 includes a substrate 102 and an epitaxial layer 103 located on the substrate. The trench gate 104 extends inward from the upper surface 101a of the semiconductor layer 101 (i.e., along the Z direction) and includes a gate electrode 112 and an insulating layer 111 surrounding the gate electrode 112. The well region 105 is located on the upper surface of the semiconductor layer 101, extends inward from the upper surface 101a of the semiconductor layer into the epitaxial layer 103 (along the Z direction), is located between the trench gates 104, and is adjacent to the sidewalls of the trench gates 104, wherein the bottom of the well region 105 is higher than the bottom of the trench gate 104. Source region 106, located on the upper surface of well region 105, extends from the upper surface 101a of semiconductor layer into well region 105 (along the Z direction), situated within well region 105 between trench gates 104, and adjacent to the sidewalls of trench gate 104. Guard layer 109 is located below trench gate 104, maintaining a certain distance from the bottom of trench gate 104. Conductive channel 110 is located in guard layer 109 below trench gate 104, and has a top surface higher than the upper surface 109a of guard layer 109 and a bottom surface lower than the lower surface 109b of guard layer 109. Well contact region 107 is located within source region 106 and well region 105, extending from the upper surface of source region 106, i.e., the upper surface 101a of semiconductor layer 101, into well region 105. Superjunction pillar 108 is located below well contact region 107 and connected to well contact region 107.

[0032] exist Figure 1In this embodiment, the conductive channel 110 provides a current path, forming a current channel from the source region 106 to the substrate 102. The top surface of the conductive channel 110 is higher than the upper surface 109a of the protective layer 109, and the bottom surface is lower than the lower surface 109b of the protective layer 109, thereby connecting the upper and lower portions of the epitaxial layer 103 isolated by the protective layer 109. In some embodiments, the epitaxial layer 103 has a uniform doping concentration. In some embodiments, the portion of the epitaxial layer 103 above the protective layer 109 has a higher doping concentration than the portion below the protective layer 109 to provide a lower specific on-resistance.

[0033] exist Figure 1 In this embodiment, the bottom of the well contact region 107 is located within the well region 105. The superjunction pillar 108 is connected to the bottom of the well contact region 107 and extends downward (along the Z direction) through the protective layer 109 until it reaches a depth in the epitaxial layer 103, close to the substrate 102. The extension depth of the superjunction pillar 108 is related to the withstand voltage requirements and process, and can be set according to application needs.

[0034] In one embodiment, semiconductor layer 101 comprises silicon carbide (SiC) material. In other embodiments, semiconductor layer 101 may also comprise other wide bandgap materials, such as gallium nitride (GaN).

[0035] Substrate 102, epitaxial layer 103, source region 106, and conductive channel 110 have a first doping type, while well region 105, well contact region 107, superjunction pillar 108, and guard layer 109 have a second doping type. In some embodiments, the first doping type is N-type, and the second doping type is P-type. In other embodiments, the first doping type is P-type, and the second doping type is N-type. In some embodiments, the doping concentration of substrate layer 102 is greater than the doping concentration of epitaxial layer 103, and the doping concentration of source region 106 is greater than the doping concentration of substrate layer 102. In some embodiments, the doping concentration of guard layer 109 is greater than the doping concentration of well region 105, and the doping concentration of well contact region 107 is greater than the doping concentration of well region 105.

[0036] Figure 2 This is a schematic planar layout of the upper surface 101a of the semiconductor layer of a trench power device 100 according to an embodiment of this application. Figure 1 The cross-sectional view corresponds to Figure 2 The cross-section at line AA' shown. Figure 2As shown, on the upper surface 101a of the semiconductor layer, a trench gate 104 extends along the Y direction, and well contact regions 107 are distributed on both sides of the trench gate 104. Along the length direction of the trench gate 104, i.e., the Y direction, the well contact regions 107 are discontinuously distributed on each side of the trench gate 104. That is, the well contact regions 107 are discontinuously distributed in the Y direction, and adjacent well contact regions 107 maintain a certain distance, having a spacing.

[0037] In one embodiment, the distribution of superstructure columns 108 is continuous in the Y direction.

[0038] The physical properties of SiC material cause the gate oxide structure of trench SiC devices to withstand high electric fields, which can easily lead to reliability issues. The trench power device 100 of this application uses a protective layer 109 to shield the electric field and protect the bottom of the trench gate 104, preventing electric field breakdown. Furthermore, in the epitaxial layer 103, superjunction pillar structures are introduced on both sides of the trench gate 104 to further reduce the electric field at the bottom corners of the trench gate 104, thus reducing the risk of breakdown of the insulating layer 111.

[0039] The trench power device 100 of this application embodiment has a superjunction pillar 108 directly connected to the well contact area 107. It can be formed by trenching and filling, or it can be matched with a multiple injection process. It has excellent superjunction process compatibility and good manufacturability.

[0040] Figure 3 This is a schematic cross-sectional view of a trench power device 300 according to an embodiment of this application. Figure 3 As shown, the trench power device 300 includes a semiconductor layer 101, a trench gate 104, a well region 105, a source region 106, a well contact region 307, a superjunction pillar 308, a protective layer 109, and a conductive channel 110. The trench power device 300 and... Figure 1 The trench power device 100 shown has a similar structure, but differs in that, in trench power device 100, the superjunction pillar 108 is directly connected to the well contact region 107 and has the same potential. In trench power device 300, the well contact region 307 is located within the source region 106 and the well region 105, extending downwards from the upper surface of the source region 106 (i.e., the upper surface 101a of the semiconductor layer 101), through the source region 106 and the well region 105, until it connects to the guard layer 109. The superjunction pillar 308 is located below the guard layer 109, extending downwards from the lower surface 109b of the guard layer 109 and connecting to the well contact region 307 through the guard layer 109. Similarly, in both trench power device 300 and trench power device 100, the well contact region and the superjunction pillar are connected to the same potential, such as the source potential.

[0041] Figure 3The trench power device 300 of the embodiment can freely adjust the distance between the trench gate 104 and the well contact area 307, so that the structure has a larger conduction window, thereby reducing the on-resistance of the device.

[0042] Figure 4 This is a schematic cross-sectional view of a trench power device 400 according to an embodiment of this application. Figure 4 As shown, the trench power device 400 includes a semiconductor layer 101, a trench gate 104, a well region 105, a source region 106, a well contact region 307, a superjunction pillar 408, a protective layer 109, and a conductive channel 110. The trench power device 400 and... Figure 3 The trench power device 300 shown has a similar structure, but differs in that the superjunction pillar 308 in the trench power device 300 has a uniform width from top to bottom, while in the trench power device 400, the superjunction pillar 408 includes at least two portions 4081 and 4082. The first portion 4081 is in contact with the protective layer 109, and the second portion 4082 is located below the first portion 4081, with the width w1 of the first portion 4081 being greater than the width w2 of the second portion 4082. In some embodiments, the first portion 4081 and the second portion 4082 of the superjunction pillar 408 have the same doping concentration. In some embodiments, the first portion 4081 and the second portion 4082 of the superjunction pillar 408 have different doping concentrations.

[0043] Figure 4 The trench power device 400 of the embodiment can modulate the breakdown position of the trench power device 400 by adjusting the width of different parts of the superjunction pillar 408 to construct a stepped structure, and / or by adjusting the doping concentration of different parts of the superjunction pillar 408, thereby affecting the two-dimensional charge balance capability of the epitaxial layer of the superjunction structure and improving the device performance.

[0044] Figure 5 This is a schematic cross-sectional view of a trench power device 500 according to an embodiment of this application. Figure 5 As shown, the trench power device 500 includes a semiconductor layer 101, a trench gate 104, a well region 105, a source region 106, well contact regions 307 and 507, a superjunction pillar 308, a protective layer 109, and a conductive channel 110. The trench power device 500 and... Figure 3The trench power device 300 shown has a similar structure, except that the well contact regions 307 and 507 on both sides of the trench gate 104 have different depths. Specifically, on the first side of the trench gate 104, the well contact region 307 extends downward to the upper surface 109a of the protective layer 109, and the superjunction pillar 308 corresponding to the well contact region 307 extends downward from the lower surface 109b of the protective layer 109. The well contact region 307 and the superjunction pillar 308 are connected through the protective layer 109. On the second side of the trench gate 104, the bottom of the well contact region 507 is located in the well region 105, and the superjunction pillar 308 corresponding to the well contact region 507 extends downward from the lower surface 109b of the protective layer 109. The superjunction pillar 308 is also connected to the well contact region 307 through the protective layer 109, and they are both connected to the same potential.

[0045] Figure 5 The trench power device 500 of the embodiment introduces a structure of both a well contact region 307 and a well contact region 507, which are arranged alternately or interspersed in a certain pattern. This reduces the high resistance region caused by the close proximity between the trench gate 104 and the well contact region 307 to a certain extent, and further reduces the device resistance.

[0046] Figure 6 This is a cross-sectional schematic diagram of a trench power device 600 according to an embodiment of this application. Figure 7 This is another cross-sectional view of a trench power device 600 according to an embodiment of this application. Figure 8 This is a schematic planar layout of the upper surface 601a of the semiconductor layer of a trench power device 600 according to an embodiment of this application. Figure 6 The cross-sectional view corresponds to Figure 8 The cross section at line BB' shown. Figure 7 The cross-sectional view corresponds to Figure 8 The cross-section at line CC' is shown. Figure 6 , Figure 7 and Figure 8 As shown, the trench power device 600 includes a semiconductor layer 101, a trench gate 104, a well region 105, a source region 106, a well contact region 607, a connection region 613, a superjunction pillar 308, a protective layer 109, and a conductive channel 110.

[0047] like Figure 6 As shown, the bottom of the well contact region 607 is located in the well region 105, and the superstructure pillar 308 extends downward from the lower surface 109b of the protective layer 109. The superstructure pillar 308 and the well contact region 607 are not directly connected. Figure 7 As shown, the connection region 613 extends downward from the upper surface 601a of the semiconductor layer 101 until it connects with the protective layer 109. Figure 8As shown, on the upper surface 601a of the semiconductor layer 101, in the direction perpendicular to the length of the trench gate 104, i.e., the X direction, the connection region 613 is strip-shaped and distributed between the gaps of adjacent well contact regions 607. In the trench power device 600, the superjunction pillar 308 is connected to the connection region 613 through a protective layer 109, and both the connection region 613 and the well contact region 607 are exposed on the upper surface 601a of the semiconductor layer. In one embodiment, the connection region 613 and the well contact region 607 are connected to the source potential together through a source metal layer covering the upper surface 601a of the semiconductor layer.

[0048] The trench power device 600 uses a connection region 613 to connect the protective layer 109 and the overlying metal layer structure (e.g., the source metal layer) in the third dimension, which can further reduce the electric field of the gate oxide at the bottom of the trench, thereby improving the reliability of the device.

[0049] In one embodiment, the width of the connection region 613 is less than 1.0 μm. In some embodiments, the channel effect implantation method is used to reduce the thickness of the implantation mask, thereby achieving a lower lithography linewidth with a simpler process. In this way, the width w3 of the connection region 613 can be less than 1.0 μm, thus reducing the impact on the device's on-resistance. The connection region 613 in this embodiment serves to connect the protective layer 109 and the surface contact, therefore it is insensitive to impurity distribution, creating conditions for using the channel implantation effect.

[0050] Figure 9 This is a cross-sectional schematic diagram of a trench power device 900 according to an embodiment of this application. Figure 10 This is a schematic planar layout of the upper surface 901a of the semiconductor layer of a trench power device 900 according to an embodiment of this application. Figure 9 The cross-sectional view corresponds to Figure 10 The cross-section at line DD' shown. Figure 9 and Figure 10 As shown, the trench power device 900 includes a semiconductor layer 101, a trench gate 104, a well region 105, a source region 106, a well contact region 907, a connection region 913, a superjunction pillar 308, a protective layer 109, and a conductive channel 110.

[0051] like Figure 9 As shown, the well contact area 907 is distributed on both sides of the trench grid 104, with its bottom located in the well area 105. Its sidewalls are connected to the sidewalls of the trench grid 104. The connecting area 913 is located below the well contact area 907, covered by the well contact area 907, and extends downwards from the bottom of the well contact area 907 until it connects with the protective layer 109. The superstructure pillar 308 extends downwards from the lower surface 109b of the protective layer 109. Figure 10As shown, on the upper surface 901a of the semiconductor layer, along the length direction of the trench gate 104, i.e. the Y direction, the well contact regions 907 on both sides of the adjacent trench gate 104 are staggered.

[0052] exist Figure 9 and Figure 10 In this embodiment, the superstructure pillar 308 is connected to the connection region 913 through the protective layer 109, and the connection region 913 is directly connected to the well contact region 907, thereby fixing the potentials of the superstructure pillar 308, the protective layer 109, the connection region 913 and the well contact region 907.

[0053] The well contact regions 907 of the trench power device 900 are distributed above the connection region 913 and are staggered along adjacent trench gates, which can better reduce the electric field at the bottom of the trench gate and improve the reliability of the device. Furthermore, the layout of the well contact regions 907 can improve the surge protection and UIS (Unclamped Inductive Switching) capability of the device.

[0054] In the above embodiments, a trench grid is distributed between adjacent well contact areas in the X direction. In other embodiments of this application, multiple trench grids may be distributed between adjacent well contact areas.

[0055] Figure 11 This is a schematic cross-sectional view of a trench power device 1100 according to an embodiment of this application. Figure 11 As shown, with Figure 3 Compared to the previous embodiment, the trench power device 1100 has two trench gates 104 distributed between adjacent well contact areas 307, thereby further increasing the current carrying capacity of the device.

[0056] exist Figure 9 In this embodiment, in the Z direction, each superstructure pillar 308 corresponds to a trap contact region 307 above it. In other embodiments, the superstructure pillars 308 and trap contact regions 307 may not correspond one-to-one.

[0057] Figure 12 This is a schematic cross-sectional view of a trench power device 1200 according to an embodiment of this application. Figure 11 Compared to the previous embodiment, the superjunction pillars of the trench power device 1200 are equidistantly distributed in the direction perpendicular to the trench gate length, i.e., in the X direction, and at least one superjunction pillar 1208 is distributed in the lower epitaxial layer between the two conduction channels 110 to further uniformly distribute the electric field and improve the reliability of the device.

[0058] The trench power devices 1100 and 1200 are merely illustrative examples of embodiments in this application, showing that one or more trench gates may be present between adjacent well contact areas. It should be understood that structures with multiple trench gates between adjacent well contact areas can also be applied. Figures 1-10 In the example.

[0059] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A trench power device, comprising: Semiconductor layer, including substrate and epitaxial layer; The trench gate extends from the upper surface of the semiconductor layer into the interior of the epitaxial layer. The well region is located in the epitaxial layer between the trench gates and is adjacent to the sidewall of the trench gate; The source region is located in the well region between the trench gates and is adjacent to the sidewall of the trench gates; The protective layer is located below the trench grid and is kept at a certain distance from the bottom of the trench grid. The conductive channel is located in the protective layer below the trench gate and has a top surface that is higher than the upper surface of the protective layer and a bottom surface that is lower than the lower surface of the protective layer. The well contact region is located within the source region and the well region, extending from the upper surface of the source region to at least the well region. as well as The superjunction pillar is located in the epitaxial layer below the well contact region and is connected to the well contact region.

2. The trench power device of claim 1, wherein the substrate, epitaxial layer, source region and conductive channel have a first doping type, and the well region, well contact region, protective layer and superjunction pillar have a second doping type.

3. The trench power device as described in claim 1, wherein, The bottom of the well contact area is located within the well area, and the superjunction pillar is connected to the bottom of the well contact area.

4. The trench power device as described in claim 1, wherein, The trap contact area extends downward to the upper surface of the protective layer, the superstructure pillar is in contact with the lower surface of the protective layer, and the trap contact area and the superstructure pillar are connected through the protective layer.

5. The trench power device as described in claim 4, wherein, The superstructure column comprises at least two parts, the first part being in contact with the protective layer, the second part being located below the first part, and the width of the first part being greater than the width of the second part.

6. The trench power device as claimed in claim 1, wherein, On the first side of the trench grid, the trap contact area extends downward to the upper surface of the protective layer; as well as On the second side of the trench grid, the bottom of the well contact area is located in the well area; The superstructure column is in contact with the lower surface of the protective layer.

7. The trench power device according to any one of claims 1-6, wherein, The trap contact area is located on both sides of the trench grid, and on each side of the trench grid, the trap contact area is discontinuously distributed along the length of the trench grid.

8. The trench power device of claim 7, further comprising: The connection region extends downward from the upper surface of the semiconductor layer until it connects with the protective layer. In a direction perpendicular to the length of the trench gate, the connection region is strip-shaped and distributed in the gaps between adjacent well contact regions.

9. The trench power device as claimed in claim 7, wherein, Along the length of the trench gate, the sink contact region between adjacent trench gates alternately contacts the adjacent trench gate, and the trench power device further includes: The connecting area is located below the trap contact area, is covered by the trap contact area, and extends downward from the bottom of the trap contact area until it connects with the protective layer.

10. The trench power device as described in claims 1-6, wherein, At least one trench gate is distributed between adjacent well contact areas in a direction perpendicular to the length of the trench gate.

11. The trench power device of claim 10, wherein, In a direction perpendicular to the upper surface of the semiconductor layer, each superjunction pillar is arranged corresponding to a well contact region above it.

12. The trench power device as claimed in claim 10, wherein, The superstructure pillars are equidistantly distributed in a direction perpendicular to the length of the trench gate, and at least one superstructure pillar is distributed in the epitaxial layer below the two conductive channels.

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