High voltage resistant terminal structure and method of manufacturing the same

Abstract

The application provides a high-voltage-resistant terminal structure and a manufacturing method thereof. The high-voltage-resistant terminal structure comprises an N-type substrate, an N-type drift layer epitaxially grown on the N-type substrate, a field oxide layer formed on the N-type drift layer, a polysilicon spiral field plate formed on the field oxide layer, an interlayer dielectric layer formed on the polysilicon spiral field plate, and a cathode and an anode formed on the interlayer dielectric layer. A transversely variable-doped P-type region is arranged in the N-type drift layer, and a wire of the polysilicon spiral field plate extends outward in a spiral shape. The application aims to overcome the existing defects and provide a high-voltage-resistant terminal structure and a manufacturing method thereof, so as to improve the breakdown voltage of the terminal structure and reduce the process complexity of the hybrid junction terminal.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a high-voltage resistant terminal structure and its manufacturing method. Background Technology

[0002] The ability of high-voltage power semiconductor devices to block high voltage is primarily limited by the breakdown voltage of the PN junction at the edge cells. For example, the Schottky junction edge of an SBD, and the PN junction edge (or gate edge) of a MOSFET, experience a much stronger electric field than the device interior due to the junction curvature effect when subjected to reverse high voltage. This excessively strong local electric field can cause the device to break down prematurely, far before reaching its theoretical breakdown voltage. Therefore, the primary goal of high-voltage termination design is to smooth and disperse this electric field spike through structural optimization, thereby improving the actual breakdown voltage of the device.

[0003] Currently, extension structures are typically placed at the edge of the main junction to alleviate electric field concentration. These extension structures widen the depletion region of the main junction outward, thereby reducing the electric field strength within it or lowering the peak electric field at the edge of the main junction, ultimately increasing the breakdown voltage. Examples include junction termination extension structures (JTE), field-limiting ring structures (FLR), deep trench termination structures (DT2), field plates (FP, FFP), or lateral variable doping structures (VLD). However, these structures are generally large in size. For example, for devices with a breakdown voltage of around 1200V, the size of the junction termination protection structure is approximately 180μm, which also increases the on-resistance of the device. Generally, to reduce the device size while maintaining the breakdown voltage, existing junction termination extension structures can be combined. However, the fabrication process for hybrid junctions is complex and costly. Summary of the Invention

[0004] The purpose of this invention is to provide a high-voltage resistant terminal structure and its manufacturing method to solve the technical problems of easy breakdown and complex manufacturing process of existing high-voltage power semiconductor devices.

[0005] To solve the above-mentioned technical problems, the present invention provides a high-voltage resistant terminal structure, the high-voltage resistant terminal structure comprising: N-type substrate; An N-type drift layer epitaxially grown on the N-type substrate; A field oxygen layer formed on the N-type drift layer; A polycrystalline silicon spiral field plate formed on the field oxygen layer; Interlayer dielectric layer formed on the polycrystalline silicon spiral field plate; and The cathode and anode are formed on the interlayer dielectric layer; The N-type drift layer contains a laterally doped P-type region, and the wiring of the polycrystalline silicon spiral field plate extends outward in a spiral shape. The first end of the wiring is connected to the anode, and the last end of the wiring is connected to the cathode.

[0006] Optionally, the wiring is configured as an equidistant planar spiral structure, with both the beginning and end being rectangular blocks arranged on the same straight line.

[0007] Optionally, the doping concentration of the P-type region gradually decreases from the center to the edge.

[0008] Optionally, a P+ ohmic contact area is provided on the top of the P-type region, and the P+ ohmic contact area is connected to the anode; an N+ ohmic contact area is provided on the top of the N-type drift layer, and the N+ ohmic contact area is connected to the cathode.

[0009] Optionally, the substrate is an n+ heavily doped silicon substrate, the N-type drift layer is an n- lightly doped drift layer, the N-type drift layer is epitaxially grown on the front side of the substrate, and the thickness of the N-type drift layer and the field oxide layer is set according to the terminal withstand voltage level.

[0010] Optionally, the thickness of the substrate is in the range of 300-500 μm; the thickness of the N-type drift layer is in the range of 30-50 μm, and the resistivity is in the range of 10-50 Ω·cm; the thickness of the field oxide layer is in the range of 0.8-1.5 μm.

[0011] Optionally, the interlayer dielectric layer is made of phosphosilicate glass or borosilicate glass, with a thickness ranging from 1.0 to 1.5 μm.

[0012] Optionally, a metal layer may also be included, the metal layer being disposed on the back side of the substrate.

[0013] Optionally, the metal layer, the cathode, and the anode are all made of aluminum-silicon alloy or aluminum-silicon-copper alloy, the metal layer thickness of the cathode and the anode is 3-5 μm, and the metal layer thickness on the back side of the substrate is 1-2 μm.

[0014] Optionally, the high-voltage termination structure is applied to Schottky barrier diodes and metal-oxide-semiconductor field-effect transistors.

[0015] Accordingly, the present invention also provides a method for manufacturing a high-voltage resistant terminal structure, the method comprising: S1: A substrate is provided, wherein the substrate is an n+ heavily doped silicon substrate; S2: Perform epitaxial growth on the substrate to form an n-low doped drift layer; S3: Perform the first ion implantation on the n-low doped drift layer to form a P-type region; S4: A field oxygen layer is formed on the N-type drift layer; S5: A polycrystalline silicon spiral field plate is formed on the field oxide layer, and the wiring of the polycrystalline silicon spiral field plate extends outward in a spiral shape. S6: Perform a second ion implantation on the n-low doped drift layer corresponding to the cathode to form an N+ ohmic contact region; S7: A third ion implantation is performed in the P-type region corresponding to the anode to form a P+ ohmic contact region; S8: An interlayer dielectric layer is formed on the N+ ohmic contact region, the P+ ohmic contact region, the polycrystalline silicon spiral field plate, and the exposed field oxide layer. S9: The interlayer dielectric layer is etched to form a contact hole, the contact hole penetrating the interlayer dielectric layer and exposing the N+ ohmic contact area, the P+ ohmic contact area and the beginning and end of the wiring of the polysilicon spiral field plate; S10: A metal electrode is formed on the interlayer dielectric layer, wherein the metal electrode connected to the beginning of the wiring is the anode, and the metal electrode connected to the end of the wiring is the cathode.

[0016] Optionally, in step S3, a first ion implantation is performed using a first mask. The first mask has N concentric annular openings, where N is a natural number. The impurity for ion implantation is boron or boron difluoride, the implantation energy is 80-100 keV, and the implantation dose is arranged in window order from 5 × 10⁻⁶. 13 cm -2 Decrease to 5×10 11 cm -2 .

[0017] Optionally, in step S4, the formation process of the field oxygen layer includes a first dry oxidation, a wet oxidation, and a second dry oxidation, during which the temperature is controlled at 1000-1100℃.

[0018] Optionally, before step S6 and after step S5, the method further includes: etching the field oxide layer using a second mask to remove the field oxide layer at the corresponding positions of the cathode and the anode.

[0019] Optionally, step S5 includes: A polycrystalline silicon layer is formed using a low-pressure chemical vapor deposition process, with the temperature controlled at 580-650℃. The polysilicon layer is etched using a third mask to form wiring that extends spirally from the inside out.

[0020] Optionally, in step S6, a second ion implantation is performed using a fourth mask. The impurity for ion implantation is phosphorus or arsenic, the implantation energy is 80-150 keV, and the implantation dose is 1×10⁻⁶.15 -5×10 15 cm -2 The annealing temperature after ion implantation is controlled at 850-950℃ for 30 minutes.

[0021] Optionally, in step S7, a third ion implantation is performed using a fifth mask. The impurity implanted is boron or boron difluoride, the implantation energy is 40-80 keV, and the implantation dose is 1×10⁻⁶. 15 -5×10 15 cm -2 The annealing temperature after ion implantation is controlled at 850-900℃ for 30 minutes.

[0022] Optionally, step S8 includes: An interlayer dielectric layer is formed using atmospheric pressure chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition processes. The interlayer dielectric layer is planarized by a reflow process, wherein the temperature of the reflow process is controlled at 850-900℃.

[0023] Optionally, in step S9, a sixth mask is used to etch contact holes, the contact holes including a circular hole array and a strip hole array, the position of the circular hole array corresponding to the cathode, and the position of the strip hole array corresponding to the anode.

[0024] Optionally, step S10 includes: The first sputtering process is performed using the seventh mask to form the first metal layer on the front side of the device. Thinning treatment is performed on the back side of the device; and A second sputtering process is performed using a seventh mask to form a second metal layer on the back side of the thinned device.

[0025] Compared with the prior art, the present invention has the following beneficial effects: 1) The resistive field plate is designed as a polycrystalline silicon spiral field plate, so that the polycrystalline silicon ring starts from the edge of the anode and extends spirally to the outer end. Each ring is coupled to the silicon capacitor below through the field oxide layer to form an RC voltage divider network. The anode potential gradually decreases along the spiral extension direction, making the surface electric field distribution more uniform and effectively avoiding local breakdown problems. 2) The production of high-voltage resistant terminal structures does not require additional photomasks or other process steps, which helps to simplify the process and reduce costs. Attached Figure Description

[0026] Figure 1 This is a cross-sectional view corresponding to step two in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention; Figure 2This is a cross-sectional view corresponding to step three in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention; Figure 3 This is a cross-sectional view corresponding to step four in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention; Figure 4 This is a cross-sectional view corresponding to step five in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention; Figure 5 This is a cross-sectional view of step seven in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention; Figure 6 This is a cross-sectional view corresponding to step eight in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention; Figure 7 This is a cross-sectional view of step ten in the manufacturing method of the high-voltage terminal structure according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the high-voltage terminal structure after back-side metallization according to an embodiment of the present invention; Figure 9 This is a top view of a polycrystalline silicon spiral field plate according to an embodiment of the present invention; Figure 10 This is a comparison diagram of the first simulation parameters between the high-voltage terminal structure of this invention and a conventional terminal. Figure 11 This is a comparison diagram of the second simulation parameters between the high-voltage terminal structure of this invention and a conventional terminal. Figure 12 This is an electric field distribution diagram of the high-voltage resistant terminal structure according to an embodiment of the present invention; Figure 13 This is a diagram showing the electric field distribution of a conventional terminal. Figure 14 for Figure 12 and Figure 13 Comparison of electric field intensities corresponding to the AA' section; Figure 15 for Figure 12 and Figure 13 Comparison of electric field strength at the BB' section. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, so that the characteristics and advantages of the present invention will become more apparent.

[0029] Please refer to Figure 1-9 This is a schematic diagram of the high-voltage resistant terminal structure according to an embodiment of the present invention. Figure 1-9 As shown, the high-voltage terminal structure includes: an N-type substrate 1; an N-type drift layer 2 epitaxially grown on the N-type substrate 1; a field oxide layer 4 formed on the N-type drift layer 2; a polycrystalline silicon spiral field plate 5 formed on the field oxide layer 4; an interlayer dielectric layer 8 formed on the polycrystalline silicon spiral field plate 5; and a cathode 9a and an anode 9b formed on the interlayer dielectric layer 8; wherein, the N-type drift layer 2 is provided with a laterally doped P-type region 3, the wiring of the polycrystalline silicon spiral field plate 5 extends spirally outward, the first end of the wiring is connected to the anode 9b, and the last end of the wiring is connected to the cathode 9a.

[0030] Specifically, the polycrystalline silicon spiral field plate 5 is a resistive field plate (PRFP), with the first end of its wiring serving as the anode connection point and the last end as the cathode connection point. The wiring (i.e., the polycrystalline silicon rings) starts from the edge of the anode and spirals outwards towards the terminal. Each ring is coupled to the underlying silicon capacitor through the field oxide layer 4. The resistance (R) between the polycrystalline silicon rings and the capacitance (C) between the ring and the substrate form an RC voltage divider network, gradually extending the anode potential to the terminal surface. Under reverse bias, the potential gradually decreases from the anode along the spiral extension direction, resulting in a uniform distribution of the surface electric field and preventing localized breakdown.

[0031] like Figure 9 As shown, in this embodiment, the wiring of the polycrystalline silicon spiral field plate 5 is configured as an equidistant planar spiral structure, which is a continuous line from beginning to end, with the curvature gradually decreasing from the inside to the outside, and the spacing between any two adjacent turns is equal. Preferably, the beginning and end of the wiring are both rectangular blocks, and are arranged on the same straight line.

[0032] Figures 1 to 8 The cross-sectional views shown all correspond to Figure 9 The N-N' line. For example... Figure 8 As shown, the P-type region 3 in the N-type drift layer 2 serves as a junction termination extension (JTE), which can alleviate the concentration of electric field at the junction edge. A P+ ohmic contact region 7 is provided on top of the P-type region 3, serving as a current inflow channel and connected to the anode 9b. An N+ ohmic contact region 6 is provided on top of the N-type drift layer 2, serving as a current outflow channel and connected to the cathode 9a. The ohmic contact region reduces contact resistance, ensuring that external current can be injected into or extracted from the device with almost no loss.

[0033] In this embodiment, the substrate 1 is an n+ heavily doped silicon substrate, the N-type drift layer 2 is an n- lightly doped drift layer, the N-type drift layer 2 is epitaxially grown on the front side of the substrate 1, and the thickness of the N-type drift layer 2 and the field oxide layer 4 is set according to the terminal withstand voltage level.

[0034] The field oxygen layer 4 covers the entire surface of the N-type drift layer 2, including the surface of the P-type region 3. As an insulating medium located between the drift layer and the polycrystalline silicon spiral field plate 5, it can passivate the silicon surface and reduce the interface state density.

[0035] The interlayer dielectric layer 8 covers the entire polysilicon spiral field plate 5, and the contact holes formed in the interlayer dielectric layer 8 expose the N+ ohmic contact area 6, the P+ ohmic contact area 7, and the beginning and end of the wiring of the polysilicon spiral field plate 5.

[0036] Preferably, the thickness of the substrate 1 is in the range of 300-500 μm. The thickness of the N-type drift layer 2 is in the range of 30-50 μm, and the resistivity is in the range of 10-50 Ω·cm. The thickness of the field oxide layer 4 is in the range of 0.8-1.5 μm. The interlayer dielectric layer 8 is made of phosphosilicate glass (i.e., phosphorus-doped silicon dioxide, PSG) or borosilicate glass (i.e., boron-phosphorus-doped silicon dioxide, BPSG), and the thickness is in the range of 1.0-1.5 μm.

[0037] Please continue to refer to this. Figure 8 The high-voltage resistant termination structure further includes a metal layer 10, which is disposed on the back side of the substrate 1. This metal layer 10 is fabricated using a back-side metallization process to form good ohmic contacts and external circuit connections, ensuring the electrical performance and long-term reliability of the device.

[0038] In this embodiment, the metal layer 10, the cathode 9a, and the anode 9b are all made of aluminum-silicon alloy or aluminum-silicon-copper alloy. The silicon content is 1%, and the copper content is 0.5%.

[0039] Preferably, the metal layer thickness of the cathode 9a and the anode 9b is 3-5 μm, and the metal layer 10 on the back side of the substrate is 1-2 μm thick.

[0040] In this embodiment, the doping concentration of the P-type region 3 gradually decreases from the center to the edge. Thus, the lateral doped region (i.e., the laterally doped P-region) and the spiral polysilicon field plate form a hybrid junction terminal. The terminal electric field is modulated by both the laterally doped P-region and the spiral polysilicon field plate, resulting in a more uniform electric field distribution.

[0041] Based on simulation and test results from two different terminals, the high-voltage terminal structure provided in this embodiment can further improve the breakdown voltage compared to the traditional lateral variable-doped polycrystalline silicon field plate hybrid terminal. For example... Figure 10 and Figure 11 As shown, the first simulation parameter comparison chart and the second simulation parameter comparison chart in this embodiment correspond to different terminal devices. The samples being compared have the same size (the sample length is 110 µm). The breakdown voltage of the traditional concentric polycrystalline silicon field plate terminal (i.e., conventional terminal) is 668V, while the breakdown voltage of the spiral polycrystalline silicon field plate terminal (i.e., spiral terminal) exceeds 700V, an increase of 13.7%. Although the leakage current of the conventional terminal is smaller, the leakage problem can be effectively improved by narrowing and lengthening the spiral polycrystalline silicon. As can be seen from the figure, the polycrystalline silicon spiral length is increased from 7×10 4 Increased to 2.5×10 5 The leakage current was reduced from 174μA to 63μA, and the leakage current did not increase even when the applied voltage was above 90% of the maximum breakdown voltage.

[0042] Furthermore, the high-voltage resistant terminal structure provided in this embodiment, due to its polycrystalline silicon spiral structure, exhibits a more uniform surface electric field distribution, effectively preventing localized breakdown. For example... Figure 12-15 As shown, from the perspectives of electric field distribution and electric field strength, compared with conventional terminals of the same size, spiral terminals can better "bind" the voltage and make the lower electric field distribution more uniform. The polycrystalline silicon spiral field plate changes the discontinuous electric field distribution below from the concentric circular electric field to the continuous electric field of the spiral polycrystalline silicon field plate terminal, thus improving the withstand voltage.

[0043] The high-voltage termination structure provided in this embodiment can be applied to high-voltage power semiconductor devices such as Schottky Barrier Diode (SBD) and Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0044] Accordingly, the present invention also provides a method for manufacturing a high-voltage resistant terminal structure.

[0045] Please refer to Figure 1-7 This is a schematic diagram of the high-voltage terminal structure of an embodiment of the present invention at each manufacturing step. For example... Figure 1-7 As shown, the manufacturing method of the high-voltage resistant terminal structure includes: S1: A substrate is provided, wherein the substrate is an n+ heavily doped silicon substrate; S2: Perform epitaxial growth on the substrate to form an n-low doped drift layer; S3: Perform the first ion implantation on the n-low doped drift layer to form a P-type region; S4: A field oxygen layer is formed on the N-type drift layer; S5: A polycrystalline silicon spiral field plate is formed on the field oxide layer, and the wiring of the polycrystalline silicon spiral field plate extends outward in a spiral shape. S6: Perform a second ion implantation on the n-low doped drift layer corresponding to the cathode to form an N+ ohmic contact region; S7: A third ion implantation is performed in the P-type region corresponding to the anode to form a P+ ohmic contact region; S8: An interlayer dielectric layer is formed on the N+ ohmic contact region, the P+ ohmic contact region, the polycrystalline silicon spiral field plate, and the exposed field oxide layer. S9: The interlayer dielectric layer is etched to form a contact hole, the contact hole penetrating the interlayer dielectric layer and exposing the N+ ohmic contact area, the P+ ohmic contact area and the beginning and end of the wiring of the polysilicon spiral field plate; S10: A metal electrode is formed on the interlayer dielectric layer, wherein the metal electrode connected to the beginning of the wiring is the anode, and the metal electrode connected to the end of the wiring is the cathode.

[0046] Specifically, in step S2, the epitaxial growth of the n-low doped drift layer can be completed using existing processes, and the thickness and doping concentration of the drift layer are set according to the breakdown voltage of the device.

[0047] In step S3, the first ion implantation is performed using a first mask. The first mask has N concentric annular openings, where N is a natural number. The N concentric annular openings are arranged in order from the inside out. The annular opening closest to the center is the first window, and the annular opening farthest from the center is the Nth window.

[0048] For the first ion implantation, a gradual dose or large-angle rotation is used. The impurity implanted is boron (B) or boron difluoride (BF2). The implantation energy is 80-100 keV. The implantation dose decreases in the order of the windows. The annealing temperature after ion implantation is controlled at 950-1100℃ for 30-60 minutes.

[0049] In this embodiment, the injection dose in the first window is 5 × 10⁻⁶. 13 cm -2 The injection dose decreases from the inside out, with the injection dose in the Nth window being 5 × 10⁻⁶. 11 cm -2 Thus, the concentration of ion doping gradually decreases from the center of P-type region 3 towards the edge.

[0050] In step S4, the formation process of the field oxygen layer 4 includes a first dry oxidation, a wet oxidation, and a second dry oxidation, during which the temperature is controlled at 1000-1100℃. The wet oxidation stage is the main thickening phase. The field oxygen layer 4 formed by the three oxidation processes has a sandwich structure.

[0051] Step S5 includes: A heavily doped polycrystalline silicon layer is formed using a low-pressure chemical vapor deposition (LPCVD) process, with the temperature controlled at 580-650℃ and the source gas being silane (SiH4). The polysilicon layer is etched using a third mask to form wiring that extends spirally from the inside out.

[0052] In step S6, a second ion implantation is performed using a fourth mask to form an N+ ohmic contact region 6 on the cathode side. The impurity implanted this time is phosphorus (P) or arsenic (As), the implantation energy is 80-150 keV, and the implantation dose is 1×10⁻⁶. 15 -5×10 15 cm -2 The annealing temperature after ion implantation is controlled at 850-950℃ for 30 minutes.

[0053] In step S7, a third ion implantation is performed using the fifth mask to form a P+ ohmic contact region 7 on the anode side. The impurity implanted this time is boron (B) or boron difluoride (BF2), the implantation energy is 40-80 keV, and the implantation dose is 1×10⁻⁶. 15 -5×10 15 cm -2 The annealing temperature after ion implantation is controlled at 850-900℃ for 30 minutes.

[0054] Step S8 includes: An interlayer dielectric layer 8 was formed using atmospheric pressure chemical vapor deposition (APCVD) or sub-atmospheric chemical vapor deposition (SACVD) processes. The interlayer dielectric layer 8 is planarized and the stepped cover structure is improved by a reflow process, wherein the temperature of the reflow process is controlled at 850-900℃.

[0055] The atmospheric pressure chemical vapor deposition (APCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) process used to fabricate the interlayer dielectric layer 8, and the low pressure chemical vapor deposition (LPCVD) process used to fabricate the polycrystalline silicon layer, can all adopt existing process technologies, and will not be described in detail in this invention.

[0056] In step S9, a sixth mask is used to etch contact holes in the interlayer dielectric layer 8. The contact holes include an array of circular holes and an array of strip holes. The circular hole array is positioned corresponding to the cathode, and the strip hole array is positioned corresponding to the anode.

[0057] Step S10 includes: The first sputtering process is performed using the seventh mask to form the first metal layer on the front side of the device. Thinning treatment is performed on the back side of the device; and A second sputtering process is performed using a seventh mask to form a second metal layer on the back side of the thinned device.

[0058] In this embodiment, the metal materials used in the two sputtering processes are aluminum-silicon alloy or aluminum-silicon-copper alloy. The thickness of the metal layer formed by the first sputtering is 3-5 μm, and the thickness of the metal layer formed by the second sputtering is 1-2 μm.

[0059] After the first sputtering process, back grinding (BG) is performed, which involves thinning the wafer from the back side to the target thickness using methods such as mechanical grinding. This improves heat dissipation, reduces on-resistance, and reduces the size for subsequent packaging.

[0060] Back-side metallization (BM) refers to the process of "plating" a metal film onto the back of a thinned wafer to provide a good electrical connection and thermal interface for the back of the chip, facilitating subsequent soldering or sintering during packaging.

[0061] This completes the high-voltage resistant terminal structure. The high-voltage resistant terminal structure can be manufactured using only seven photomasks, eliminating the need for additional photomasks and other process steps, thus simplifying the process and reducing costs.

[0062] The present invention has been described in detail above with reference to the accompanying drawings and embodiments. Those skilled in the art can make various modifications to the present invention based on the above description. Therefore, certain details in the embodiments should not be construed as limiting the present invention, and the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A high-voltage resistant terminal structure, characterized in that, include: N-type substrate; An N-type drift layer epitaxially grown on the N-type substrate; A field oxygen layer formed on the N-type drift layer; A polycrystalline silicon spiral field plate formed on the field oxygen layer; An interlayer dielectric layer formed on the polycrystalline silicon spiral field plate; as well as The cathode and anode are formed on the interlayer dielectric layer; The N-type drift layer contains a laterally doped P-type region, and the wiring of the polycrystalline silicon spiral field plate extends outward in a spiral shape. The first end of the wiring is connected to the anode, and the last end of the wiring is connected to the cathode.

2. The high-voltage resistant terminal structure as described in claim 1, characterized in that, The wiring is configured as an equidistant planar spiral structure, with both the beginning and end being rectangular blocks arranged on the same straight line.

3. The high-voltage resistant terminal structure as described in claim 1, characterized in that, The doping concentration of the P-type region gradually decreases from the center to the edge.

4. The high-voltage resistant terminal structure as described in claim 1, characterized in that, A P+ ohmic contact area is provided at the top of the P-type region, and the P+ ohmic contact area is connected to the anode; an N+ ohmic contact area is provided at the top of the N-type drift layer, and the N+ ohmic contact area is connected to the cathode.

5. The high-voltage resistant terminal structure as described in claim 1, characterized in that, The substrate is an n+ heavily doped silicon substrate, the N-type drift layer is an n- lightly doped drift layer, the N-type drift layer is epitaxially grown on the front side of the substrate, and the thickness of the N-type drift layer and the field oxide layer are set according to the terminal withstand voltage level.

6. The high-voltage resistant terminal structure as described in claim 5, characterized in that, The thickness of the substrate ranges from 300 to 500 μm; the thickness of the N-type drift layer ranges from 30 to 50 μm, and the resistivity ranges from 10 to 50 Ω·cm; the thickness of the field oxide layer ranges from 0.8 to 1.5 μm.

7. The high-voltage resistant terminal structure as described in claim 1, characterized in that, The interlayer dielectric layer is made of phosphosilicate glass or borophosphosilicate glass, and its thickness ranges from 1.0 to 1.5 μm.

8. The high-voltage resistant terminal structure as described in claim 1, characterized in that, It also includes a metal layer disposed on the back side of the substrate.

9. The high-voltage resistant terminal structure as described in claim 8, characterized in that, The metal layer, the cathode, and the anode are all made of aluminum-silicon alloy or aluminum-silicon-copper alloy. The thickness of the metal layer on the cathode and the anode is 3-5 μm, and the thickness of the metal layer on the back side of the substrate is 1-2 μm.

10. The high-voltage resistant terminal structure as described in any one of claims 1 to 9, characterized in that, The high-voltage resistant termination structure is applied to Schottky barrier diodes and metal-oxide-semiconductor field-effect transistors.

11. A method for manufacturing a high-voltage resistant terminal structure, characterized in that, include: S1: A substrate is provided, wherein the substrate is an n+ heavily doped silicon substrate; S2: Perform epitaxial growth on the substrate to form an n-low doped drift layer; S3: Perform the first ion implantation on the n-low doped drift layer to form a P-type region; S4: A field oxygen layer is formed on the N-type drift layer; S5: A polycrystalline silicon spiral field plate is formed on the field oxide layer, and the wiring of the polycrystalline silicon spiral field plate extends outward in a spiral shape. S6: Perform a second ion implantation on the n-low doped drift layer corresponding to the cathode to form an N+ ohmic contact region; S7: A third ion implantation is performed in the P-type region corresponding to the anode to form a P+ ohmic contact region; S8: An interlayer dielectric layer is formed on the N+ ohmic contact region, the P+ ohmic contact region, the polycrystalline silicon spiral field plate, and the exposed field oxide layer. S9: The interlayer dielectric layer is etched to form a contact hole, the contact hole penetrating the interlayer dielectric layer and exposing the N+ ohmic contact area, the P+ ohmic contact area and the beginning and end of the wiring of the polysilicon spiral field plate; S10: A metal electrode is formed on the interlayer dielectric layer, wherein the metal electrode connected to the beginning of the wiring is the anode, and the metal electrode connected to the end of the wiring is the cathode.

12. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, In step S3, the first ion implantation is performed using a first mask. The first mask has N concentric annular openings, where N is a natural number. The impurity for ion implantation is boron or boron difluoride, the implantation energy is 80-100 keV, and the implantation dose is arranged in window order from 5 × 10⁻⁶. 13 cm -2 Decrease to 5×10 11 cm -2 .

13. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, In step S4, the formation process of the field oxygen layer includes a first dry oxidation, a wet oxidation, and a second dry oxidation, during which the temperature is controlled at 1000-1100℃.

14. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, Before step S6 and after step S5, the method further includes: etching the field oxide layer using a second mask to remove the field oxide layer at the corresponding positions of the cathode and the anode.

15. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, Step S5 includes: A polycrystalline silicon layer is formed using a low-pressure chemical vapor deposition process, with the temperature controlled at 580-650℃. The polysilicon layer is etched using a third mask to form wiring that extends spirally from the inside out.

16. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, In step S6, a second ion implantation is performed using a fourth mask. The impurity for ion implantation is phosphorus or arsenic, the implantation energy is 80-150 keV, and the implantation dose is 1×10⁻⁶. 15 -5×10 15 cm -2 The annealing temperature after ion implantation is controlled at 850-950℃ for 30 minutes.

17. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, In step S7, a third ion implantation is performed using a fifth mask. The impurity for ion implantation is boron or boron difluoride, the implantation energy is 40-80 keV, and the implantation dose is 1×10⁻⁶. 15 -5×10 15 cm -2 The annealing temperature after ion implantation is controlled at 850-900℃ for 30 minutes.

18. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, Step S8 includes: An interlayer dielectric layer is formed using atmospheric pressure chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition processes. The interlayer dielectric layer is planarized by a reflow process, wherein the temperature of the reflow process is controlled at 850-900℃.

19. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, In step S9, a sixth mask is used to etch contact holes, which include an array of circular holes and an array of strip holes. The position of the array of circular holes corresponds to the cathode, and the position of the array of strip holes corresponds to the anode.

20. The method for manufacturing a high-voltage resistant terminal as described in claim 11, characterized in that, Step S10 includes: The first sputtering process is performed using the seventh mask to form the first metal layer on the front side of the device. Thinning treatment is performed on the back side of the device; and A second sputtering process is performed using a seventh mask to form a second metal layer on the back side of the thinned device.

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