Method for realizing coexistence of poly-si gate and metal gate based on high-k-metal gate platform

Abstract

The application provides a method for realizing coexistence of polysilicon gates and metal gates based on a high-k-metal gate platform, comprising the following steps: step one, providing a substrate, the substrate is divided into a low-voltage device area, a medium-voltage device area and a high-voltage device area, and a first groove is formed in the high-voltage device area; step two, after forming a first gate oxide layer in the first groove, a second groove is formed in the medium-voltage device area; step three, after forming a second gate oxide layer in the second groove, a third gate oxide layer is formed in the low-voltage device area in sequence, a polysilicon gate is formed on the substrate, and an interlayer dielectric layer is formed on the substrate, and the top of the polysilicon gate located in the medium-voltage device area and the high-voltage device area is lower than the top of the polysilicon gate located in the low-voltage device area; step four, removing the polysilicon gate located in the low-voltage device area; and step five, forming a metal gate in the low-voltage device area. Not only the number of masks is not increased, but also the HV and MV devices can be high-voltage while keeping low power consumption and high switching performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform. Background Technology

[0002] Polysilicon gates and metal gates each have their advantages and disadvantages in semiconductor manufacturing. Metal gates have better compatibility with high-k dielectric layers, reduce leakage current, do not suffer from polysilicon depletion effects, have lower threshold voltages, lower resistance, higher mobility, and improved Idsat; therefore, mature process platforms all use metal gates. However, metal gates have complex processes and poor high-temperature stability, while polysilicon gates have a good interface structure and a high melting point. The operating function of polysilicon gates can be adjusted to lower the threshold voltage of NMOS and PMOS devices, which is crucial for high-voltage (HV) and medium-voltage (MV) devices, as they need to maintain low power consumption and efficient switching performance while achieving high withstand voltages. Polysilicon gates have a better interface structure with the silicon substrate and oxide layer, with fewer defects, which helps improve device reliability and stability, especially under high-voltage environments. The high melting point of polysilicon makes it more stable in high-temperature processes, which is a significant advantage for the manufacturing processes of HV and MV devices, as these devices typically need to withstand higher voltages and power.

[0003] Therefore, developing an integrated process based on a high-k metal gate platform to use polysilicon gates in HV and MV devices while using metal gates in low-voltage (LV) devices without requiring additional photomasks is an urgent problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for realizing the coexistence of polysilicon gates and metal gates based on a high-k metal gate platform, so as to solve the problem that the coexistence of polysilicon gates and metal gates cannot be realized based on the high-k metal gate platform in the prior art.

[0005] To achieve the above and other related objectives, this application provides a method for realizing the coexistence of polysilicon gates and metal gates based on a high-k metal gate platform, comprising: Step 1: Provide a substrate, which is divided into a low-voltage device region, a medium-voltage device region, and a high-voltage device region. A first groove is formed in the high-voltage device region. Step 2: After forming the first gate oxide layer in the first groove, a second groove is formed in the medium-voltage device region; Step 3: After forming the second gate oxide layer in the second groove, the third gate oxide layer is formed in the low-voltage device region, the polysilicon gate is formed on the substrate, and the interlayer dielectric layer is formed on the substrate in sequence. The top of the polysilicon gate in the medium-voltage device region and the high-voltage device region is lower than the top of the polysilicon gate in the low-voltage device region. Step 4: Remove the polysilicon gate located in the low-voltage device region; Step 5: Form a metal gate in the low-voltage device region.

[0006] Preferably, the depth of the second groove is less than the depth of the first groove.

[0007] Preferably, the step of forming the first groove includes: sequentially forming a hard mask layer and a first photoresist layer having a first groove pattern on a substrate; using the first photoresist layer as a mask, sequentially etching the hard mask layer and the substrate to form the first groove.

[0008] Preferably, the step of forming the second groove includes: removing the first photoresist layer by an ashing process; sequentially forming a hard mask layer and a second photoresist layer having a second groove pattern on the substrate; and sequentially etching the hard mask layer and the substrate using the second photoresist layer as a mask to form the second groove.

[0009] Preferably, a first gate oxide layer and a second gate oxide layer of a predetermined thickness are formed in the first groove and the second groove respectively by a high-temperature thermal oxidation process.

[0010] Preferably, after forming the second gate oxide layer, the second photoresist layer and the hard mask layer are first removed by an etching process, and then a silicon oxide layer is grown on the substrate by a thermal oxidation process and a polycrystalline silicon layer is formed by a deposition process.

[0011] Preferably, after forming sidewalls on both sides of the polysilicon gate, an interlayer dielectric layer is deposited on the substrate.

[0012] Preferably, the step of forming a metal gate includes: depositing a metal gate material layer on the interlayer dielectric layer using a physical vapor deposition process, a chemical vapor deposition process, or a metal sputtering deposition process to fill the trench formed after removing the polysilicon gate located in the low-voltage device region; and etching back the metal gate material layer to remove the metal gate material layer outside the trench.

[0013] Preferably, the etching process is plasma etching.

[0014] Preferably, before forming the metal gate material layer, the method further includes the step of sequentially forming a high-k dielectric layer, a capping layer, a work function metal layer, and a barrier layer within the trench.

[0015] As described above, the method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform provided in this application has the following advantages: not only does it eliminate the need for additional photomasks, but it also enables HV and MV devices to maintain low power consumption and efficient switching performance while achieving high withstand voltage. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 The flowchart shown is a method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform provided in an embodiment of this application. Figure 2 The diagram shown is a schematic cross-sectional structure of the device formed after step one is completed in the method for realizing the coexistence of polysilicon gate and metal gate based on a high-k metal gate platform provided in the embodiments of this application. Figure 3 The diagram shown is a schematic cross-sectional structure of the device formed after step two in the method for realizing the coexistence of polysilicon gate and metal gate based on a high-k metal gate platform provided in the embodiments of this application. Figure 4 The diagram shows a cross-sectional structure of the device formed after step three in the method for realizing the coexistence of polysilicon gates and metal gates based on a high-k metal gate platform provided in this application embodiment. Figure 5 The diagram shown is a schematic cross-sectional structure of the device formed after step four in the method for realizing the coexistence of polysilicon gate and metal gate based on a high-k metal gate platform provided in the embodiments of this application. Figure 6 The diagram shown is a schematic cross-sectional view of the device formed after step five in the method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform provided in this application embodiment. Detailed Implementation

[0018] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] Please see Figure 1 The document illustrates a flowchart of a method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform, as provided in an embodiment of this application.

[0024] like Figure 1 As shown, the method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform includes the following steps: Step 1: Provide a substrate, which is divided into a low-voltage device region, a medium-voltage device region, and a high-voltage device region. A first groove is formed in the high-voltage device region. Step 2: After forming the first gate oxide layer in the first groove, a second groove is formed in the medium-voltage device region; Step 3: After forming the second gate oxide layer in the second groove, the third gate oxide layer is formed in the low-voltage device region, the polysilicon gate is formed on the substrate, and the interlayer dielectric layer is formed on the substrate in sequence. The top of the polysilicon gate in the medium-voltage device region and the high-voltage device region is lower than the top of the polysilicon gate in the low-voltage device region. Step 4: Remove the polysilicon gate located in the low-voltage device region; Step 5: Form a metal gate in the low-voltage device region.

[0025] In step one, as Figure 2As shown, optionally, the substrate 200 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 200 may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate 200, therefore the type of substrate 200 should not limit the scope of protection of this invention.

[0026] Multiple isolation components 201 are formed on the substrate 200, dividing the substrate 200 into multiple regions, including a low-voltage device region (LV device), a medium-voltage device region (MV device), and a high-voltage device region (HV device). For simplicity, only the low-voltage device region, the medium-voltage device region, and the high-voltage device region are shown in the figure.

[0027] The insulating component 201 may be made of any insulating material such as silicon dioxide (SiO2), and in some cases, the insulating component 201 may be made of oxide material.

[0028] For example, the isolation component 201 is formed by a shallow trench isolation process (STI), which includes, but is not limited to, shallow trench etching, oxide filling and oxide planarization.

[0029] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.

[0030] As an example, the step of forming the first groove 202 in the high-voltage device region includes: sequentially forming a hard mask layer 203 and a first photoresist layer 205 having a pattern of the first groove 202 on a substrate 200; using the first photoresist layer 205 as a mask, sequentially etching the hard mask layer 203 and the substrate 200 to form the first groove 202. Exemplarily, the etching process removes a portion of the isolation component 201.

[0031] In step two, as Figure 3 As shown, a first gate oxide layer 206 of a predetermined thickness is formed in the first groove 202 through a high-temperature thermal oxidation process. Before forming the first gate oxide layer 206, a thin sacrificial oxide layer is first formed to fill the surface defect layer of the first groove 202. Then, the entire sacrificial oxide layer is completely etched by a diluted hydrofluoric acid wet etching process to thoroughly clean the damaged layer on the sidewalls and bottom of the first groove 202.

[0032] Next, a second groove 207 is formed in the medium-voltage device region. As an example, the step of forming the second groove 207 in the medium-voltage device region includes: removing the first photoresist layer 205 by an ashing process; sequentially forming a hard mask layer 203 and a second photoresist layer 208 having the pattern of the second groove 207 on the substrate 200; and sequentially etching the hard mask layer 203 and the substrate 200 using the second photoresist layer 208 as a mask to form the second groove 207. The thickness of the gate oxide layer formed in the medium-voltage device region is less than the thickness of the gate oxide layer formed in the high-voltage device region; therefore, the depth of the second groove 207 is less than the depth of the first groove 202.

[0033] In step three, such as Figure 4 As shown, a second gate oxide layer 209 of a predetermined thickness is formed in the second groove 207 through a high-temperature thermal oxidation process. Before forming the second gate oxide layer 209, a thin sacrificial oxide layer is first formed to fill the surface defect layer of the second groove 207. Then, the entire sacrificial oxide layer is completely etched by a diluted hydrofluoric acid wet etching process to thoroughly clean the damaged layer on the sidewalls and bottom of the second groove 207.

[0034] Next, the second photoresist layer 208 and the hard mask layer 203 are removed by etching. Then, a silicon oxide layer is grown on the substrate 200 by thermal oxidation, and a polysilicon layer is formed by deposition. Then, a third gate oxide layer 210 is formed in the low-voltage device region by photolithography and etching, and a polysilicon gate 211 is formed on the substrate 200. Since the top of the third gate oxide layer 210 is higher than the top of the first gate oxide layer 206 and the second gate oxide layer 209, the top of the polysilicon gate 211 located in the medium-voltage device region and the high-voltage device region is lower than the top of the polysilicon gate 211 located in the low-voltage device region.

[0035] Next, after forming sidewalls on both sides of the polysilicon gate 211, an interlayer dielectric layer 212 is deposited on the substrate 200. The formed interlayer dielectric layer 212 is then chemically mechanically polished to expose the polysilicon gate 211 located in the low-voltage device region. Since the top of the polysilicon gate 211 located in the medium-voltage and high-voltage device regions is lower than the top of the polysilicon gate 211 located in the low-voltage device region, after polishing, only the polysilicon gate 211 located in the low-voltage device region is exposed; the top of the polysilicon gate 211 located in the medium-voltage and high-voltage device regions is still covered by the interlayer dielectric layer 212 (as indicated by the arrows in the figure).

[0036] Optionally, the material of the interlayer dielectric layer 212 may include, but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).

[0037] In step four, as Figure 5 As shown, the polysilicon gate 211 located in the low-voltage device region is removed by photolithography and etching processes to form a trench 213.

[0038] The polysilicon gate 211 located in the medium-voltage device region and the high-voltage device region is covered with an interlayer dielectric layer 212. Therefore, during the removal of the polysilicon gate 211 located in the low-voltage device region, the polysilicon gate 211 located in the medium-voltage device region and the high-voltage device region is retained.

[0039] In step five, as Figure 6 As shown, a metal gate 215 is formed in the low-voltage device region. As an example, the steps of forming the metal gate 215 include: depositing a metal gate material layer on the interlayer dielectric layer 212 using a physical vapor deposition process, a chemical vapor deposition process, or a metal sputtering deposition process to fill the trench 213; and etching back the metal gate material layer to remove the metal gate material layer outside the trench 213. Exemplarily, this etching back is plasma etching.

[0040] For example, the material of the metal gate includes tungsten. Before forming the metal gate material layer, the method further includes the step of sequentially forming a high-k dielectric layer, a capping layer, a work function metal layer, and a barrier layer within the trench 213.

[0041] For example, the high-k dielectric layer is made of hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium dioxide (ZrO2), or hafnium zirconium oxide (HfZrOx), the capping layer is made of titanium nitride (TiN), the work function metal layer is made of titanium nitride and titanium aluminum (TiAl), and the barrier layer is made of titanium nitride and tantalum nitride (TaN).

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] In summary, the method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform provided in this application not only eliminates the need for additional photomasks but also enables HV and MV devices to maintain low power consumption and efficient switching performance while achieving high voltage withstand capability. Therefore, this application effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0044] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for achieving coexistence of polysilicon gates and metal gates based on a high-k metal gate platform, characterized in that, The method includes: Step 1: Provide a substrate, which is divided into a low-voltage device region, a medium-voltage device region, and a high-voltage device region, and form a first groove in the high-voltage device region; Step 2: After forming the first gate oxide layer in the first groove, a second groove is formed in the medium-voltage device region; Step 3: After forming the second gate oxide layer in the second groove, a third gate oxide layer is formed in the low-voltage device region, a polysilicon gate is formed on the substrate, and an interlayer dielectric layer is formed on the substrate in sequence. The top of the polysilicon gate located in the medium-voltage device region and the high-voltage device region is lower than the top of the polysilicon gate located in the low-voltage device region. Step 4: Remove the polysilicon gate located in the low-voltage device region; Step 5: Form a metal gate in the low-voltage device region.

2. The method according to claim 1, characterized in that, The depth of the second groove is less than the depth of the first groove.

3. The method according to claim 1 or 2, characterized in that, The step of forming the first groove includes: sequentially forming a hard mask layer and a first photoresist layer having the first groove pattern on the substrate; using the first photoresist layer as a mask, sequentially etching the hard mask layer and the substrate to form the first groove.

4. The method according to claim 3, characterized in that, The steps for forming the second groove include: removing the first photoresist layer by an ashing process; sequentially forming a hard mask layer and a second photoresist layer having the second groove pattern on the substrate; and sequentially etching the hard mask layer and the substrate using the second photoresist layer as a mask to form the second groove.

5. The method according to claim 1, characterized in that, The first gate oxide layer and the second gate oxide layer of a predetermined thickness are formed in the first groove and the second groove respectively by a high-temperature thermal oxidation process.

6. The method according to claim 4, characterized in that, After the second gate oxide layer is formed, the second photoresist layer and the hard mask layer are first removed by etching process, and then a silicon oxide layer is grown on the substrate by thermal oxidation process and a polysilicon layer is formed by deposition process.

7. The method according to claim 1, characterized in that, After forming sidewalls on both sides of the polysilicon gate, an interlayer dielectric layer is deposited on the substrate.

8. The method according to claim 1, characterized in that, The steps for forming the metal gate include: depositing a metal gate material layer on the interlayer dielectric layer using a physical vapor deposition process, a chemical vapor deposition process, or a metal sputtering deposition process to fill the trench formed after removing the polysilicon gate located in the low-voltage device region; and etching back the metal gate material layer to remove the metal gate material layer outside the trench.

9. The method according to claim 8, characterized in that, The etching process is plasma etching.

10. The method according to claim 8, characterized in that, Before forming the metal gate material layer, the method further includes the step of sequentially forming a high-k dielectric layer, a capping layer, a work function metal layer, and a barrier layer within the trench.

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