Semiconductor device and method of manufacturing the same

Abstract

The application provides a preparation method of a semiconductor device. Firstly, a low-pressure area, a medium-pressure area, a high-pressure area and a plurality of isolation structures between the areas are formed in a substrate; secondly, a high-resistance material layer and a hard mask layer are formed in sequence; then, the high-resistance material layer above the medium-pressure area and the high-pressure area is removed, and the high-resistance material layer above the low-pressure area and the high-resistance material layer above the high-resistance structure definition area are reserved; then, a medium-pressure gate oxide layer is formed; finally, the high-resistance material layer above the low-pressure area is removed, and the high-resistance material layer above the high-resistance structure definition area forms a high-resistance structure. The semiconductor device and the preparation method thereof provided by the application optimize the process of the high-resistance structure in the HKMG high-pressure process, reduce the separate high-resistance structure mask and the related process steps, simplify the process flow and reduce the production cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the semiconductor manufacturing field, high-k metal gate (HKMG) technology has been widely applied to medium-voltage (MV) and high-voltage (HV) process platforms. High-voltage processes are primarily used in screen driver chips, encompassing low-voltage (LV), medium-voltage, and high-voltage devices. Medium-voltage devices are mainly used for brightness adjustment of the screen's light-emitting units, while high-voltage devices are primarily used in screen driver chips. Compared to the standard HKMG process, the integration process for medium- and high-voltage HKMG devices is more complex, requiring multiple additional photomasks. Reducing the number of photomasks has been a key focus of this technology's development and a crucial indicator of the competitiveness of each process. Medium-voltage (8V) and high-voltage (32V) devices differ from low-voltage (0.9V) devices in that they employ a thicker gate oxide (GOX) layer. For the sake of process convenience, the mainstream approach for high-voltage device technology developed on the HKMG platform is to also use the HKMG process for the intermediate-voltage and high-voltage device parts. The intermediate-voltage and high-voltage device areas need to undergo active area recess (AA recess) in advance to keep the gate height consistent with the low-voltage device. The process steps are more complicated than the standard HKMG process.

[0003] The HKMG technology platform needs to provide high resistance (HR) structures to customers for analog circuit design. However, since HKMG's gate material is aluminum, high resistance structures cannot use polysilicon gates. The industry generally requires additional high resistance photolithography (HR Photo) and corresponding process steps to make high resistance structures. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problems of high-resistivity structures requiring additional photomask lithography, complex processes, and high manufacturing costs in the HKMG process.

[0005] To address the above problems, the present invention provides a method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided in which a low-pressure region, a medium-pressure region, a high-pressure region, and a plurality of isolation structures located between the regions are formed;

[0007] A high-resistivity material layer and a hard mask layer are formed sequentially. The high-resistivity material layer covers the low-pressure region, the medium-pressure region, and the high-pressure region, and the hard mask layer covers the high-resistivity material layer.

[0008] Remove the high-resistivity material layer above the medium-pressure region and the high-pressure region, and retain the high-resistivity material layer above the low-pressure region and the high-resistivity structure definition region, which is located between the medium-pressure region and the high-pressure region;

[0009] A medium-pressure gate oxide layer is formed, wherein the medium-pressure gate oxide layer is located in the medium-pressure region;

[0010] The high-resistivity material layer above the low-pressure region is removed, and the high-resistivity material layer above the high-resistivity structure definition region constitutes a high-resistivity structure.

[0011] Optionally, the high-resistivity material layer includes a bottom silicon oxide layer, a titanium nitride layer, and a top silicon oxide layer stacked sequentially.

[0012] Optionally, the material of the hard mask layer is silicon nitride.

[0013] Optionally, the high-resistivity material layer in the medium-pressure region and the high-pressure region can be removed using input and output oxide layer photolithography processes.

[0014] Optionally, a dual-gate photolithography process can be used to remove the high-resistivity material layer above the low-pressure region.

[0015] Optionally, before forming the intermediate-voltage gate oxide layer, the process further includes performing a first wet etching process to remove the hard mask layer.

[0016] Optionally, after removing the high-resistivity material layer above the low-pressure region, the method further includes:

[0017] A metal gate structure is formed, the metal gate structure being located above the low-voltage region, the medium-voltage region, and the high-voltage region;

[0018] A contact plug is formed, the contact plug being located on the high-resistance structure and electrically connected to the high-resistance structure.

[0019] Optionally, a low-voltage gate oxide layer is formed prior to the formation of the metal gate structure, the low-voltage gate oxide layer being located on the surface of the low-voltage region.

[0020] Optionally, the step of forming the contact plug includes:

[0021] A buffer layer is formed on the interlayer dielectric layer;

[0022] A first contact hole and a second contact hole are formed, the first contact hole and the second contact hole are located in the buffer layer, the first contact hole and the second contact hole respectively penetrate the buffer layer and extend into the interlayer dielectric layer, the first contact hole exposes the surface of the high-resistivity structure near the medium-pressure region, and the second contact hole exposes the surface of the high-resistivity structure near the high-pressure region;

[0023] A second metal layer is formed, the second metal layer located in the first contact hole constitutes the first contact plug, and the second metal layer located in the second contact hole constitutes the second contact plug.

[0024] Based on the same inventive concept, the present invention also provides a semiconductor device, which is prepared by the semiconductor device preparation method.

[0025] In a semiconductor device fabrication method provided by this invention, firstly, a low-voltage region, a medium-voltage region, a high-voltage region, and multiple isolation structures located between each region are formed in a substrate; secondly, a high-resistivity material layer and a hard mask layer are formed sequentially, with the high-resistivity material layer covering the low-voltage, medium-voltage, and high-voltage regions, and the hard mask layer covering the high-resistivity material layer; next, the high-resistivity material layers above the medium-voltage and high-voltage regions are removed, retaining the high-resistivity material layers above the low-voltage region and above the high-resistivity structure definition region, which is located between the medium-voltage and high-voltage regions; then, a medium-voltage gate oxide layer is formed, located in the medium-voltage region; finally, the high-resistivity material layer above the low-voltage region is removed, and the high-resistivity material layer above the high-resistivity structure definition region constitutes the high-resistivity structure. The semiconductor device and its fabrication method provided by this invention, by optimizing the high-resistivity structure process in the HKMG high-voltage process, reduce the need for separate high-resistivity structure photomasks and related process steps, simplifying the process flow and reducing production costs. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the active region etched back in the medium-voltage region of the existing HKMG high-voltage process.

[0027] Figure 2 This is a schematic diagram of the structure for forming the intermediate-voltage gate oxide layer in the existing HKMG high-voltage process.

[0028] Figure 3 This is a schematic diagram of the structure for forming a high-voltage resistor layer in the existing HKMG high-voltage process.

[0029] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0030] Figure 5 This is a schematic diagram of the substrate structure according to an embodiment of the present invention.

[0031] Figure 6 This is a schematic diagram of the structure for forming a high-resistivity material layer and a hard mask layer according to an embodiment of the present invention.

[0032] Figure 7 This is a schematic diagram of the structure of removing the high-resistivity material layer above the medium-pressure region and the high-pressure region according to an embodiment of the present invention.

[0033] Figure 8 This is a schematic diagram of the structure for removing the hard mask layer according to an embodiment of the present invention.

[0034] Figure 9 This is a schematic diagram of the structure of the intermediate voltage gate oxide layer and the first oxide layer in an embodiment of the present invention.

[0035] Figure 10 This is a schematic diagram of the structure for removing the high-resistivity material layer above the low-pressure region according to an embodiment of the present invention.

[0036] Figure 11 This is a schematic diagram of the structure for forming a low-voltage gate oxide layer according to an embodiment of the present invention.

[0037] Figure 12 This is a schematic diagram of the metal gate structure formed according to an embodiment of the present invention.

[0038] Figure 13 This is a schematic diagram of the structure for forming a buffer layer according to an embodiment of the present invention.

[0039] Figure 14 This is a schematic diagram of the structure for forming the first contact hole and the second contact hole according to an embodiment of the present invention.

[0040] Figure 15 This is a schematic diagram of the structure for forming the first contact plug and the second metal plug according to an embodiment of the present invention.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] Figures 1-3 101-Substrate; 102-Low-voltage region; 103-Medium-voltage region; 104-High-voltage region; 105-Isolation region; 106-Metal gate dielectric layer; 107-Hard mask layer; 108-Active region opening; 109-Gate oxide layer; 110-Medium-voltage gate oxide layer; 111-Low-voltage gate oxide layer; 112-Low-voltage metal gate; 113-Medium-voltage metal gate; 114-High-voltage metal gate; 115-Dielectric layer; 116-Silicon oxide layer; 117-Titanium nitride layer; 118-Silicon nitride layer; 119-High-voltage resistor layer; 120-Contact layer; 121-First contact metal; 122-Second contact metal.

[0043] Figures 5-15201-Substrate; 202-Low-voltage region; 203-Medium-voltage region; 204-High-voltage region; 205-Isolation region; 206-Metal gate dielectric stack; 207-Bottom silicon oxide layer; 208-Titanium nitride layer; 209-Top silicon oxide layer; 210-High-resistivity material layer; 210a-High-resistivity structure; 211-Hard mask layer; 212-High-resistivity structure definition region; 213-First opening; 214-Second opening; 215-Medium-voltage gate oxide layer; 216-First oxide layer; 217-Low-voltage gate oxide layer; 218- 219-Low-voltage grid dielectric layer; 220-High-voltage grid dielectric layer; 221-Low-voltage sidewall; 223-Medium-voltage sidewall; 224-High-voltage sidewall; 225-Interlayer dielectric layer; 226-Low-voltage first metal layer; 227-Medium-voltage first metal layer; 228-High-voltage first metal layer; 229-Low-voltage metal grid; 230-Medium-voltage metal grid; 231-High-voltage metal grid; 232-Buffer layer; 233-First contact hole; 234-Second contact hole; 235-First contact plug; 236-Second contact plug. Detailed Implementation

[0044] The semiconductor device and its fabrication method provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may have different emphases and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between various components, elements, steps, etc.

[0045] Figures 1 to 3 This is a schematic diagram of the high-resistivity structure in the existing HKMG high-voltage process. To make the process of the high-resistivity structure in the existing HKMG high-voltage process clearer and easier to understand, the following is combined with... Figures 1 to 3 The process of high-resistivity structures in the existing HKMG high-voltage process is explained.

[0046] like Figure 1As shown, an input / output oxide photolithography (IOX Photo) process is performed to etch the active area above the medium-pressure region 103, completing the active area recess (AA Recess) of the medium-pressure region 103, and forming the active area opening 108 of the medium-pressure region 103.

[0047] like Figure 2 As shown, a dual gate photolithography (DG Photo) process is performed to remove the gate oxide layer 109 outside the active region opening 108 of the medium-pressure region 103, forming a medium-pressure gate oxide layer 110.

[0048] like Figure 3 As shown, a high-resistance photolithography (HRPhoto) process is performed to retain the resistive layer between the medium-pressure region 103 and the high-pressure region 104 to form a high-pressure resistive layer 119.

[0049] The formation of high-resistivity structures in the existing HKMG process has problems such as the need for additional photomask lithography, complex process, and high manufacturing cost.

[0050] Based on this, the core idea of ​​the present invention is that, in the semiconductor device fabrication method provided by the present invention, firstly, a low-voltage region, a medium-voltage region, a high-voltage region, and multiple isolation structures located between each region are formed in a substrate; secondly, a high-resistivity material layer and a hard mask layer are formed sequentially, with the high-resistivity material layer covering the low-voltage region, the medium-voltage region, and the high-voltage region, and the hard mask layer covering the high-resistivity material layer; next, the high-resistivity material layers above the medium-voltage region and the high-voltage region are removed, retaining the high-resistivity material layer above the low-voltage region and the high-resistivity structure definition region, which is located between the medium-voltage region and the high-voltage region; then, a medium-voltage gate oxide layer is formed, located in the medium-voltage region; finally, the high-resistivity material layer above the low-voltage region is removed, and the high-resistivity material layer above the high-resistivity structure definition region constitutes the high-resistivity structure. The semiconductor device and its fabrication method provided by the present invention, by optimizing the process of the high-resistivity structure in the HKMG high-voltage process, reduces the need for separate high-resistivity structure photomasks and related process steps, simplifies the process flow, and reduces production costs.

[0051] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, this embodiment provides a method for fabricating a semiconductor device, including:

[0052] Step S1: Provide a substrate in which a low-voltage region, a medium-voltage region, a high-voltage region, and a plurality of isolation structures located between the regions are formed;

[0053] Step S2: A high-resistivity material layer and a hard mask layer are formed sequentially. The high-resistivity material layer covers the low-pressure region, the medium-pressure region, and the high-pressure region, and the hard mask layer covers the high-resistivity material layer.

[0054] Step S3: Remove the high-resistivity material layer above the medium-pressure region and the high-pressure region, and retain the high-resistivity material layer above the low-pressure region and the high-resistivity structure definition region, which is located between the medium-pressure region and the high-pressure region;

[0055] Step S4: Form a medium-voltage gate oxide layer, wherein the medium-voltage gate oxide layer is located in the medium-voltage region;

[0056] Step S5: Remove the high-resistivity material layer above the low-pressure region. The high-resistivity material layer above the high-resistivity structure definition area constitutes a high-resistivity structure.

[0057] Figures 5 to 15 This is a schematic diagram of the structure corresponding to the semiconductor device fabrication method of an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with... Figures 5 to 15 The method for fabricating the semiconductor device provided in this embodiment will be described.

[0058] like Figure 5 As shown, a substrate 201 is provided. Substrate 201 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, the substrate can be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 201 is a silicon substrate.

[0059] Please continue to refer to this. Figure 5In step S1, the substrate 201 forms the low-voltage region 202, the medium-voltage region 203, the high-voltage region 204, and a plurality of isolation regions 205 located between the regions. A metal gate dielectric stack 206 is formed above the high-voltage region 204, and the upper surfaces of the low-voltage region 202, the medium-voltage region 203, the metal gate dielectric stack 206, and the plurality of isolation regions 205 are flush. In this embodiment, for example, a shallow trench isolation (STI) process is used to form the plurality of isolation regions 205 in the substrate 201. The isolation regions 205 are used to isolate the active region to define the low-voltage region 202, the medium-voltage region 203, and the high-voltage region 204 in the substrate 201.

[0060] The metal gate dielectric stack 206 is formed above the high-voltage region 204. In this embodiment, the operating voltage of the high-voltage device is, for example, 32V, and the thickness of the metal gate dielectric stack 206 is, for example, 15nm~35nm.

[0061] like Figure 6 As shown, in step S2, a high-resistivity material layer 210 and a hard mask layer 211 are formed sequentially. The high-resistivity material layer covers the low-pressure region 202, the medium-pressure region 203, and the high-pressure region 204, and the hard mask layer 211 covers the high-resistivity material layer 210. The high-resistivity material layer 210 includes a bottom silicon oxide layer 207, a titanium nitride layer 208, and a top silicon oxide layer 209 stacked sequentially. The material of the hard mask layer 211 is silicon nitride.

[0062] Please continue to refer to this. Figure 6 In this embodiment, for example, chemical vapor deposition (CVD) is used to deposit a bottom silicon oxide layer 207 on the surface of the substrate 201, the thickness of the bottom silicon oxide layer 207 being, for example, 3nm to 10nm; next, for example, chemical vapor deposition is used to deposit a titanium nitride layer 208 on the bottom silicon oxide layer 207, the thickness of the titanium nitride layer 208 being, for example, 3nm to 10nm; then, for example, chemical vapor deposition is used to deposit a top silicon oxide layer 209 on the surface of the titanium nitride layer 208, the thickness of the top silicon oxide layer 209 being, for example, 3nm to 10nm, and the high-resistivity material layer 210 is composed of the bottom silicon oxide layer 207, the titanium nitride layer 208, and the top silicon oxide layer 209; finally, for example, chemical vapor deposition is used to form a hard mask layer 211 on the top silicon oxide layer 209, the thickness of the hard mask layer 211 being, for example, 3nm to 10nm.

[0063] like Figure 7As shown, in step S3, the high-resistivity material layer 210 above the medium-pressure region 203 and the high-pressure region 204 is removed, while the high-resistivity material layer 210 above the low-pressure region 202 and the high-resistivity structure definition region 212 are retained. The high-resistivity structure definition region 212 is located between the medium-pressure region 203 and the high-pressure region 204. A first opening 213 is formed in the medium-pressure region 203, and a second opening 214 with the same depth as the first opening 213 is formed in the metal gate dielectric stack 206. The high-resistivity material layer 210 in the medium-pressure region 203 and the high-pressure region 204 is removed using an input / output oxide photolithography (IOX Photo) process.

[0064] Please continue to refer to this. Figure 7 In this embodiment, the process of the input and / or output oxide layer photolithography is as follows: A first photoresist (not shown in the figure) is coated on the hard mask layer 211; for example, the first photoresist is exposed and developed using input and output oxide layer photomasks, so that the first photoresist above the low-pressure region 203 and the high-resistivity structure definition region 212 is retained, while the first photoresist above the medium-pressure region 203 and the high-pressure region 204 is removed, forming a patterned first photoresist; using the patterned first photoresist as a mask, for example, reactive ion etching is used to sequentially etch away the exposed hard mask layer 211, the top silicon oxide layer 209, the titanium nitride layer 208, and the bottom silicon oxide layer 207, and continues etching downwards until the first opening 213 is formed in the medium-pressure region 203 and the second opening 214 is formed in the metal gate dielectric stack 206, the second opening 214 having the same depth as the first opening 213; for example, plasma ashing is used to remove the remaining photoresist.

[0065] like Figure 8 As shown, prior to the step of forming the medium-voltage gate oxide layer, the process further includes performing a first wet etching process to remove the hard mask layer 211.

[0066] Please continue to refer to this. Figure 8 In this embodiment, for example, a hot phosphoric acid solution (H3PO4) is used to wet-etch the hard mask layer 211 to remove the hard mask layer 211 on the high-resistivity material layer 210 and expose the underlying top silicon oxide layer 209.

[0067] like Figure 9As shown, in step S4, the medium-voltage gate oxide layer 215 is formed. The medium-voltage gate oxide layer 215 is formed in the first opening 213 of the medium-voltage region 203 and the first oxide layer 216 is formed simultaneously in the second opening 214. The medium-voltage gate oxide layer 215 and the first oxide layer 216 have the same thickness.

[0068] Please continue to refer to this. Figure 9 In this embodiment, for example, a chemical vapor deposition process is used, such as depositing silicon oxide in the first opening 213 and the second opening 214 to form the medium-voltage gate oxide layer 215 and the first oxide layer 216.

[0069] The thickness of the intermediate voltage gate oxide layer 215 corresponds to the operating voltage requirement of the intermediate voltage device. In this embodiment, the operating voltage of the intermediate voltage device is, for example, 8V, and the thickness of the intermediate voltage gate oxide layer 215 is, for example, 5nm~15nm. Since the depths of the first opening 213 and the second opening 214 are the same, the thickness of the intermediate voltage gate oxide layer 215 and the first oxide layer 216 are the same, and the upper surfaces of the intermediate voltage gate oxide layer 215 and the first oxide layer 216 remain flush.

[0070] like Figure 10 As shown, in step S5, the high-resistivity material layer 210 above the low-voltage region 202 is removed. The high-resistivity material layer 210 above the high-resistivity structure definition region 212 constitutes the high-resistivity structure 210a. The high-resistivity material layer above the low-voltage region is removed using a dual-gate photolithography (DG Photo) process. After removing the high-resistivity material layer 210 above the low-voltage region 202, the process further includes:

[0071] Step S6: Form a metal gate (MG) structure, which is located above the low-voltage region 202, the medium-voltage region 203 and the high-voltage region 204;

[0072] Step S7: A contact plug is formed, which is located on the high-resistance structure 210a and electrically connected to the high-resistance structure 210a.

[0073] Please continue to refer to this. Figure 10In this embodiment, for example, the high-resistivity material layer 210 above the low-pressure region 202 is removed using a dual-gate photolithography process. The dual-gate photolithography process involves, for example, coating a second photoresist onto the surface of the substrate 201; performing exposure and development, for example, using a dual-gate photomask, to remove the second photoresist above the low-pressure region 202, while other areas are covered and protected by the second photoresist; then, for example, using a dry etching process, removing the high-resistivity material layer 210 above the low-pressure region 202 to expose the surface of the low-pressure region 202; and for example, using a plasma ashing process to remove the remaining second photoresist. The high-resistivity material layer 210 above the high-resistivity structure definition region 212 is protected by the second photoresist and thus remains intact, forming the high-resistivity structure 210a.

[0074] like Figure 11 As shown, in step S6, a low-voltage gate oxide layer 217 is formed before forming the metal gate structure. The low-voltage gate oxide layer 217 is located on the surface of the low-voltage region 202. In this embodiment, for example, a thermal oxidation process is used to form the low-voltage gate oxide layer 217 on the surface of the low-voltage region 202. The material for forming the low-voltage gate oxide layer 217 is, for example, silicon oxide, and the thickness of the low-voltage gate oxide layer 217 is, for example, 0.8 nm to 1.2 nm. The operating voltage of the low-voltage device in this embodiment is, for example, 0.9 V.

[0075] In this embodiment, the metal gate structure is formed after the low-voltage gate oxide layer 217 is formed. For example... Figure 12As shown, the metal gate structure includes a low-voltage metal gate 229, a medium-voltage metal gate 230, and a high-voltage metal gate 231. The low-voltage metal gate 229 includes a low-voltage gate dielectric layer 218, a low-voltage sidewall 221, and a low-voltage first metal layer 226; the medium-voltage metal gate 230 includes a medium-voltage gate dielectric layer 219, a medium-voltage sidewall 223, and the medium-voltage first metal layer 227; the high-voltage metal gate 231 includes a high-voltage gate dielectric layer 220, a high-voltage sidewall 224, and a high-voltage first metal layer 228. The low-voltage gate dielectric layer 218, the medium-voltage gate dielectric layer 219, and the high-voltage gate dielectric layer 220 are respectively located on the low-voltage gate oxide layer 217, the medium-voltage gate oxide layer 215, and the first oxide layer 216. The low-voltage sidewall 221, the medium-voltage sidewall 223, and the high-voltage sidewall 224 are located on both sides of the low-voltage gate dielectric layer 218, the medium-voltage gate dielectric layer 219, and the high-voltage gate dielectric layer 220, respectively. The interlayer dielectric layer 225 covers the sidewalls of the low-voltage sidewall 221, the medium-voltage sidewall 223, and the high-voltage sidewall 224, and also covers the high-resistivity structure 210a. The low-voltage first metal layer 226, the medium-voltage first metal layer 227, and the high-voltage first metal layer 228 are located above the low-voltage sidewall 221, the medium-voltage sidewall 223, and the high-voltage sidewall 224, respectively.

[0076] In step S7, the contact plug is formed, the contact plug being located on the high-resistance structure 210a and electrically connected to the high-resistance structure 210a. The step of forming the contact plug includes:

[0077] Step S71: A buffer layer is formed, wherein the buffer layer is located on the interlayer dielectric layer;

[0078] A first contact hole and a second contact hole are formed, the first contact hole and the second contact hole are located in the buffer layer, the first contact hole and the second contact hole respectively penetrate the buffer layer and extend into the interlayer dielectric layer, the first contact hole exposes the surface of the high-resistivity structure near the medium-pressure region, and the second contact hole exposes the surface of the high-resistivity structure near the high-pressure region;

[0079] A second metal layer is formed, the second metal layer located in the first contact hole constitutes the first contact plug, and the second metal layer located in the second contact hole constitutes the second contact plug.

[0080] like Figure 13 As shown, in step S71, the buffer layer 232 is formed, and the buffer layer 232 is located on the interlayer dielectric layer 225. Please refer to [link / reference needed]. Figure 13 In this embodiment, the buffer layer 232 is formed, for example, by chemical vapor deposition, and the material forming the buffer layer 232 is, for example, silicon nitride.

[0081] like Figure 14 As shown, in step S72, the first contact hole 233 and the second contact hole 234 are formed in the buffer layer 232. The first contact hole 233 and the second contact hole 234 penetrate the buffer layer 232 and extend into the interlayer dielectric layer 225. The first contact hole 233 exposes the surface of the high-resistivity structure 210a near the medium-pressure region 203, and the second contact hole 234 exposes the surface of the high-resistivity structure 210a near the high-pressure region 204.

[0082] Please continue to refer to this. Figure 14 In this embodiment, the process of forming the first contact hole 233 and the second contact hole 234 is as follows: coating the buffer layer 232 with a third photoresist, for example, by using a contact hole photomask for exposure and development; for example, using dry etching to sequentially etch the buffer layer 232 and part of the interlayer dielectric layer 225 to form the first contact hole 233 and the second contact hole 234 that penetrate the buffer layer 232 and extend into the interlayer dielectric layer 225; for example, using a plasma ashing process to remove the remaining third photoresist.

[0083] like Figure 15 As shown, in step S73, a second metal layer is formed. The second metal layer located within the first contact hole 233 constitutes the first contact plug 235, and the second metal layer located within the second contact hole 234 constitutes the second contact plug 236. Please continue to refer to... Figure 15 In this embodiment, for example, a titanium and titanium nitride (Ti / TiN) barrier layer is deposited using a physical vapor deposition process, and then a tungsten (W) metal layer is filled using an electroplating process to form the second metal layer. The high-resistivity structure 210a leads out electrodes through the first contact plug 235 and the second contact plug 236 for use in analog circuit design.

[0084] In summary, the semiconductor device fabrication method provided in this embodiment involves the following steps: First, a low-voltage region, a medium-voltage region, a high-voltage region, and multiple isolation structures located between each region are formed in a substrate. Second, a high-resistivity material layer and a hard mask layer are formed sequentially, with the high-resistivity material layer covering the low-voltage, medium-voltage, and high-voltage regions, and the hard mask layer covering the high-resistivity material layer. Next, the high-resistivity material layers above the medium-voltage and high-voltage regions are removed, leaving the high-resistivity material layers above the low-voltage region and above the high-resistivity structure definition region, which is located between the medium-voltage and high-voltage regions. Then, a medium-voltage gate oxide layer is formed, located in the medium-voltage region. Finally, the high-resistivity material layer above the low-voltage region is removed, and the high-resistivity material layer above the high-resistivity structure definition region constitutes the high-resistivity structure. The semiconductor device and its fabrication method provided in this embodiment optimize the high-resistivity structure process in the HKMG high-voltage process, reducing the need for separate high-resistivity structure photomasks and related process steps, simplifying the process flow, and lowering production costs.

[0085] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided in which a low-pressure region, a medium-pressure region, a high-pressure region, and a plurality of isolation structures located between the regions are formed; A high-resistivity material layer and a hard mask layer are formed sequentially. The high-resistivity material layer covers the low-pressure region, the medium-pressure region, and the high-pressure region, and the hard mask layer covers the high-resistivity material layer. Remove the high-resistivity material layer above the medium-pressure region and the high-pressure region, and retain the high-resistivity material layer above the low-pressure region and the high-resistivity structure definition region, which is located between the medium-pressure region and the high-pressure region; A medium-pressure gate oxide layer is formed, wherein the medium-pressure gate oxide layer is located in the medium-pressure region; The high-resistivity material layer above the low-pressure region is removed, and the high-resistivity material layer above the high-resistivity structure definition region constitutes a high-resistivity structure.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The high-resistivity material layer comprises a bottom silicon oxide layer, a titanium nitride layer, and a top silicon oxide layer stacked sequentially.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The material of the hard mask layer is silicon nitride.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The high-resistivity material layer in the medium-voltage region and the high-voltage region is removed using input and output oxide layer photolithography processes.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The high-resistivity material layer above the low-pressure region is removed using a dual-gate photolithography process.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the medium-voltage gate oxide layer further includes performing a first wet etching process to remove the hard mask layer.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After the step of removing the high-resistivity material layer above the low-pressure region, the method further includes: A metal gate structure is formed, the metal gate structure being located above the low-voltage region, the medium-voltage region, and the high-voltage region; A contact plug is formed, the contact plug being located on the high-resistance structure and electrically connected to the high-resistance structure.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, A low-voltage gate oxide layer is formed prior to the formation of the metal gate structure, and the low-voltage gate oxide layer is located on the surface of the low-voltage region.

9. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The steps for forming the contact plug include: A buffer layer is formed on the interlayer dielectric layer; A first contact hole and a second contact hole are formed, the first contact hole and the second contact hole are located in the buffer layer, the first contact hole and the second contact hole respectively penetrate the buffer layer and extend into the interlayer dielectric layer, the first contact hole exposes the surface of the high-resistivity structure near the medium-pressure region, and the second contact hole exposes the surface of the high-resistivity structure near the high-pressure region; A second metal layer is formed, the second metal layer located in the first contact hole constitutes the first contact plug, and the second metal layer located in the second contact hole constitutes the second contact plug.

10. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 9.

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