Method of forming metal gate

Abstract

The application discloses a metal gate forming method, and belongs to the technical field of semiconductors. The metal gate forming method comprises the following steps: providing a wafer with a gate recess formed in an insulating medium layer on a wafer surface; sequentially depositing a high-K gate dielectric layer, a work function layer and a barrier layer in the gate recess; filling a metal layer in the gate recess formed with the barrier layer, so that the metal layer is higher than the surface of the insulating medium layer by a preset thickness; removing the high-K gate dielectric layer on the surface of the insulating medium layer and other dielectric layers on the high-K gate dielectric layer by adopting a chemical mechanical polishing method, so that the metal layer is substantially flush with the surface of the insulating medium layer; wet etching the metal layer and the barrier layer in the gate recess, so that the metal layer in the gate recess is lower than the insulating medium layer to a first preset height; and wet etching the work function layer in the gate recess to be substantially flush with the metal layer. The metal layer is etched by adopting a wet etching method, the height of each film layer is accurately controlled, and damage to the film layer caused by plasma in dry etching is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a metal gate. Background Technology

[0002] In advanced manufacturing processes, to address the depletion effect of polysilicon, improve gate control, and increase effective capacitance, metal gates are commonly used instead of traditional polysilicon gates to control the switching of the channel. To achieve the same control performance as traditional polysilicon gates, engineers add multiple layers of film materials (TiN / TiAl / TaN / HfO2, etc.) between the metal gate and the channel to modulate the device's electrical properties. This inevitably leads to differences in the etching rate of dry etching when etching various film materials during subsequent Metal Gate Etch Back (MGEB) processes, increasing the difficulty of controlling the gate height. Furthermore, dry etching introduces loading for gates of different lengths, further resulting in different electrical properties for devices with different gate lengths. Therefore, as device dimensions continue to shrink, finding a solution that can perform MGEB with minimal loading is crucial for improving electrical properties.

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming a metal gate, so as to solve the problem of difficulty in controlling the gate height during the metal gate fabrication process.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a metal grid, comprising:

[0006] Provides a wafer with gate grooves formed in the insulating dielectric layer on the wafer surface;

[0007] A high-K gate dielectric layer, a work function layer, and a barrier layer are sequentially deposited within the gate groove;

[0008] A metal layer is filled in the gate groove where the barrier layer is formed, such that the metal layer is higher than the surface of the insulating dielectric layer by a predetermined thickness.

[0009] Chemical mechanical polishing is used to remove the high-K gate dielectric layer and other dielectric layers on the surface of the insulating dielectric layer, so that the metal layer is approximately flush with the surface of the insulating dielectric layer.

[0010] The metal layer and the barrier layer inside the gate groove are wet-etched back, so that the metal layer inside the gate groove is lower than the insulating dielectric layer by a first preset height;

[0011] The work function layer within the gate groove is wet-etched back to approximately flush with the metal layer.

[0012] Preferably, the metal layer and the barrier layer are etched back using a first solution wet etching process, wherein the first solution contains a predetermined proportion of NH4OH and H2O2.

[0013] Preferably, the first solution is an SC1 solution, which contains NH4OH, H2O2 and deionized water, and the volume ratio is NH4OH:H2O2:deionized water = 1:1:5.

[0014] Preferably, after wet etching of the metal layer and the barrier layer, the metal layer and the barrier layer are further cleaned to remove any residual first solution.

[0015] Preferably, the work function layer is etched back using a hydrochloric acid solution with a mass fraction of less than 20% via a wet etching process.

[0016] Preferably, the metal layer contains at least tungsten.

[0017] Preferably, the barrier layer contains at least titanium.

[0018] Preferably, the work function layer is made of TiAl.

[0019] Preferably, the barrier layer is made of TiN.

[0020] Preferably, the high-k gate dielectric layer is made of HfSiO2.

[0021] The present invention provides a method for forming a metal gate, comprising: providing a wafer in which a gate groove is formed within an insulating dielectric layer on the wafer surface; sequentially depositing a high-k gate dielectric layer, a work function layer, and a barrier layer within the gate groove; filling the gate groove in which the barrier layer is formed with a metal layer, such that the metal layer is higher than the surface of the insulating dielectric layer by a predetermined thickness; removing the high-k gate dielectric layer and other dielectric layers on the surface of the insulating dielectric layer using chemical mechanical polishing, such that the metal layer is approximately flush with the surface of the insulating dielectric layer; wet etching back the metal layer and the barrier layer within the gate groove, such that the metal layer within the gate groove is lower than the insulating dielectric layer by a first predetermined height; and wet etching back the work function layer within the gate groove until it is approximately flush with the metal layer. By using wet etching to etch the metal layer, the height of each film layer can be controlled, thereby avoiding damage to the film layers caused by plasma in dry etching. Furthermore, different chemicals can be used for stepwise wet etching to achieve precise control of the height of each film layer in the metal gate region, thereby freely controlling the electrical parameters of the device. In addition, wet etching can control the etching rate by adjusting chemical concentration, temperature, wafer rotation speed, etc., thereby increasing the process window, regulating uniformity, and reducing the load on each area. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a stacked structure in the prior art;

[0023] Figure 2 This is a schematic diagram of the metal layer structure in the prior art;

[0024] Figure 3 This is a schematic diagram of the structure after CMP process in the prior art;

[0025] Figure 4 This is a schematic diagram of the structure after back etching using existing technology;

[0026] Figure 5 The difference in load on different gate lengths during dry etching.

[0027] Figure 6 This is a flowchart of an embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of a stacked structure according to an embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of a metal layer structure according to an embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of the structure after CMP process according to an embodiment of the present invention;

[0031] Figure 10This is a schematic diagram of the structure after the first wet etching step according to an embodiment of the present invention;

[0032] Figure 11 This is a schematic diagram of the structure after the second wet etching step in an embodiment of the present invention.

[0033] In the attached image:

[0034] 10. Substrate; 11. Source region; 12. Drain region; 20. Insulating dielectric layer; 30. High-K gate dielectric layer; 40. Work function layer; 50. Barrier layer; 60. Metal layer. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. Embodiments of this disclosure are illustrated in the accompanying drawings. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the content of this disclosure thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used in this disclosure is for describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0037] It should be understood that when an element or layer is referred to as being "in," "near," "connected to," or "coupled to" another element or layer, it can be directly in, near, connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly in," "directly near," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. It should be understood that although the terms "first," "second," "third," etc., can be used to describe various elements, parts, regions, layers, doping types, and / or portions, they should not be limiting of these elements, parts, regions, layers, doping types, and / or portions. These terms are used only to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as the second element, part, region, layer, doping type, or portion. For example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type. The first doping type and the second doping type are different doping types. For example, the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.

[0038] This document uses spatial relation terms such as “below,” “under,” “lower,” “above,” or “upper” to describe the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, the element described as “below” or “under” another element or feature would be facing “above” that other element or feature. Therefore, the exemplary terms “below” and “under” can include upward and downward directions. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein should be interpreted accordingly.

[0039] As used herein, the singular forms “a,” “an,” “an,” and “the” may include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, integral, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. Additionally, in the specification, the term “and / or” includes any and all combinations of the associated listed items.

[0040] Embodiments of this disclosure are described herein with reference to schematic cross-sectional views of preferred embodiments (and intermediate structures) of this disclosure; therefore, it is expected that the shapes shown will vary due to manufacturing techniques and / or tolerances, etc. Consequently, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but should include shape variations, for example, due to manufacturing techniques. For instance, injection regions shown as rectangular typically have rounded or curved features at their edges and / or injection concentration gradients, rather than a binary variation from the injection region to the non-injection region. Furthermore, the embedded region formed by injection may result in some injection in the area between the embedded region and the surface where the injection is performed. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the device regions, nor do they limit the scope of this disclosure.

[0041] Existing technology uses dry etching to adjust the gate height in MGEB, as follows: Figure 1 As shown, a metal gate region is dry-etched in the active region using a pre-processing technique, followed by the growth of an insulating dielectric layer 20, a high-k gate dielectric layer 30, a work function layer 40, and a barrier layer 50; as Figure 2 As shown, a metal layer 60 is grown on the wafer surface using CVD (Chemical Vapor Deposition) to fill the metal gate region; the metal layer 60 is typically made of tungsten. Figure 3As shown, CMP process is used to remove excess metal layer 60, and further grinding is used to remove surface work function layer 40 and other film layers, finally stopping at the surface of insulating dielectric layer 20; then as... Figure 4 As shown, dry etching is used to further etch away part of the metal layer 60 and the surrounding film layer. At the same time, the etching time needs to be precisely controlled to adjust the height of the final metal gate. Finally, wet cleaning and drying are used to clean the surface residues and by-products, in preparation for the next process.

[0042] The aforementioned existing technology, which uses dry etching to control the height of the metal gate, presents the following challenges:

[0043] First, dry etching requires the use of plasma. During etching, the plasma inevitably damages the surface material, causing material deformation and consequently leading to drift in the electrical properties of the device. Second, fabricating metal gates through a one-step dry etching process presents significant challenges in precisely controlling the height of each film layer, resulting in a smaller process window. Furthermore, dry etching introduces loading at the edges and center of the wafer, causing differences in chip electrical properties across different regions of the wafer, affecting overall yield. Moreover, dry etching applies different loading to metal gates with different gate lengths, resulting in non-negligible differences in height and morphology between longer and shorter metal gates, impacting device performance. Figure 5 The diagram shows long gate and short gate structures. Finally, dry etching often uses fluorine-containing gases, such as CF4, which may cause F ions to penetrate the entire metal gate, resulting in electrical drift of the device.

[0044] Based on this, the core idea of ​​this invention is to use wet etching to etch the metal layer and control the height of each film layer, thereby avoiding the damage to the film layers caused by the use of plasma (especially etching gases containing C and F) in dry etching. Simultaneously, different chemicals can be used for stepwise wet etching to achieve precise control of the height of each film layer in the metal gate region, thus freely adjusting the device's electrical parameters. Furthermore, wet etching can control the etching rate by adjusting chemical concentration, temperature, wafer rotation speed, etc., thereby increasing the process window, controlling uniformity, and reducing the loading in each region.

[0045] For details, please refer to Figures 6-11 This is a schematic diagram of an embodiment of the present invention. Figure 6 As shown, a method for forming a metal grid includes:

[0046] A wafer with gate grooves formed within an insulating dielectric layer 20 on the wafer surface is provided;

[0047] A high-K gate dielectric layer 30, a work function layer 40, and a barrier layer 50 are sequentially deposited in the gate groove;

[0048] A metal layer 60 is filled in the gate groove where the barrier layer 50 is formed, such that the metal layer 60 is higher than the surface of the insulating dielectric layer 20 by a predetermined thickness.

[0049] Chemical mechanical polishing is used to remove the high-K gate dielectric layer 30 and other dielectric layers on the high-K gate dielectric layer 30 from the surface of the insulating dielectric layer 20, so that the metal layer 60 is approximately flush with the surface of the insulating dielectric layer 20.

[0050] The metal layer 60 and the barrier layer 50 in the gate groove are wet-etched back, so that the metal layer 60 in the gate groove is lower than the insulating dielectric layer 20 by a first preset height;

[0051] The work function layer 40 within the gate groove is wet-etched until it is approximately flush with the metal layer 60.

[0052] A one-step wet etching process is used to process the metal layer 60 and the barrier layer 50 to control the height of the metal gate. Then, the work function layer 40 is wet-etched separately to control its height, while retaining the high-k gate dielectric layer 30 on the sidewall of the gate recess. This wet etching method not only facilitates the adjustment and control of the heights of the metal gate and the work function layer 40, allowing engineers to freely adjust the parameters of both parts according to their needs, thus precisely controlling the electrical properties of the chip, but also avoids the damage to the film surface caused by plasma in traditional dry etching methods and the electrical changes caused by F ion penetration. Since the products and byproducts of wet etching are water-soluble, they do not affect the etching rate and efficiency. Furthermore, etching and cleaning can be completed in a single step, improving production efficiency and reducing costs.

[0053] First, a wafer with gate grooves formed in an insulating dielectric layer on the wafer surface is provided, and a metal layer 60 and a multilayer film material on its outer side are provided. Specifically, an insulating dielectric layer 20 with gate grooves is provided, wherein a high-K gate dielectric layer 30, a work function layer 40, a barrier layer 50 and a metal layer 60 are sequentially stacked in the gate grooves, including:

[0054] A substrate 10 is provided, on which an insulating dielectric layer 20 having a gate groove is formed;

[0055] The high-K gate dielectric layer 30, the work function layer 40, the barrier layer 50, and the metal layer 60 are sequentially deposited in the insulating dielectric layer 20 and the gate groove;

[0056] The metal layer 60 is thinned using a CMP process until the top surfaces of the high-K gate dielectric layer 30, the work function layer 40, the barrier layer 50, the metal layer 60, and the insulating dielectric layer 20 are flush.

[0057] like Figure 7 As shown, a preliminary film layer required for fabricating a metal gate is provided. The substrate 10 also has a source region 11 and a drain region 12. An insulating dielectric layer 20 is first formed on the substrate 10. The insulating dielectric layer 20 is then etched using a dry etching process to form a gate trench in the region between the source region 11 and the drain region 12. Next, a high-k gate dielectric layer 30, a work function layer 40, and a barrier layer 50 are sequentially deposited. Then, as shown... Figure 8 As shown, a metal layer 60 is deposited on the barrier layer 50, such as... Figure 9 As shown, the metal layer 60 is thinned using a CMP process until the top surfaces of the high-K gate dielectric layer 30, work function layer 40, barrier layer 50, and metal layer 60 are flush with the top surface of the insulating dielectric layer 20. The metal layer 60 contains at least tungsten, and the barrier layer 50 contains at least titanium.

[0058] In one embodiment, the high-k gate dielectric layer 30 is made of HfSiO2, and the insulating dielectric layer 20 is made of silicon oxide. The substrate 10 also has a source region 11 and a drain region 12, located on either side of the bottom of the gate trench. The material of the substrate 10 can include semiconductor materials, insulating materials, conductive materials, or any combination thereof; and the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The substrate 10 can also be, for example, a layered substrate of Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0059] Next, the metal layer 60 is wet-etched until a metal gate is formed, and the barrier layer 50 is simultaneously wet-etched, wherein the tungsten at the top of the metal layer 60 is converted into water-soluble tungstate, and the titanium at the top of the barrier layer 50 is converted into titanium oxide ions. Figure 10 As shown, the metal layer 60 and the barrier layer 50 are etched back using a first solution wet etching process. The first solution contains a predetermined proportion of NH4OH and H2O2. H2O2 oxidizes the tungsten metal, converting it into WO3, which then forms water-soluble tungstate under the action of NH4OH. Meanwhile, the titanium in the barrier layer 50 is oxidized by H2O2 to titanium oxide ions (TiO2). 2+ The NH4OH and H2O2 are thus removed by water. The etching rate can be controlled by adjusting the ratio of NH4OH and H2O2 to achieve different process requirements. The reaction equation is as follows:

[0060] W + 3H₂O₂ → WO₃ + 3H₂O

[0061] WO3 + 2NH4OH → (NH4)2WO4 + H2O

[0062] More preferably, the first solution is SC1 solution (standard cleaning solution 1). The classic chemical ratio of SC1 solution is: NH4OH (i.e., ammonia water NH3·H2O, usually 29%), H2O2 (hydrogen peroxide, usually 30%), and deionized water (DI water), with a classic volume ratio of NH4OH:H2O2:DI water = 1:1:5. SC1 solution can be used directly or diluted according to process requirements, which helps to reduce the number of operation steps.

[0063] In one embodiment, the barrier layer 50 is made of TiN.

[0064] It should be noted that after wet etching back the metal layer 60 and the barrier layer 50, the metal layer 60 and the barrier layer 50 are also cleaned to remove any residual first solution. For example, deionized water can be used to clean the entire wafer to prevent residual H2O2 from affecting the subsequent wet etching process.

[0065] In the second wet etching process, the work function layer 40 is wet-etched to its target height, and the etching products and byproducts are soluble in water. The work function layer 40 can be wet-etched using a dilute hydrochloric acid solution (D-HCl), where the hydrochloric acid solution has a mass fraction of less than 20%. The work function layer 40 is made of TiAl. Because H2O2 is absent, the etching rate for the metal layer 60 and the barrier layer 50 is extremely low, but a certain etching rate is observed for the TiAl compound. Therefore, the height of the work function layer 40 can be selectively controlled by adjusting the concentration and time of the dilute hydrochloric acid solution. The reaction equation is as follows:

[0066] 6HCl + 2Al → AlCl3 + 3H2

[0067] 6HCl + 2Ti → TiCl3 + 3H2

[0068] like Figure 11 As shown, the work function layer 40 is wet-etched until its top surface is flush with the metal layer 60. Here, the dilute hydrochloric acid solution etches the work function layer 40 separately, without consuming the high-k gate dielectric layer 30, the metal layer 60, and the barrier layer 50. This allows for individual adjustment of the height of the work function layer 40. The high-k gate dielectric layer 30 retained on the sidewall of the gate recess helps reduce the tunneling effect, and the etching products and byproducts are all water-soluble, facilitating post-etching cleaning.

[0069] The method for forming a metal gate provided by the present invention includes: providing an insulating dielectric layer 20 having a gate groove, wherein a high-K gate dielectric layer 30, a work function layer 40, a barrier layer 50, and a metal layer 60 are sequentially stacked in the gate groove, the top surfaces of the high-K gate dielectric layer 30, the work function layer 40, the barrier layer 50, the metal layer 60, and the insulating dielectric layer 20 are flush, the metal layer 60 contains at least tungsten, and the barrier layer 50 contains at least titanium; wet etching the metal layer 60 until a metal gate is formed, and simultaneously wet etching the barrier layer 50, wherein the tungsten at the top of the metal layer 60 is converted into water-soluble tungstate, and the titanium at the top of the barrier layer 50 is converted into titanium oxy ions; wet etching the work function layer 40 to a target height, and the etching products and byproducts are both water-soluble. Wet etching avoids the damage to the film surface caused by plasma in traditional dry etching, thus protecting the film's physicochemical properties. This method allows for separate high-precision control of the metal gate and work function layer 40, enabling engineers to freely adjust the parameters of both parts according to their needs, thereby precisely controlling the chip's electrical properties. Wet etching can control the etching rate by adjusting chemical concentration, temperature, and wafer rotation speed, thereby increasing the process window, regulating uniformity, and reducing the load on different areas of the wafer. The products and byproducts generated by wet etching are water-soluble and therefore do not affect the etching rate and efficiency. Furthermore, etching and cleaning can be completed in a single step, improving production efficiency and reducing costs. The SC1 and D-HCl used in wet etching do not contain F ions, thus avoiding electrical changes caused by F ion penetration.

[0070] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for forming a metal grid, characterized in that, include: Provides a wafer with gate grooves formed in the insulating dielectric layer on the wafer surface; A high-K gate dielectric layer, a work function layer, and a barrier layer are sequentially deposited within the gate groove; A metal layer is filled in the gate groove where the barrier layer is formed, such that the metal layer is higher than the surface of the insulating dielectric layer by a predetermined thickness. Chemical mechanical polishing is used to remove the high-K gate dielectric layer and other dielectric layers on the surface of the insulating dielectric layer, so that the metal layer is approximately flush with the surface of the insulating dielectric layer. The metal layer and the barrier layer inside the gate groove are wet-etched back, so that the metal layer inside the gate groove is lower than the insulating dielectric layer by a first preset height; The work function layer within the gate groove is wet-etched back to approximately flush with the metal layer.

2. The method for forming a metal grid according to claim 1, characterized in that, The metal layer and the barrier layer are etched back using a first solution wet etching process, wherein the first solution contains a predetermined ratio of NH4OH and H2O2.

3. The method for forming a metal grid according to claim 2, characterized in that, The first solution is an SC1 solution, which contains NH4OH, H2O2 and deionized water, and the volume ratio is NH4OH:H2O2:deionized water = 1:1:

5.

4. The method for forming a metal grid according to claim 2, characterized in that, After wet etching of the metal layer and the barrier layer, the metal layer and the barrier layer are further cleaned to remove any residual first solution.

5. The method for forming a metal grid according to claim 1, characterized in that, The work function layer was etched back using a hydrochloric acid solution with a mass fraction of less than 20% via a wet etching process.

6. The method for forming a metal grid according to claim 1, characterized in that, The metal layer contains at least tungsten.

7. The method for forming a metal grid according to claim 1, characterized in that, The barrier layer contains at least titanium.

8. The method for forming a metal grid according to claim 1, characterized in that, The work function layer is made of TiAl.

9. The method for forming a metal grid according to claim 1, characterized in that, The barrier layer is made of TiN.

10. The method for forming a metal grid according to claim 1, characterized in that, The high-K gate dielectric layer is made of HfSiO2.

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