Method of forming a semiconductor device

Abstract

The application provides a semiconductor device forming method, comprising the following steps: providing a substrate; forming a first material layer on the surface of the substrate; etching the first material layer to form a first recess in the first material layer; forming a sacrificial layer in the first recess; forming a second material layer on the surface of the first material layer and the sacrificial layer; etching the second material layer to form a second recess in the second material layer, and the bottom of the second recess exposes the top surface of the sacrificial layer; etching to remove the sacrificial layer, and the first recess and the second recess are communicated to form a deep trench; the morphology of the gate hole is well controlled, and the stable and controllable preparation of the high aspect ratio deep trench is facilitated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a semiconductor device. Background Technology

[0002] 3D NOR Flash memory devices, as a key technological path to overcome the storage density bottleneck of traditional planar NOR Flash, have achieved a significant increase in storage capacity per unit area through vertically stacked memory cell arrays. In this architecture, the gate hole, as the core structure connecting each layer of memory cells to the vertical channel, directly determines the electrical characteristics and operational reliability of the device through its morphology and dimensions (including aperture, sidewall roughness, bottom profile, and aspect ratio). Specifically, the bottom morphology of the gate hole directly affects the coupling efficiency between the gate and the channel, thereby regulating the threshold voltage (Vth) distribution, programming / erasing speed, and durability; the uniformity of the aperture is related to the consistency of the operating voltage of each cell in the array, and morphological deviations can easily lead to local electric field concentration, inducing early breakdown or charge retention failure.

[0003] Traditional gate hole fabrication primarily relies on dry etching techniques (such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching). However, with the increase in the number of 3D stacked layers, the etching depth increases significantly, exposing many limitations of dry etching in fabricating high aspect ratio hole structures. On the one hand, plasma transport within the hole is affected by the shielding effect, resulting in a non-uniform distribution of ion energy and free radical concentration along the depth direction. This leads to a reduced etching rate and distorted contours at the bottom of the hole, making it difficult to precisely control the bottom morphology (such as rounding, tilting, or residual polymer). On the other hand, the process window for sidewall passivation and bottom activation narrows sharply with increasing depth, making the micro-loading effect and aspect ratio-dependent etching (ARDE) phenomena increasingly significant. This deteriorates the dimensional uniformity of gate holes within the same wafer and between different batches.

[0004] Therefore, there is an urgent need for a semiconductor device fabrication method to improve the quality of gate via formation, which is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor device that can effectively control the morphology of the gate aperture, which is beneficial to the stable and controllable fabrication of high aspect ratio deep trenches.

[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate; forming a first material layer on the surface of the substrate; etching the first material layer to form a first trench within the first material layer; forming a sacrificial layer within the first trench; forming a second material layer on the surfaces of the first material layer and the sacrificial layer; etching the second material layer to form a second trench within the second material layer, wherein the bottom of the second trench exposes the top surface of the sacrificial layer; and etching away the sacrificial layer, wherein the first trench and the second trench are connected to form a deep trench.

[0007] Optionally, the first material layer and the second material layer are silicon epitaxial layers, and the first material layer and the second material layer are formed by epitaxial growth.

[0008] Optionally, the second groove is located above the first groove, and the projections of the first groove and the second groove on the substrate completely overlap.

[0009] Optionally, the material of the sacrificial layer is different from the materials of the first material layer and the second material layer, and the material of the sacrificial layer includes silicon germanium.

[0010] Optionally, after forming the second groove, the method further includes: forming the sacrificial layer within the second groove and planarizing it to be flush with the top surface of the second material layer; forming a third material layer on the surfaces of the second material layer and the sacrificial layer; etching the third material layer to form a third groove, the bottom of which exposes the surface of the sacrificial layer; the projections of the first groove, the second groove, and the third groove on the substrate coincide; and repeating the above steps at least once: forming and planarizing the sacrificial layer within the previous groove; forming a new material layer on the surfaces of the previous material layer and the sacrificial layer; etching the new material layer to form a new groove until the sacrificial layer within the previous groove is exposed, the projections of each groove on the substrate coincide; and removing the sacrificial layer within all grooves to form the deep trench.

[0011] Optionally, a gate structure is formed within the deep trench, the gate structure comprising a gate dielectric layer formed on the bottom and sidewall surfaces of the deep trench and a gate conductive layer formed on the surface of the gate dielectric layer.

[0012] Optionally, the gate dielectric layer includes a tunneling oxide layer formed on the sidewalls and bottom surface of the deep trench; a charge trapping layer formed on the surface of the tunneling oxide layer; and a barrier oxide layer formed on the surface of the charge trapping layer.

[0013] Optionally, the first material layer is a single layer or a stack. When the first material layer is a stack, the first material layer includes alternating stacked first semiconductor layers and second semiconductor layers, and the conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer.

[0014] Optionally, the second material layer is a single layer or a stack; when the second material layer is a stack, the second material layer includes alternately stacked third and fourth semiconductor layers, the conductivity type of the third semiconductor layer is opposite to that of the fourth semiconductor layer, and the conductivity type of the semiconductor layer in the second material layer that is in direct contact with the first material layer is opposite to that of the top semiconductor layer of the first material layer.

[0015] Optionally, it further includes: etching the first material layer and the second material layer to form a plurality of contact holes; forming plugs in the plurality of contact holes respectively, wherein the plugs are electrically connected to the corresponding first material layer or second material layer respectively.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages: In the semiconductor device formation method of the present invention, a first groove is first formed in the first material layer and a sacrificial layer is filled. Then, a second material layer is formed on the surface of the first material layer and the sacrificial layer, and a second groove is etched to expose the top of the sacrificial layer at the bottom of the second groove. Finally, the sacrificial layer is removed to achieve communication between the first groove and the second groove. This decomposes the traditional one-time deep trench etching into two shallow trench etchings, effectively reducing the aspect ratio of a single etching, avoiding the bottom morphology distortion problems caused by uneven bottom passivation, ion scattering and micro-loading effects commonly found in deep trench etching, significantly improving the bottom flatness and morphology consistency of the deep trench, and the process window of multiple shallow etchings is wider and the repeatability is better, which is conducive to the stable and controllable preparation of high aspect ratio deep trenches and has a wide range of applications. Attached Figure Description

[0017] Figures 1 to 8 This is a schematic diagram of the structure corresponding to the method for forming a semiconductor device according to the first embodiment of the present invention; Figures 9 to 18 This is a schematic diagram of the structure corresponding to the method for forming a semiconductor device according to the second embodiment of the present invention; Figures 19 to 25 This is a schematic diagram of the structure corresponding to the method for forming a semiconductor device according to the third embodiment of the present invention. Detailed Implementation

[0018] As mentioned in the background section, the bottom morphology of traditional gate holes is difficult to control and stably fabricated.

[0019] Through research, the inventors discovered that by first forming a first groove within a first material layer and filling it with a sacrificial layer, then forming a second material layer on the surface of the first material layer and the sacrificial layer, and finally etching a second groove, the bottom of the second groove is exposed above the top of the sacrificial layer. Finally, the sacrificial layer is removed to achieve communication between the first and second grooves. This decomposes the traditional one-time deep trench etching into two shallow trench etching processes, effectively reducing the aspect ratio of a single etching process. It avoids the common problems in deep trench etching, such as uneven bottom passivation, ion scattering, and micro-loading effects that cause bottom morphology distortion. It significantly improves the bottom flatness and morphology consistency of deep trenches. Furthermore, the process window for multiple shallow etching processes is wider and the repeatability is better, which is conducive to the stable and controllable preparation of high aspect ratio deep trenches and has a wider range of applications.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] First Embodiment

[0022] Please refer to Figure 1 Substrate 100 is provided.

[0023] In this embodiment, the substrate 100 is made of single-crystal silicon.

[0024] In other embodiments, the substrate 100 may also be made of polycrystalline silicon or amorphous silicon, germanium, silicon germanide, gallium arsenide, or other semiconductor materials.

[0025] Please refer to Figure 2 A first material layer 101 is formed on the surface of the substrate 100.

[0026] In this embodiment, an epitaxial growth process is used to form a first material layer 101 on the surface of the substrate 100.

[0027] In this embodiment, the first material layer 101 is a stack.

[0028] In this embodiment, the first material layer 101 includes an alternately stacked first semiconductor layer 1011 and a second semiconductor layer 1012, wherein the conductivity type of the first semiconductor layer 1011 is opposite to that of the second semiconductor layer 1012.

[0029] It should be noted that the first material layer 101 includes an alternately stacked first semiconductor layer 1011 and a second semiconductor layer 1012. The first material may include an alternately stacked first semiconductor layer 1011 and a second semiconductor layer 1012. Specifically, the first material layer 101 includes a first semiconductor layer 1011 formed on the surface of the substrate 100 and a second semiconductor layer 1012 formed on the surface of the first semiconductor layer 1011. Alternatively, the first material layer 101 may further include two alternately stacked first semiconductor layers 1011 and two second semiconductor layers 1012. Specifically, the first material layer 101 includes a first semiconductor layer 1011 formed on the surface of the substrate 100; a second semiconductor layer 1012 formed on the surface of the first semiconductor layer 1011; a first semiconductor layer 1011 formed on the surface of the second semiconductor layer 1012; and a second semiconductor layer 1012 formed on the surface of the first semiconductor layer 1011. Alternatively, the first material layer 101 may also include two alternately stacked first semiconductor layers 1011 and one second semiconductor layer 1012. Specifically, the first material layer 101 includes the first semiconductor layer 1011 formed on the surface of the substrate 100; the second semiconductor layer 1012 formed on the surface of the first semiconductor layer 1011; and the first semiconductor layer 1011 formed on the surface of the second semiconductor layer 1012. Of course, the first semiconductor layer 1011 and the second semiconductor layer 1012 can be stacked on top of each other according to actual design requirements, and are not limited to the example given.

[0030] In this embodiment, the first material layer 101 includes two alternately stacked first semiconductor layers 1011 and one second semiconductor layer 1012. Specifically, the first material layer 101 includes the first semiconductor layer 1011 formed on the surface of the substrate 100; the second semiconductor layer 1012 formed on the surface of the first semiconductor layer 1011; and the first semiconductor layer 1011 formed on the surface of the second semiconductor layer 1012.

[0031] In this embodiment, the first material layer 101 is a silicon epitaxial layer.

[0032] In this embodiment, the first semiconductor layer 1011 is doped with N-type ions, and the second semiconductor layer 1012 is doped with P-type ions.

[0033] Please refer to Figure 3 The first material layer 101 is etched to form a first groove 102 within the first material layer 101.

[0034] In this embodiment, the first groove 102 is formed using a dry etching process.

[0035] Please refer to Figure 4 A sacrificial layer 103 is formed in the first groove 102.

[0036] In this embodiment, the material of the sacrificial layer 103 includes silicon germanium.

[0037] Please refer to Figure 5 A second material layer 104 is formed on the surfaces of the first material layer 101 and the sacrificial layer 103.

[0038] In this embodiment, the second material layer 104 is formed using an epitaxial growth process.

[0039] In this embodiment, the second material layer 104 is an epitaxial silicon layer.

[0040] In this embodiment, the second material layer 104 is a stack, which includes the third semiconductor layer 1041 and the fourth semiconductor layer 1042 stacked alternately. The conductivity type of the third semiconductor layer 1041 is opposite to that of the fourth semiconductor layer 1042. The conductivity type of the semiconductor layer in the second material layer 104 that is in direct contact with the first material layer 101 is opposite to that of the top semiconductor layer of the first material layer 101.

[0041] It should be noted that the second material layer 104 includes an alternately stacked third semiconductor layer 1041 and a fourth semiconductor layer 1042. The second material layer 104 may include one alternately stacked third semiconductor layer 1041 and one alternately stacked fourth semiconductor layer 1042. Specifically, the second material layer 104 includes the third semiconductor layer 1041 formed on the surface of the first material layer 101 and the fourth semiconductor layer 1042 formed on the surface of the third semiconductor layer 1041. Alternatively, the second material layer 104 may further include two alternately stacked third semiconductor layers 1041 and two fourth semiconductor layers 1042. Specifically, the second material layer 104 includes the third semiconductor layer 1041 formed on the surface of the first material layer 101; the fourth semiconductor layer 1042 formed on the surface of the third semiconductor layer 1041; the third semiconductor layer 1041 formed on the surface of the fourth semiconductor layer 1042; and the fourth semiconductor layer 1042 formed on the surface of the third semiconductor layer 1041. Alternatively, the second material may include two alternately stacked layers of the third semiconductor layer 1041 and one layer of the fourth semiconductor layer 1042. Specifically, the second material layer 104 includes the third semiconductor layer 1041 formed on the surface of the first material layer 101; the fourth semiconductor layer 1042 formed on the surface of the third semiconductor layer 1041; and the third semiconductor layer 1041 formed on the surface of the fourth semiconductor layer 1042. Of course, the fourth semiconductor layer 1042 and the third semiconductor layer 1041 mentioned here can be stacked on top of each other according to actual design requirements, and are not limited to the example given.

[0042] In this embodiment, the second material layer 104 may include one layer of the third semiconductor layer 1041 and one layer of the fourth semiconductor layer 1042 stacked alternately. Specifically, the second material layer 104 includes the third semiconductor layer 1041 formed on the surface of the first material layer 101 and the fourth semiconductor layer 1042 formed on the surface of the third semiconductor layer 1041.

[0043] In this embodiment, the third semiconductor layer 1041 is doped with P-type ions, and the fourth semiconductor layer 1042 is doped with N-type ions.

[0044] Please refer to Figure 6 The second material layer 104 is etched to form a second groove 105 within the second material layer 104, the bottom of the second groove 105 exposing the top surface of the sacrificial layer 103.

[0045] Before etching the second material layer 104, a dielectric layer 108 is formed on the surface of the second material layer 104.

[0046] In this embodiment, the second groove 105 is located above the first groove 102, and the projections of the first groove 102 and the second groove 105 on the substrate 100 completely overlap.

[0047] In other embodiments, the second groove 105 is located above the first groove 102, and the projection of the first groove 102 on the substrate 100 may be located within the projection of the second groove 105 on the substrate 100; or the projection of the second groove 105 on the substrate 100 may be located within the projection of the first groove 102 on the substrate 100.

[0048] Please refer to Figure 7 The sacrificial layer 103 is removed by etching, and the first groove 102 and the second groove 105 are connected to form a deep trench 106.

[0049] In this embodiment, a wet etching process is used to remove the sacrificial layer 103 until the first groove 102 is exposed.

[0050] In this embodiment, the first groove 102 is first formed in the first material layer 101 and the sacrificial layer 103 is filled. Then, the second material layer 104 is epitaxially grown on the surface of the first material layer 101 and the sacrificial layer 103. Subsequently, the second material layer 104 is etched to form the second groove 105 and expose the top of the sacrificial layer 103 at the bottom of the second groove 105. Finally, the sacrificial layer 103 is selectively wet-removed to connect the first groove 102 and the second groove 105 to form the deep trench 106. This breaks down the traditional one-time deep trench etching into two steps. Shallow trench etching effectively reduces the aspect ratio of a single etching operation, avoiding the bottom morphology distortion problems caused by uneven bottom passivation, ion scattering, and micro-loading effects commonly seen in deep trench etching. At the same time, by using the top surface of the sacrificial layer 103 as the stop reference surface for the etching of the second groove 105, the bottom morphology of the deep trench 106 is precisely defined by the surface of the sacrificial layer 103 rather than depending on the etching time, which significantly improves the bottom flatness and morphology consistency. Furthermore, the process window for the two shallow etching operations is wider and the repeatability is better, which is conducive to the stable and controllable fabrication of the high aspect ratio deep trench 106.

[0051] Please refer to Figure 8 A gate structure 107 is formed in the deep trench 106. The gate structure 107 includes a gate dielectric layer 1071 formed on the bottom and sidewall surfaces of the deep trench 106 and a gate conductive layer 1072 formed on the surface of the gate dielectric layer 1071.

[0052] In this embodiment, the gate dielectric layer 1071 includes a tunneling oxide layer (not shown in the figure) formed on the sidewalls and bottom surface of the deep trench 106; a charge trapping layer (not shown in the figure) formed on the surface of the tunneling oxide layer; and a blocking oxide layer (not shown in the figure) formed on the surface of the charge trapping layer.

[0053] Please continue to refer to this. Figure 8 It also includes etching the first material layer 101 and the second material layer 104 to form a plurality of contact holes (not shown in the figure); and forming plugs 109 in the plurality of contact holes respectively, wherein the plugs 109 are electrically connected to the corresponding first material layer 101 or second material layer 104 respectively.

[0054] Second Embodiment

[0055] The difference between this embodiment and the first embodiment is that the first material layer 101 and the second material layer 104 are single layers.

[0056] Please refer to Figure 9 Substrate 200 is provided.

[0057] In this embodiment, the substrate 200 is made of single-crystal silicon.

[0058] In other embodiments, the substrate 200 may also be made of polycrystalline silicon or amorphous silicon, germanium, silicon germanide, gallium arsenide, or other semiconductor materials.

[0059] Please refer to Figure 10 A first material layer 201 is formed on the surface of the substrate 200.

[0060] In this embodiment, an epitaxial growth process is used to form a first material layer 201 on the surface of the substrate 200.

[0061] In this embodiment, the first material layer 201 is a single layer.

[0062] In this embodiment, the first material layer 201 is doped with N-type ions.

[0063] Please refer to Figure 11 The first material layer 201 is etched to form a first groove 202 within the first material layer 201.

[0064] In this embodiment, Please refer to Figure 12 A sacrificial layer 203 is formed in the first groove 202.

[0065] In this embodiment, the material of the sacrificial layer 203 includes silicon germanium.

[0066] Please refer to Figure 13 A second material layer 204 is formed on the surfaces of the first material layer 201 and the sacrificial layer 203.

[0067] In this embodiment, the second material layer 204 is formed using an epitaxial growth process.

[0068] In this embodiment, the second material layer 204 is an epitaxial silicon layer.

[0069] In this embodiment, the second material layer 204 is a single layer.

[0070] In this embodiment, the second material layer 204 is doped with P-type ions.

[0071] Please refer to Figure 14 The second material layer 204 is etched to form a second groove 208 within the second material layer 204, the bottom of the second groove 208 exposing the top surface of the sacrificial layer 203.

[0072] Please refer to Figure 15 The sacrificial layer 203 is formed in the second groove 208 and planarized to be flush with the top surface of the second material layer 204.

[0073] Please refer to Figure 16 A third material layer 205 is formed on the surface of the second material layer 204 and the sacrificial layer 203.

[0074] In this embodiment, the third material layer 205 is a stack, and the third material layer 205 includes a fifth semiconductor layer 2051 formed on the surface of the second material layer 204; a sixth semiconductor layer 2052 formed on the surface of the fifth semiconductor layer 2051; and a fifth semiconductor layer 2051 formed on the surface of the sixth semiconductor layer 2052.

[0075] Similarly, the number of the fifth semiconductor layer 2051 and the sixth semiconductor layer 2052 in the third material layer 205 can be selected according to the actual design requirements, and the arrangement pattern when the first material layer 201 is a stack can be referred to.

[0076] Wherein, the conductivity type of the first material layer 201 is opposite to that of the second material layer 204, the conductivity type of the semiconductor layer in the third material layer 205 that is in direct contact with the second material layer 204 is opposite to that of the second material layer 204, and the conductivity type of the semiconductor layers in adjacent layers within the third material layer 205 is opposite.

[0077] Specifically, the fifth semiconductor layer 2051 is doped with N-type ions, and the sixth semiconductor layer 2052 is doped with P-type ions.

[0078] Please refer to Figure 17 The third material layer 205 is etched to form a third groove 206, the bottom of which exposes the surface of the sacrificial layer 203.

[0079] The projections of the first groove 202, the second groove 208, and the third groove 206 on the substrate 200 coincide.

[0080] Please refer to Figure 18 The sacrificial layer 203 in the second groove 208 and the first groove 202 is removed by etching to form the deep trench 207.

[0081] After forming the deep trench 207, the process of forming the gate structure 107 and the plug is described in [reference needed]. Figure 8 .

[0082] Third Embodiment

[0083] For the process from providing the substrate 200 to forming the sacrificial layer 203 within the second recess 208 and planarizing it to be flush with the top surface of the second material layer 204, please refer to [reference needed]. Figures 9 to 15 .

[0084] Please refer to Figure 19 A third material layer 300 is formed on the surfaces of the second material layer 204 and the sacrificial layer 203.

[0085] In this embodiment, the third material layer 300 is a single layer.

[0086] Please refer to Figure 20 The third material layer 300 is etched to expose the sacrificial layer 203, and a third groove 306 is formed in the third material layer 300.

[0087] Please refer to Figure 21 The sacrificial layer 203 is formed in the third groove 306, and a fourth material layer 301 is formed on the surface of the third material layer 300 and the sacrificial layer 203.

[0088] Please refer to Figure 22 The fourth material layer 301 is etched to expose the surface of the sacrificial layer 203, and a fourth groove 302 is formed in the fourth material layer 301.

[0089] Please refer to Figure 23 The sacrificial layer 203 is formed in the fourth groove 302, and a fifth material layer 303 is formed on the surface of the fourth material layer 301 and the surface of the sacrificial layer 203.

[0090] Please refer to Figure 24 The fifth material layer 303 is etched to expose the sacrificial layer 203, and a fifth groove 304 is formed in the fifth sacrificial layer 203.

[0091] Please refer to Figure 25 Remove the sacrificial layer 203 to expose the bottom and sidewall surfaces of the first groove 202, forming a deep trench 305.

[0092] In this embodiment, the first material layer 201, the third material layer 300, and the fifth material layer 303 are doped with N-type ions; the second material layer 204 and the fourth material layer 301 are doped with P-type ions.

[0093] In this embodiment, after the second material layer 204 is formed, the process of forming and planarizing the sacrificial layer 203 in the previous groove is repeated three times, a new material layer is formed on the surface of the previous material layer and the sacrificial layer 203, and the new material layer is etched to form a new groove until the sacrificial layer 203 in the previous groove is exposed.

[0094] In other embodiments, the number of times the execution can be repeated can be selected according to actual design requirements, such as once, twice, etc.

[0095] After forming the deep trench 305, the process of forming the gate structure 107 and the plug is described in [reference needed]. Figure 8 .

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: Provide substrate; A first material layer is formed on the surface of the substrate; The first material layer is etched to form a first groove within the first material layer; A sacrificial layer is formed within the first groove; A second material layer is formed on the surfaces of the first material layer and the sacrificial layer; The second material layer is etched to form a second groove within the second material layer, the bottom of the second groove exposing the top surface of the sacrificial layer; The sacrificial layer is removed by etching, and the first groove and the second groove are connected to form a deep trench.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, The first material layer and the second material layer are silicon epitaxial layers, and the first material layer and the second material layer are formed by epitaxial growth.

3. The method for forming a semiconductor device as described in claim 1, characterized in that, The second groove is located above the first groove, and the projections of the first groove and the second groove on the substrate completely overlap.

4. The method for forming a semiconductor device as described in claim 1, characterized in that, The material of the sacrificial layer is different from the materials of the first material layer and the second material layer, and the material of the sacrificial layer includes silicon germanium.

5. The method for forming a semiconductor device as described in claim 1, characterized in that, After forming the second groove, the process also includes: The sacrificial layer is formed within the second groove and planarized to be flush with the top surface of the second material layer; A third material layer is formed on the surfaces of the second material layer and the sacrificial layer; The third material layer is etched to form a third groove, the bottom of which exposes the surface of the sacrificial layer; The projections of the first groove, the second groove, and the third groove on the substrate coincide; Following the steps above, repeat at least once: form a sacrificial layer in the previous groove and planarize it; form a new material layer on the surface of the previous material layer and the sacrificial layer; etch the new material layer to form a new groove until the sacrificial layer in the previous groove is exposed; and make the projections of each groove on the substrate coincide. Remove the sacrificial layer from all the grooves to form the deep trench.

6. The method for forming a semiconductor device as described in claim 1, characterized in that, A gate structure is formed within the deep trench, the gate structure comprising a gate dielectric layer formed on the bottom and sidewall surfaces of the deep trench and a gate conductive layer formed on the surface of the gate dielectric layer.

7. The method for forming a semiconductor device as described in claim 6, characterized in that, The gate dielectric layer includes a tunneling oxide layer formed on the sidewalls and bottom surface of the deep trench; a charge trapping layer formed on the surface of the tunneling oxide layer; and a barrier oxide layer formed on the surface of the charge trapping layer.

8. The method for forming a semiconductor device as described in claim 1, characterized in that, The first material layer is a single layer or a stack. When the first material layer is a stack, the first material layer includes alternating stacked first semiconductor layers and second semiconductor layers, and the conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer.

9. The method for forming a semiconductor device as described in claim 8, characterized in that, The second material layer is a single layer or a stacked layer; when the second material layer is a stacked layer, the second material layer includes an alternately stacked third semiconductor layer and a fourth semiconductor layer, the conductivity type of the third semiconductor layer is opposite to the conductivity type of the fourth semiconductor layer, and the conductivity type of the semiconductor layer in the second material layer that is in direct contact with the first material layer is opposite to the conductivity type of the top semiconductor layer of the first material layer.

10. The method for forming a semiconductor device as described in claim 9, characterized in that, Also includes: Etching the first material layer and the second material layer forms a plurality of contact holes; Inserts are formed in the plurality of contact holes, and the inserts are electrically connected to the corresponding first material layer or second material layer.

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