A power electronic assembly, power semiconductor assembly, high power density converter and intelligent computing chip system

Abstract

The application is directed to a high current density converter, comprising a capacitor and a power semiconductor assembly; the power semiconductor assembly comprises an upper switch, a lower switch, a direct current positive electrode, a direct current negative electrode and a jump electrode, and the upper switch and the lower switch are electrically connected to the jump electrode; on the one hand, by optimizing the structure of the power semiconductor assembly, the heat dissipation capacity of the converter is improved, the parasitic inductance of the input loop is reduced, and the current density of the power semiconductor assembly is improved; on the other hand, by optimizing the structure of the capacitor, the heat conduction capacity of the capacitor is improved, and by the structure of the multi-layer silicon capacitor stack, the heat dissipation capacity of the capacitor is improved, so that the high current density converter has the ability of double-sided heat dissipation, and the current density and conversion efficiency of the converter are improved.

Description

Technical Field

[0001] This invention belongs to the field of high-frequency power supply technology, and particularly relates to a power electronic component, a power semiconductor component, a high power density converter, and an intelligent computing chip system. Background Technology

[0002] In recent years, with the development of artificial intelligence, the power requirements of intelligent data processing chips, such as GPU / CPU / NPU / TPU (collectively referred to as XPU), have become increasingly higher. On the other hand, due to the increase in peripheral circuits of intelligent chips, the space left for power supply modules on the smart card motherboard is becoming smaller and smaller, which means that the demand for output current density per unit area of ​​the power supply module is becoming higher and higher.

[0003] In the existing technology, the three commonly used solutions are as follows: Figure 1 A, Figure 1 B and Figure 1 As shown in C. Figure 1 In scheme A shown in Figure A, the magnetic element Mag is positioned above the power semiconductor component IC. This structure is simple and low-cost; however, due to the poor heat dissipation of the power semiconductor component IC and the need for external capacitors in the converter, it occupies a significant amount of motherboard space. Although the converter itself can have a high current density, adding external capacitors significantly reduces the equivalent current density, sometimes by more than 30%, or even more. Figure 1 In scheme B, the power semiconductor component IC is placed above the magnetic component Mag, and the capacitors are located inside the converter. This structure provides a good heat dissipation path for the power semiconductor component and requires fewer external capacitors, allowing the converter's equivalent current density to be 130% or even higher than that of scheme A. However, due to parasitic inductance between the motherboard and the internal capacitors, and because the number or capacitance of the internal capacitors is limited, the parasitic inductance and the internal capacitors are prone to resonance, thus reducing the converter's performance and reliability. Figure 1 Scheme C, as shown in Figure C, places more capacitors between the magnetic components and the power semiconductor components, solving the resonance problem and achieving a higher current density in the converter. However, because the capacitors adjacent to the power semiconductor components and the magnetic components need to withstand high temperatures, MLCC (Multi-layer Ceramic Capacitors) with a temperature rating of 125 degrees Celsius, such as the X7R series, are required. This increases the cost of the converter and reduces the size of the magnetic components, further affecting the conversion efficiency of the converter.

[0004] This invention optimizes existing technologies, addresses their shortcomings, and achieves better converter performance, higher space utilization, lower manufacturing costs, and a simpler assembly process. Summary of the Invention

[0005] In view of this, one of the objectives of the present invention is to provide a power electronic component, characterized in that it comprises: a power semiconductor component; the power semiconductor component includes a bridge arm unit, a DC positive electrode, a DC negative electrode, and a switching electrode; the bridge arm unit includes an upper switch and a lower switch; the upper switch is electrically connected to the DC positive electrode and the switching electrode, and the lower switch is electrically connected to the DC negative electrode and the switching electrode; the power semiconductor component includes a top surface and a bottom surface opposite to each other, the DC positive electrode and the DC negative electrode are respectively disposed on the top surface and / or the bottom surface of the power semiconductor component; the switching electrode is disposed on the bottom surface of the power semiconductor component; a capacitor is disposed on the top surface of the power semiconductor component, the positive electrode of the capacitor is electrically connected to the DC positive electrode, and the negative electrode of the capacitor is electrically connected to the DC negative electrode; a wafer is used to assemble the bridge arm unit; a large-area thermal interface is disposed on the upper surface of the wafer, the area of ​​the large-area thermal interface is greater than or equal to 50% of the cross-sectional area of ​​the wafer; the large-area thermal interface is thermally connected to the capacitor.

[0006] Preferably, both the DC positive electrode and the DC negative electrode are disposed on the top surface of the power semiconductor component; the large-area thermal interface is electrically connected to the DC negative electrode.

[0007] Preferably, the DC negative electrode is disposed on the top surface of the power semiconductor component, and the DC positive electrode is disposed on the bottom surface of the power semiconductor component; the DC positive electrode is electrically connected to the positive electrode of the capacitor through a vertical channel; and the large-area thermal interface is electrically connected to the DC negative electrode.

[0008] Preferably, the chip is thermally connected to the capacitor through multiple small units.

[0009] Preferably, it also includes a large-area temperature equalization layer, which is disposed between the wafer and the multiple small cells.

[0010] Preferably, the number of capacitors located on the top surface of the power semiconductor component that have the same polarity as the electrodes disposed on the top surface of the power semiconductor component is greater than the number of capacitors that have different polarities from the electrodes disposed on the top surface of the power semiconductor component.

[0011] Preferably, a capacitor layer is disposed on the top surface of the power semiconductor component, the capacitor layer includes capacitors, and a thermally conductive insulating material is disposed between the capacitors.

[0012] Preferably, the capacitor is a ceramic capacitor, which includes multiple layers of metal sheets and multiple layers of ceramic sheets, wherein the metal sheets are arranged perpendicularly to the top surface of the power semiconductor component.

[0013] Preferably, the wafer includes a substrate and a wafer functional region, wherein the upper switch and the lower switch are disposed in the wafer functional region.

[0014] Preferably, the substrate is stacked on the upper surface of the wafer functional region; the substrate is at the same potential as the DC negative electrode; the upper surface of the substrate is provided with a DC negative electrode and / or a DC positive electrode, and the lower surface of the wafer functional region is provided with a switching electrode.

[0015] Preferably, the lower surface of the wafer functional area is further provided with a DC positive electrode and / or a DC negative electrode.

[0016] Preferably, the wafer functional regions are stacked on the upper surface of the substrate; the substrate and the switching electrode are at the same potential; a DC negative electrode and a DC positive electrode are disposed on the upper surface of the wafer functional regions, and a switching electrode is disposed on the lower surface of the substrate.

[0017] Preferably, the chip includes an upper switch chip and a lower switch chip, the lower switch chip being located above the upper switch chip, the upper surface of the lower switch chip having a DC negative electrode, and the lower surface of the upper switch chip having a DC positive electrode; a switching metal layer is disposed between the lower switch chip and the upper switch chip, and at least one end of the switching metal layer has a switching electrode; the lower switch chip is electrically connected to both the DC negative electrode and the switching electrode, and the upper switch chip is electrically connected to both the DC positive electrode and the switching electrode.

[0018] Preferably, the chip includes an upper switch chip and a lower switch chip, with the lower switch chip located above the upper switch chip; a DC positive electrode and a DC negative electrode are disposed on the top surface of the power semiconductor component, and a DC negative electrode and a switching electrode are disposed on the lower surface of the power semiconductor component; the lower switch chip includes a DC negative potential and a switching potential, and the upper switch chip includes a DC positive potential and a switching potential; the DC negative potential of the lower switch chip is led out to the top and bottom surfaces of the power semiconductor component through a metal layer and / or a vertical channel and electrically connected to the DC negative electrode; the DC positive potential of the upper switch chip is led out to the top surface of the power semiconductor component through a metal layer and / or a vertical channel and electrically connected to the DC positive electrode; the switching potentials of the upper switch chip and the lower switch chip are led out to the bottom surface of the power semiconductor component through a switching metal layer and electrically connected to the switching electrode.

[0019] Preferably, the chip includes an upper switch chip and a lower switch chip, which are arranged horizontally; the upper surface of the upper switch chip is electrically connected to a DC positive electrode, the upper surface of the lower switch chip is electrically connected to a DC negative electrode, and the lower surfaces of the upper switch chip and the lower surface of the lower switch chip are electrically connected to a switching electrode.

[0020] Preferably, the DC positive electrode and the DC negative electrode are disposed on the top surface of the power semiconductor component, and the switching electrode is disposed on the bottom surface of the power semiconductor component; the capacitors are arranged horizontally to form a capacitor layer, and at least two capacitor layers are stacked on the top surface of the power semiconductor component; the positive and negative electrodes of the capacitors respectively lead the DC positive and DC negative electrodes of the top surface of the power semiconductor component from the lower surface of the capacitor to the upper surface of the capacitor, the positive and negative electrodes of the lower layer capacitors correspond one-to-one with the positive and negative electrodes of the upper layer capacitors and are electrically connected, and the positive and negative electrodes of the uppermost layer capacitors and the switching electrode on the bottom surface of the power semiconductor component are external pins of the power electronic component.

[0021] Preferably, a connector is provided on the outside of the external connection pin, the external connection pin is led out to the connection surface through the connector, and the power electronic component is electrically connected to an external component through the connection surface.

[0022] Preferably, the connector is a metal sheet, which is achieved through welding or embedding processes.

[0023] Preferably, the capacitor is a silicon capacitor.

[0024] The present invention also provides a high current density converter, including a magnetic component and a power electronic component; the magnetic component is disposed on the lower surface of the power semiconductor component; the capacitor in the power electronic component is the high voltage side capacitor of the high current density converter.

[0025] Preferably, the magnetic component is a silicon wafer inductor; and the high-voltage side capacitor is a silicon capacitor.

[0026] Preferably, the silicon wafer inductor consists of two oppositely coupled inductors.

[0027] Preferably, a low-voltage side capacitor layer is stacked on the lower surface of the silicon wafer inductor, and a low-voltage side capacitor is disposed in the low-voltage side capacitor layer, wherein the low-voltage side capacitor is a silicon capacitor.

[0028] Preferably, the upper surface of the high current density converter is the input surface, and the input surface is provided with an input connection portion; the high voltage side capacitor layer is disposed adjacent to the input surface; the lower surface of the high current density converter is the output surface, and the output surface is provided with an output connection portion; the low voltage side capacitor layer is disposed adjacent to the output surface; the output surface is electrically connected to the upper surface of the load; the projections of the high current density converter and the load on the same horizontal plane at least partially overlap.

[0029] Preferably, a signal pin is disposed on the upper surface of the load; the lower surface of the output connection is flush with the bottom end of the signal pin, and the upper surface of the input connection is flush with the top end of the signal pin.

[0030] Preferably, the frequency of the high current density converter is higher than 10MHz.

[0031] Preferably, the device further includes a module carrier plate, wherein an input connection portion is provided on the upper surface of the module carrier plate and an output connection portion is provided on the lower surface of the module carrier plate; the high current density converter is embedded in the module carrier plate; the upper surface of the high current density converter is the input surface, which is electrically connected to the input connection portion through the module carrier plate; the lower surface of the high current density converter is the output surface, which is electrically connected to the output connection portion through the module carrier plate; the module carrier plate is electrically connected to the load through the output connection portion and supplies power to the load.

[0032] Preferably, the lower surface of the high current density converter is fixed to and electrically connected to the load, and a control chip is integrated on the load. The control chip is disposed adjacent to the high current density converter and is used to transmit information between the high current density converter and the load.

[0033] This invention provides an intelligent computing chip system, including a high current density converter and a load chip. The high current density converter and the load chip are stacked vertically, and their projections in the vertical direction at least partially overlap. The high current density converter includes an output capacitor layer, an inductor layer, a power semiconductor wafer layer, an input capacitor layer, and a converter input layer. The load chip, output capacitor layer, inductor layer, power semiconductor wafer layer, input capacitor layer, and converter input layer are arranged sequentially in the vertical direction. The frequency of the high current density converter is higher than 10MHz.

[0034] Preferably, both the input capacitor layer and the output capacitor layer are silicon capacitor layers, and the inductor layer is a silicon wafer inductor.

[0035] The present invention also provides a power semiconductor component, comprising: a wafer, the wafer including a substrate, an upper switching wafer region and a lower switching wafer region, the upper switching wafer region and the lower switching wafer region being horizontally distributed, the substrate being located above the upper switching wafer region and the lower switching wafer region; the upper switching wafer region including a DC potential and a switching potential, the lower switching wafer region including a DC potential and a switching potential; two electrode layers, the two electrode layers being an upper electrode layer disposed on the upper surface of the power semiconductor component and a lower electrode layer disposed on the lower surface of the power semiconductor component; an isolation layer, the isolation layer isolating the upper switching wafer region and the lower switching wafer region; an inner bus layer, the inner bus layer being used to lead the DC potential and switching potential of the wafer to the electrode layer; further comprising a DC positive electrode, a DC negative electrode and a switching electrode, the DC positive electrode, the DC negative electrode and the switching electrode being located on the electrode layer, the DC potential of the upper switching wafer being led to the DC positive electrode, the DC potential of the lower switching wafer region being led to the DC negative electrode, and the switching potential being led to the switching electrode.

[0036] Preferably, the isolation layer is "n"-shaped, with the upper switch wafer region located inside the isolation layer and the lower switch wafer region located outside the isolation layer.

[0037] Preferably, the inner bus layer is located below the wafer; the upper electrode layer is provided with a DC negative electrode, the lower electrode layer is provided with a switching electrode, and the DC positive electrode is provided in the upper electrode layer and / or the lower electrode layer; the DC potential and switching potential of the upper switching wafer region are led out to the inner bus layer through vias, and then led out to the DC positive electrode and the switching electrode through vias and / or conductive vias, respectively; the switching potential of the lower switching wafer region is led out to the inner bus layer through vias, and then led out to the switching electrode through vias; the DC potential of the lower switching wafer region is led out to the DC negative electrode through the substrate.

[0038] Preferably, the DC potential of the lower switch wafer region is led out to the DC negative electrode through a via provided above the substrate, or led out to the inner bus layer through a via and then led out to the DC negative electrode through a conductive via.

[0039] Preferably, the lower switching chip region includes a source region and a drain region. The source region includes an N+ buried layer, a P+ buried layer, and a P- buried layer. The source region is electrically connected to the DC negative electrode, and the drain region is electrically connected to the switching electrode.

[0040] Preferably, the substrate is a P+ substrate, the P+ buried layer is electrically connected to the DC negative electrode through the P+ substrate, the upper electrode layer is provided with a DC negative electrode, and the lower electrode layer is provided with a switching electrode and a DC positive electrode.

[0041] Preferably, a P epitaxial layer is further disposed between the P+ buried layer and the P+ substrate, and the P+ buried layer is electrically connected to the DC negative electrode through the P epitaxial layer and the P+ substrate.

[0042] Preferably, the lower electrode layer is provided with a DC negative electrode, and the area of ​​the DC negative electrode provided in the lower electrode layer is less than half the area of ​​the switching electrode; a GND wiring layer is provided on the lower surface of the source region, and the GND wiring layer is electrically connected to the DC negative electrode of the lower electrode layer through the inner bus layer.

[0043] Preferably, the substrate is an N+ substrate, and the N+ buried layer is electrically connected to the DC negative electrode through the N+ substrate; the upper electrode layer is provided with a DC negative electrode, and the lower electrode layer is provided with a switching electrode and a DC positive electrode.

[0044] Preferably, a buried via / groove is provided between the source region and the N+ substrate, and the source region is electrically connected to the N+ substrate through the buried via / groove.

[0045] Preferably, a GND wiring layer is disposed on the surface of the source region, the GND wiring layer extending outside the projection area of ​​the source region on the upper surface of the wafer, and the GND wiring layer outside the projection area is electrically connected to the N+ substrate through vias / grooves.

[0046] Preferably, a docking hole / groove is provided on the N+ substrate, and the docking hole / groove is electrically connected to the via / groove and the DC negative electrode, respectively.

[0047] Preferably, the N+ substrate includes an N+ substrate diffusion region, which extends from the upper surface of the N+ substrate to the upper surface of the wafer and is disposed adjacent to the upper switch wafer region; a bridge arm capacitor is integrated on the N+ substrate diffusion region, and the bridge arm capacitor is electrically connected to the DC positive terminal and the DC negative terminal nearby.

[0048] Preferably, the bridge arm capacitor includes a high-density deep trench, the surface of which is provided with a dielectric layer, and the interior of which is filled with tungsten or polycrystalline silicon.

[0049] Preferably, a plurality of buried vias / grooves are provided between the source region and the substrate, and a GND wiring layer is provided on the lower surface of the source region; at least one buried via / groove is electrically connected to the N+ substrate and the N+ buried layer, and at least another buried via / groove is electrically connected to the P+ buried layer, and the buried via / groove electrically connected to the P+ buried layer is electrically connected to the N+ buried layer through the GND wiring layer.

[0050] Preferably, an N+ electrical connection path is provided between the source region and the N+ substrate, and the N+ electrical connection path is realized through multiple epitaxy and multiple implantation.

[0051] Preferably, the N+ electrical connection path extends to the P+ buried layer and is electrically connected to the P+ buried layer.

[0052] Preferably, an N+ electrical connection path is provided between the source region and the N+ substrate. The N+ electrical connection path includes an implanted N+ layer and a buried via / trench. The source region is electrically connected to the N+ substrate in sequence through the buried via / trench and the implanted N+ layer.

[0053] Preferably, the substrate is an N+ substrate, the upper electrode layer is provided with a DC positive electrode, and the lower electrode layer is provided with a switching electrode and a DC negative electrode; the upper switch wafer region is provided with a vertical upper switch, the upper surface of the vertical upper switch includes a drain region, and the lower surface of the vertical upper switch includes a source region and a gate region; the drain region of the vertical upper switch is electrically connected to the DC positive electrode of the upper electrode layer through the N+ substrate; the source region of the vertical upper switch is electrically connected to the switching electrode through the inner bus layer.

[0054] Preferably, the lower electrode layer is also provided with a DC positive electrode, the area of ​​the DC positive electrode of the lower electrode layer is less than 50% of the area of ​​the switching electrode, and a high-frequency capacitor is provided between the DC positive electrode and the DC negative electrode of the lower electrode layer.

[0055] Preferably, the substrate is an N+ substrate, and both the upper and lower electrode layers are provided with switching electrodes. The lower electrode layer is also provided with a DC positive electrode and a DC negative electrode. The upper switch wafer region is provided with a planar upper switch, and the lower switch wafer region is provided with a vertical lower switch. The upper surface of the vertical lower switch includes a drain region, and the lower surface of the vertical lower switch includes a source region and a gate region. The drain region of the vertical lower switch is electrically connected to the switching electrode of the upper electrode layer through the N+ substrate, and the source region of the vertical lower switch is electrically connected to the DC negative electrode. The source region, drain region, and gate region of the planar upper switch are all disposed on the lower surface of the upper switch wafer region. The drain region of the planar upper switch is electrically connected to the DC electrode through the inner bus layer. The source region of the planar upper switch is electrically connected to the switching electrode located on the lower electrode layer through the inner bus layer, and the switching electrode located on the lower electrode layer is electrically connected to the switching electrode located on the upper electrode layer through a through-silicon via or a buried via / groove.

[0056] Preferably, the lower switching wafer region includes a source region and a drain region. The source region includes an N+ buried layer and a P- buried layer. A buried via / groove is disposed between the source region and the substrate. One end of the buried via / groove is electrically connected to the N+ buried layer. A parasitic diode is disposed between the source region and the drain region. The conductive path of the parasitic diode is formed by direct electrical connection between the buried via / groove and the P- buried layer.

[0057] The present invention also provides a high current density converter, comprising: a power semiconductor component, a high voltage end and a low voltage end; a magnetic component, the magnetic component including a magnetic core and a winding, one end of the winding being electrically connected to the switching electrode, and the other end of the winding being electrically connected to the high voltage end or the low voltage end; and a capacitor disposed adjacent to the power semiconductor component and electrically connected to the DC positive terminal and the DC negative terminal.

[0058] Preferably, the system includes a first carrier plate, which has an upper surface and a lower surface opposite to each other; the magnetic component is disposed on the upper surface of the first carrier plate, and both ends of the winding are fixed to the upper surface of the first carrier plate and electrically connected to the switching electrode and the high-voltage end or the low-voltage end through the first carrier plate.

[0059] Preferably, the capacitor is disposed on the upper surface of the first carrier plate, and an accommodating space is formed between the magnetic core, the winding and the upper surface of the first carrier plate, with the capacitor located within the accommodating space.

[0060] Preferably, the power semiconductor component is disposed on the lower surface of the first carrier plate, and the top surface of the power semiconductor component is fixed and electrically connected to the lower surface of the first carrier plate; the power semiconductor component and the lower surface of the first carrier plate are encapsulated with molding compound to form a molded body, and the DC negative electrode is disposed on the bottom surface of the power semiconductor component and exposed outside the molded body.

[0061] Preferably, a carrier plate connection end is provided within the molding compound, the carrier plate connection end being used for transmitting signals and / or power.

[0062] Preferably, the carrier plate connection end is a conductive post.

[0063] Preferably, a window is provided on the lower surface of the encapsulation, and the carrier board connection end is formed by setting solder balls or metallized windows in the window.

[0064] Preferably, the capacitor is disposed on the lower surface of the first carrier plate and located within the encapsulation.

[0065] Preferably, the capacitor and power conductor assembly are embedded in the first carrier plate and electrically connected to external components through the first carrier plate.

[0066] Preferably, the device further includes a capacitor carrier plate, in which the capacitor is embedded, the high current density converter is electrically connected to external components through the lower surface of the capacitor carrier plate, and the upper surface of the capacitor carrier plate is electrically connected to the power semiconductor component and / or the magnetic component and / or the lower surface of the first carrier plate.

[0067] Preferably, the DC negative electrode is disposed on the upper surface of the power semiconductor component; the DC positive electrode and the switching electrode are disposed on the lower surface of the power semiconductor component; it also includes a DC negative electrode conductive strip, through which the DC negative electrode of the power semiconductor component is electrically connected to the upper surface of the first carrier plate; the lower surface of the power semiconductor component is fixed and electrically connected to the upper surface of the carrier plate; the magnetic component is disposed on the lower surface of the first carrier plate, and the capacitor is disposed on the upper surface and / or the lower surface of the first carrier plate.

[0068] Preferably, it also includes a semiconductor substrate, wherein the power semiconductor component is disposed on the semiconductor substrate and encapsulated integrally with a molding compound, or the power semiconductor component is embedded in the semiconductor substrate, and the power semiconductor component is assembled on the upper surface of the semiconductor substrate through the semiconductor substrate.

[0069] Preferably, it also includes a power connector, a signal connector, and a second carrier board, wherein the two ends of the power connector, the signal connector, and the winding are electrically connected to the lower surface of the first carrier board and the upper surface of the second carrier board, respectively.

[0070] The present invention also provides a high current density converter, comprising: a high voltage end and a low voltage end; a first carrier plate, the first carrier plate including opposing upper and lower surfaces; a power semiconductor assembly, the power semiconductor assembly including opposing upper and lower surfaces, an electrode assembly, a DC negative electrode, a bridge arm unit, a wafer, and a bridge arm capacitor; the electrode assembly including a DC positive electrode, a switching electrode, and / or a DC negative electrode; the bridge arm unit including an upper switch and a lower switch; the upper switch and the lower switch are disposed on the wafer; the upper switch is electrically connected to the DC positive electrode and the switching electrode, and the lower switch is electrically connected to the DC negative electrode. Negative and switching electrodes; the bridge arm capacitor is disposed above the wafer, the positive terminal of the bridge arm capacitor is electrically connected to the DC positive terminal, and the negative terminal of the bridge arm capacitor is electrically connected to the DC negative terminal; the bridge arm capacitor absorbs at least 50% of the AC component in the bridge arm unit; a magnetic component, the magnetic component including a magnetic core and a winding, one end of the winding being electrically connected to the switching electrode, and the other end of the winding being electrically connected to the high voltage terminal or the low voltage terminal; a DC-side capacitor, the DC-side capacitor being disposed adjacent to the power semiconductor component and electrically connected to the DC positive and DC negative terminals.

[0071] Preferably, the magnetic component is disposed on the upper surface of the first carrier plate, both ends of the winding are fixed to the upper surface of the first carrier plate and electrically connected to the switching electrode and the high-voltage end or the low-voltage end through the first carrier plate; the DC-side capacitor is disposed on the upper surface and / or the lower surface of the first carrier plate; and the power semiconductor component is disposed on the lower surface of the first carrier plate.

[0072] Preferably, it also includes a DC-side capacitor carrier plate, wherein the DC-side capacitor is embedded in the DC-side capacitor carrier plate, the high current density converter is electrically connected to external components through the lower surface of the DC-side capacitor carrier plate, and the upper surface of the DC-side capacitor carrier plate is electrically connected to the power semiconductor component and / or the magnetic component and / or the lower surface of the carrier plate.

[0073] Preferably, the DC negative electrode is disposed on the upper surface of the power semiconductor component, and the electrode assembly is disposed on the lower surface of the power semiconductor component. It also includes a DC negative electrode conductive strip, through which the DC negative electrode of the power semiconductor component is electrically connected to the upper surface of the first carrier plate; the lower surface of the power semiconductor component is fixed and electrically connected to the upper surface of the first carrier plate; the magnetic component is disposed on the lower surface of the first carrier plate; and the DC side capacitor is disposed on the upper and / or lower surface of the first carrier plate.

[0074] The beneficial effects of this invention are: (1) The present invention proposes a power electronic component, which improves the thermal conductivity of the capacitor and the heat dissipation capacity of the component by optimizing the structure of the power electronic component and reducing the parasitic inductance of the input circuit; (2) On the other hand, by optimizing the process and structure of the high current density converter and by using the multilayer silicon capacitor stacking structure, the heat dissipation capacity of the capacitor is improved, thereby enabling the power module to have ultra-thin, double-sided heat dissipation capability, thereby further improving the current density and conversion efficiency of the converter. Attached Figure Description

[0075] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0076] Figure 1 This is existing technology; Figure 2 It is a high current density converter; Figure 3 A schematic diagram of the circuit topology used in the converter; Figure 4A and Figure 4B This is the structure of a power electronic component; Figure 5A and Figure 5B This is the structure of another type of power electronic component; Figures 6A to 6H This is an extended embodiment of a power electronic component; Figures 7A to 7E A schematic diagram of another monocrystalline double-sided electrode is shown; Figures 8A to 8I A schematic diagram of another monocrystalline double-sided electrode is shown; Figures 9A to 9E A side cross-sectional schematic diagram of a converter using the aforementioned power semiconductor components is shown; Figure 9F1 and Figure 9F2 This describes the implementation methods for the power and signal terminals of the converter; Figure 10A This is a side cross-sectional view of the internal structure of a traditional capacitor. Figure 10B This is a side sectional view of the internal structure of a novel capacitor; Figure 11A and Figure 11B This is a schematic diagram of the power electronic component structure; Figure 11C This is a schematic diagram of an extended structure of the converter; Figures 12A to 12C This is a schematic diagram of a converter structure; Figures 13A to 13C This is a schematic diagram of the system structure; Figures 14A to 14C A schematic diagram of another monocrystalline double-sided electrode is shown. Detailed Implementation

[0077] One of the core aspects of this invention is to provide a power electronic component, a power semiconductor component, an ultra-high current density converter, and an intelligent computing chip system.

[0078] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0079] like Figure 2As shown, this invention relates to a high current density converter, which includes a magnetic element, a power semiconductor component, and a capacitor. The converter's output pin is located below the magnetic element, the power semiconductor component is positioned above the magnetic element, and the capacitor is positioned above the power semiconductor component. More than 50% of the heat generated by the power semiconductor component is dissipated to the outside through the capacitor. The winding of the magnetic element is electrically connected to the power semiconductor component; a signal connector is provided on the side of the magnetic element for signal transmission between the power semiconductor component and external components. The portion consisting of the power semiconductor component and the capacitor positioned above the magnetic element is defined as the top component, and the portion consisting of the magnetic element and the signal connector is defined as the middle component. Theoretically, the surface area occupied by the converter on the motherboard shown in this invention can be similar to the cross-sectional area of ​​the power semiconductor component, thereby maximizing the current density of the converter. For example, the cross-sectional area of ​​a current 90A-level power semiconductor component is approximately 15mm². 2 The current density is approximately 6 A / mm². 2 The converter shown in this invention can achieve a current density greater than or equal to 5 A / mm². 2 Much greater than 1 A / mm 2 This is a current technology. Furthermore, the capacitors are positioned on the top surface of the module, closest to the heatsink vertically, resulting in low capacitor temperatures. Therefore, low-temperature, high-capacity capacitors can be used, such as 105°C-level MLCC capacitors (e.g., the S6 series); or even 85°C-level MLCC capacitors (e.g., the X5R series). Using low-temperature capacitors can increase capacitance by 30% or more. Moreover, using a single layer of capacitors on the top surface of the converter effectively balances capacitance and high thermal conductivity; this reduces the risk of input circuit oscillation and allows for larger input circuits, thus providing more possibilities for structural design.

[0080] Figure 3This is a schematic diagram of the circuit topology used in the converter, where the active devices are typically connected as bridge arm units. Each bridge arm unit includes an upper switch QH and a lower switch QL, which are connected in series. Therefore, each bridge arm unit includes three power electrodes: a DC positive electrode DC+ (or Vin), a switching electrode SW, and a DC negative electrode DC- (or GND). The potentials of the DC positive and DC negative electrodes DC+ and DC- are relatively stable and can be considered as DC potentials; the switching electrode SW is an AC potential, and the switching frequency of this AC potential is typically higher than 100kHz, and can even reach MHz. A high-frequency decoupling capacitor Cbus (also called a bridge arm capacitor) is connected between DC+ and DC- to reduce the input loop inductance Lloop and lower the voltage stress on the power semiconductor components during high-frequency switching. The bridge arm capacitor can absorb at least 50% of the AC component in the bridge arm current. When this invention is applied to a common buck converter, the DC positive terminal (DC+) is connected to the positive input terminal (Vin) of the buck circuit, and the DC negative terminal (DC-) is connected to the negative input terminal (GND) of the buck circuit. Here, the high-frequency decoupling capacitor (Cbus) is the input capacitor (Cin); the magnetic component is the inductor (L). In practical applications, the converter also includes an output capacitor (Co), which can be integrated into the converter or placed outside the converter.

[0081] Taking its application in a buck circuit as an example, this invention details one inventive aspect: the capacitor C (corresponding to the input capacitor in the buck circuit) is positioned on top of the power semiconductor component to help dissipate heat generated by the power semiconductor component. Figure 4 is a side sectional view of the top component. As shown in Figure 4, the power semiconductor component 10 here includes at least one... Figure 3 The bridge arm unit in the power semiconductor component 10, which includes at least one set of upper switch QH and lower switch QL connected in series, is referred to simply as IC. To improve the integration of the converter, at least two Buck circuits are usually used in parallel, meaning the converter includes at least two bridge arm units IC. The following explanation will use this as an example.

[0082] In this embodiment, one of two DC potentials, such as electrode GND, is provided on the upper surface of the power semiconductor component 10; the DC positive electrode Vin and the switching electrode SW are provided on the lower surface of the power semiconductor component 10. A capacitor C is provided above the power semiconductor component 10, forming a capacitor layer 20; and the negative electrode of capacitor C is connected to the DC negative electrode GND through soldering or electroplating to achieve low thermal resistance. The DC positive electrode Vin is electrically connected to capacitor C through a vertical channel 101 (such as a via or an internal metal pillar), which is located adjacent to one side of the power semiconductor component 10; additionally, a large-area thermal interface 102 is provided on the upper surface of the bridge arm unit IC to facilitate thermal connection with capacitor C; and the bridge arm unit IC is electrically connected to capacitor C through the large-area thermal interface 102. In this embodiment, only one power semiconductor component 10 is used as an example for the packaging structure description. In other embodiments, multiple power semiconductor components 10 can be combined and packaged together, all using the packaging structure described above, and achieving the same technical benefits.

[0083] At least two electrodes are disposed on the upper surface of the power semiconductor component 10. One of the two electrodes can be at the same potential as the large-area thermal interface 102, for example, at the same potential as the DC negative terminal GND; both electrodes can also be at the same potential as the large-area thermal interface 102. The area of ​​the large-area thermal interface 102 is greater than or equal to 50% of the wafer cross-sectional area, and preferably even reaches 80%, thereby reducing the vertical thermal resistance. On the other hand, because the cross-sectional area of ​​the capacitor C is smaller than the cross-sectional area of ​​the bridge arm unit IC, that is, the two electrodes corresponding to the capacitor above the bridge arm unit IC, but the large-area thermal interface 102 is only one of the two electrodes, in the actual structure, the bridge arm unit IC is thermally connected to the capacitor C through multiple GND small units (i.e., thermal vias). Therefore, a large-area heat spreader 103 is disposed in the gap between the two thermal vias to achieve lateral heat spreader. This large-area heat spreader 103 can be a metal layer, such as a copper layer. (Refer to...) Figure 4B The heat flow diagram shown illustrates that the heat generated by the bridge arm unit IC is transferred to the large-area heat spreader 103, then through thermally conductive holes to the bottom of the electrodes of capacitor C, and then through the capacitor C body to the upper surface of capacitor C, before being dissipated directly or indirectly to the outside. Preferably, thermally conductive insulating material 201 is filled between capacitors C, allowing the heat from multiple GND small units to also dissipate to the outside through the thermally conductive insulating material 201.

[0084] To achieve better heat dissipation, the number of electrodes of capacitor C above the power semiconductor component 10 that have the same polarity as the electrodes on the upper surface of the power semiconductor component 10 is greater than the number of electrodes of capacitor C that have different polarity from the electrodes on the upper surface of the power semiconductor component 10. Figure 4A and Figure 4BThe structure shown is simple, but only one electrode of capacitor C is the main interface for heat transfer, and the other electrode does not fully play the role of heat transfer. On the other hand, the DC positive electrode Vin needs to go around from the side of the bridge arm unit IC to capacitor C, the power transmission path is long, and the path length to different capacitors C is different, which makes the current flowing into capacitor C different.

[0085] Figure 5A and Figure 5B Another structure is shown. In this embodiment, both the DC positive electrode Vin and the DC negative electrode GND are disposed on the upper surface of the power semiconductor component 10, and the switching electrode SW is disposed on the lower surface of the power semiconductor component 10. Both electrodes of the capacitor C can serve as the main heat dissipation channels, which significantly improves the heat dissipation effect; and a low-loop electrical connection is achieved between the two DC electrodes and the capacitor C.

[0086] Figures 6A to 6C for Figure 4A and Figure 4B The illustrated extended embodiments show that the DC negative electrode GND is disposed on the upper surface of the power semiconductor component and serves as the main thermal interface. Figure 6A and Figure 6B The power semiconductor component in this device uses a single wafer, meaning the upper switch QH and lower switch QL are integrated on a single wafer using monolithic technology (the device is typically planar, such as LDMOS, CMOS, GaN, etc.). This wafer includes a substrate 111, which is over 10 μm thick and set to GND potential. The upper switch QH and lower switch QL (i.e., bridge arm unit ICs) are located in the wafer functional region 112, which is adjacent to the lower surface of the power semiconductor component 10 and typically has a thickness in the micrometer or even hundreds of nanometer range. Taking silicon devices as an example, the thermal conductivity of a silicon wafer can be greater than 100 W / m•K; if the silicon wafer is 100 μm thick and has an area of ​​10 mm²... 2 Therefore, the upward thermal resistance of the silicon wafer is less than 0.1 K / W, which is almost negligible. For example... Figure 6A As shown, a DC negative electrode GND is disposed on the upper surface adjacent to the power semiconductor component 10, and a DC positive electrode Vin, a DC negative electrode GND, and a switching electrode SW are disposed on the lower surface adjacent to the power semiconductor component 10. The DC negative electrode GND disposed adjacent to the upper surface mainly serves as a heat dissipation interface, and most of the current flowing through the bridge arm unit or the three power electrodes passes through the lower surface of the wafer. Figure 6BAs shown, the DC negative electrode GND, located near the upper surface, serves as both a heat dissipation interface and a main current interface; the DC positive electrode Vin and the switching electrode SW are located on the lower surface of the chip; both the upper and lower surfaces of the chip serve as electrical packaging interfaces, which can reduce the equivalent resistance of the internal wiring layers of the IC chip by more than 20%; this is suitable for applications with higher operating currents. In this embodiment, only two electrodes may be provided on the lower surface of the IC chip, but it is not limited to this. Figure 6C As shown, the IC chip is a multi-chip design, with the upper switch QH and the lower switch QL mounted on separate chips (typically vertical devices such as Optimos and SiC). The areas of the two chips can be equal or unequal. When used in a buck circuit, the area of ​​the lower switch chip 112QL is typically larger than that of the upper switch chip 112QH. The lower switch chip 112QL is stacked on top of the upper switch chip 112QH; the upper surface of the lower switch chip 112QL is the DC negative electrode GND, and its lower surface is the switching electrode SW; the upper surface of the upper switch chip 112QH is the switching electrode SW, and its lower surface is the DC positive electrode Vin; a metal layer 113 SW is placed between the two chips, guiding the SW electrode to one or more sides of the chip. This achieves high current density and excellent heat dissipation in the power semiconductor device. A bridge arm capacitor can be placed above the chips, which can absorb at least 50% of the AC component of the bridge arm current.

[0087] Figure 6D for Figure 6C Extended embodiments, Figure 6E for Figure 6D Cross-sectional views of lines A-A' and B-B'. (See diagram.) Figure 6D and 6E As shown, the positive DC potential located on the lower surface of the upper switching chip 112QH is led out to the upper surface of the power semiconductor device through a metal layer (horizontal direction) and a Vin vertical channel, forming a positive DC electrode Vin; the negative DC potential located on the upper surface of the lower switching chip 112QL is led out to the lower surface of the power semiconductor device through a metal layer and a GND vertical channel, forming a negative DC electrode GND, and simultaneously led out to the upper surface of the power semiconductor device through a large-area metal layer, forming a large-area negative DC electrode GND (large-area thermal interface); the switching potentials on the lower surface of the lower switching chip and the upper surface of the upper switching chip are led out to the lower surface of the power semiconductor device through the SW metal layer and the SW and SW vertical channels, forming a switching electrode SW. Therefore, in Figure 6D In the power semiconductor component shown, the upper surface has a DC positive electrode Vin and a DC negative electrode GND for easy connection to the capacitor C, achieving a low-loop connection; the lower surface has a switching electrode SW and a DC negative electrode GND to optimize heat dissipation and conductivity. Figure 6EAs shown, alternating the GND vertical channel and Vin vertical channel can reduce the parasitic inductance of the loop.

[0088] Figures 6F to 6H for Figure 5A and Figure 5B In the extended embodiments shown, the DC positive electrode Vin and the DC negative electrode GND are disposed on the upper surface of the power semiconductor component 10, and the switching electrode SW is disposed on its lower surface. The DC positive electrode Vin and the DC negative electrode GND disposed on the upper surface are not only the electrical connection interface between the two electrodes, but also the main thermal conductivity interface. Figure 6F and Figure 6G The power semiconductor components in the system use single-chip wafers. For example... Figure 6F As shown, the wafer functional region 112 is located adjacent to the upper surface of the power semiconductor component 10, and two DC electrodes are pulled out through the surface wiring layer; the wafer substrate 111 is at a switching potential. The advantage of this layout is that the three power electrodes can achieve the same current density, thereby achieving minimum package resistance. The disadvantage is that the wafer substrate is at a switching potential, which can easily affect the operation of the wafer logic region, affecting high-precision control or sampling. Figure 6G The wafer substrate 111 remains at a DC potential. The wafer substrate 111 is electrically and thermally connected to the DC electrode. Another DC electrode penetrates the wafer substrate 111 through a conductive via (such as TSV technology) and is electrically connected to another DC electrode, thereby enabling two DC electrodes to be on the same surface of the power semiconductor component 10. In other embodiments, the two DC electrodes can also be electrically connected to the wafer functional region 112 through vias. Figure 6H As a multi-chip IC, the upper switch chip 112QH and the lower switch chip 112QL are arranged horizontally and are both electrically connected to the switching electrode SW located on the lower surface. The upper switch chip 112QH is electrically connected to the DC positive electrode Vin on the upper surface, and the lower switch chip 112QL is electrically connected to the DC negative electrode GND on the upper surface. This structure is simple and easy to implement, and has low thermal resistance. The heat generated in the functional semiconductor component can be dissipated through the electrodes on the upper and lower surfaces.

[0089] Figures 7A to 7E A schematic diagram of a double-sided electrode for a power semiconductor component is shown. (As shown) Figure 7AAs shown, the power semiconductor component 10 includes a substrate 111, an inner bus layer 115, two electrode layers, an upper switching chip 112QH, a lower switching chip 112QL, an isolation layer 114, and multiple conductive vias Via. In this embodiment, the isolation layer 114 is n-shaped and is disposed adjacent to the lower surface of the substrate 111, dividing the substrate 111 into two independent regions. The upper switching chip 112QH is disposed below the isolation layer 114; the lower switching chip 112QL is disposed in the independent region outside the isolation layer 114; wherein both the upper switching chip 112QH and the lower switching chip 112QL are disposed adjacent to the lower surface of the substrate 111. The DC positive potential and switching potential of the upper switching chip 112QH are converged to the inner bus layer 115 through Via, and then connected to the DC positive electrode Vin and the switching electrode SW through Via. The switching potential of the lower switching chip 112QL is converged to the inner bus layer 115 via Via, and then connected to the switching electrode SW via Via. The DC negative potential of the lower switching chip 112QL is led upward through the substrate and electrically connected to the DC negative electrode GND. In this embodiment, the DC electrode of the lower switching chip 112QL hardly occupies the wiring layer resources below the chip, reducing the equivalent resistance of the wiring layer by more than 20%, and even more than 40%. For low-voltage devices where the equivalent resistance of the wiring layer accounts for 30% of the total impedance, the current density of the chip can be increased by more than 10%. In addition, in order to reduce the loss on the path of current transmission to the DC negative electrode GND, the substrate 111 can use a high concentration of doping, so that the resistivity of the substrate is less than 1 mΩ•cm, and even less than 0.7 mΩ•cm. The thickness of the substrate 111 should be thinner than 50 μm, and even thinner than 30 μm, so that the equivalent resistance of the substrate 111 can be further less than 0.1 mΩ, which is suitable for high-current applications. In this embodiment, both the DC positive electrode Vin and the switching electrode SW are connected to the lower surface electrode through the surface conductive hole Via. This structure has a simple manufacturing process and low cost.

[0090] Figure 7B and Figure 7A The difference lies in the fact that the switching potential of the upper switching chip 112QH is led out to the lower surface of the chip, where it merges with the switching potential of the lower switching chip 112QL, which is also led out to the lower surface, to form the switching electrode SW. The DC potential of the upper switching chip 112QH penetrates the substrate 111 through the conductive via TSV and is led to the upper surface of the power semiconductor component 10 to form the DC positive electrode Vin; the DC potential of the lower switching chip 112QL is led to the upper surface to form the DC negative electrode GND. The DC positive electrode Vin and the DC negative electrode GND are connected to the two ends of the capacitor C, which reduces the size of the capacitor Lloop circuit and increases the current density of the power semiconductor component by more than 20%.

[0091] Figure 7CIn the embodiment shown, the power semiconductor component 10 includes more upper switching chips 112QH and lower switching chips 112QL; on the one hand, this allows the power semiconductor component 10 to further reduce the loop inductance within the same size, making it suitable for higher frequency applications, such as frequencies above 2MHz, or even operating at 10MHz; on the other hand, at the same frequency, the chips can obtain a larger area, thereby increasing the current density of the power semiconductor component by more than 20%.

[0092] Figure 7D and Figure 7E In the illustrated embodiment, the DC negative electrode GND disposed on the upper surface of the power semiconductor component 10 can be electrically connected to the DC negative electrode disposed on the lower surface of the lower switch chip 112QL through a conductive via (such as TSV technology) penetrating the wafer substrate 111. Furthermore, the DC positive electrode Vin disposed on the upper surface of the power semiconductor component 10 can be electrically connected to the DC positive electrode disposed on the lower surface of the upper switch chip 112QH through a conductive via (such as TSV technology) penetrating the wafer substrate 111.

[0093] The above-mentioned technical features can also be combined or substituted to increase the current density of power semiconductor components by more than 30%. Combined with the current density improvement provided by the module structure shown in this invention, the overall current density can be increased by more than 50%.

[0094] Figures 8A to 8I A schematic diagram of another type of monolithic double-sided electrode is shown. (e.g.) Figure 8A As shown, the DC negative electrode GND of the lower switching chip 112QL is directly electrically connected to the P+ buried layer and the P+ substrate 111P+. A P-epitaxial layer 116P is disposed between the P+ substrate 111P+ and the P+ buried layer. Because the buried layer is relatively thin, typically around a few micrometers, and each unit cell is directly led to the substrate through the buried layer, its area ratio is relatively high and its distribution is uniform, thus achieving a low on-resistance. On the other hand, because the DC negative electrode GND of the lower switching chip 112QL is directly led out from the lower surface of the power semiconductor component 10, the mutual cross-segmentation when multiple electrodes are led out on the same surface is reduced, simplifying the wiring layer of the switching electrode SW on the upper surface and making the interconnection wiring of the upper surface electrodes easier to implement; further reducing the on-resistance of the device; and because the complexity of electrode interconnection is reduced, the yield and product reliability are further improved. This embodiment shows only a single unit cell structure; in practical applications, multiple unit cell structures are arranged in parallel.

[0095] Figure 8B As shown Figure 8AThe difference shown is that a small amount of DC negative electrode GND is fanned out on the upper surface of the power semiconductor component 10. The area occupied by the DC negative electrode GND on the upper surface is less than half the area occupied by the switching electrode SW; in other embodiments, the DC negative electrode GND on the upper surface can be distributed and fanned out, which has a lower on-state impedance while reducing the inductance of the high-frequency loop.

[0096] Figure 8C As shown in another embodiment, the DC potential of the lower switch chip 112QL is directly electrically connected through the N+ buried layer and the N+ substrate 111N+. Because the N+ substrate 111N+ has a low resistivity, the on-resistance of the lower switch can be further reduced.

[0097] Figure 8D As shown in another embodiment, the source region of the lower switch chip 112QL is directly electrically connected to the N+ substrate 111N+ via a buried via / groove 117; the buried via / groove 117 can be a tungsten buried via / groove, a ruthenium buried via / groove, or a polysilicon buried via / groove; the buried via / groove 117 can serve both as an intra-layer interconnect and as a way to reduce the on-resistance of the lower switch. Other technical features of this embodiment are similar to those of the previous embodiment. Figure 8C As shown, both can yield the same technical benefits.

[0098] Figure 8D1 The following is another implementation method, which differs from... Figure 8D The source region of the lower switch chip 112QL is fanned out to the outside of the unit cell region through the wiring layer GND layout, and then directly electrically connected to the substrate through the buried via / groove 117 connected to the wiring layer GND layout.

[0099] Figure 8D2 The following is another implementation method, which differs from... Figure 8D1 A metal mating hole / slot 118 is provided on the lower side of the buried hole / slot 117 to further reduce the transmission impedance.

[0100] Figure 8D3 The following is another implementation method, which differs from... Figure 8D2 An N+ diffusion region 120 is formed on the N+ substrate. While setting the buried via / groove 117, a high-density deep trench 119 is simultaneously formed on the N+ diffusion region 120. A dielectric layer is formed by oxidation, and a conductive layer such as tungsten, ruthenium, or polysilicon is filled inside. This conductive layer is connected to the wiring layer of the DC positive electrode Vin, so that a capacitor is integrated close to the DC positive electrode Vin and the DC negative electrode GND.

[0101] Figure 8EAs shown in another embodiment, the source region of the lower switching chip 112QL is directly electrically connected to the N+ substrate 111N+ via buried vias / grooves 117. Multiple buried vias / grooves 117 can be provided in the source region of a unit cell. One buried via / groove 117 is electrically connected to the N+ substrate 111N+, and another buried via / groove 117 is connected to the P+ region. The conductivity of the buried via / groove 117 connected to the P+ region can be electrically connected to the N+ region of the unit cell through the wiring layer GND-Layout on the upper surface of the unit cell. These buried vias / grooves 117 can be tungsten buried vias / grooves, ruthenium buried vias / grooves, or polysilicon buried vias / grooves. This embodiment further reduces the on-resistance of the lower switching transistor by providing multiple buried vias / grooves.

[0102] Figure 8F As shown in another embodiment, the N+ connection path between the source region of the lower switch chip 112QL and the N+ substrate 111N+ is achieved through multiple epitaxy and multiple implantation. This N+ connection path has the characteristics of high density and low impedance, achieving a low impedance connection without affecting the cell density, thereby effectively reducing the on-resistance of the lower transistor.

[0103] Figure 8G As shown in another embodiment, the N+ connection path between the source region of the lower switch chip 112QL and the N+ substrate 111N+ can be realized through multiple epitaxy and multiple implantation. The N+ connection path has the characteristics of high density and low impedance. At the same time, the N+ connection path can be extended to the P+ region, thereby reducing the process difficulty of power semiconductor components and reducing the on-resistance of the lower switch.

[0104] Figure 8H Another embodiment is shown, in which an N+ layer is implanted below the source region of the lower switch wafer 112QL through one or more epitaxial growths; and the source region of the lower switch wafer 112QL is directly connected to the implanted N+ layer through multiple buried vias / grooves 117. This approach can increase the area of ​​the implanted N+ layer and reduce the depth of the buried vias / grooves 117, thereby further reducing the manufacturing difficulty of the power semiconductor device and reducing the on-resistance of the lower switch.

[0105] Figure 8I In another implementation, with Figure 8H The difference in the illustrated embodiment is that only an N+ layer is formed in the source region of the lower switch chip 112QL, and no P+ layer is formed. In this case, the conductive path of the parasitic diode between the source and drain regions of the lower switch chip 112QL is directly connected to the P- region through the buried via / groove 117, forming a conduction loop. Reducing the P+ layer not only lowers the production cost, but also further increases the cell density of the lower switch chip 112QL and reduces the on-resistance of the lower switch.

[0106] Figures 8A to 8IThe embodiments shown only illustrate the differences between the different implementations; all others can employ the same technical features and obtain the same technical benefits. The buried vias / trenches 117 in these embodiments can be tungsten buried vias / trenches, ruthenium buried vias / trenches, or polysilicon buried vias / trenches.

[0107] Figures 9A to 9E A side cross-sectional schematic diagram of a converter using the aforementioned power semiconductor component 10 is shown. (See attached diagram.) Figure 9A As shown, two power semiconductor components 10 are disposed on the upper surface of the first carrier plate 301. The power semiconductor components 10 are electrically connected to the first carrier plate 301 via an electrode assembly 105a and a GND conductive strip 105b. The electrode assembly 105a includes a DC positive electrode Vin, a switching electrode SW, and / or a DC negative electrode GND. A capacitor C is disposed on the upper surface and / or the lower surface of the first carrier plate 301. The positive and negative terminals of the capacitor C are electrically connected to the DC positive electrode Vin and the DC negative electrode GND of the power semiconductor components 10 via the first carrier plate 301. The converter also includes a second carrier plate 302, and a magnetic component Mag is disposed between the lower surface of the first carrier plate 301 and the upper surface of the second carrier plate 302. The first and second ends of the winding 31 of the magnetic component Mag are fixed to and electrically connected to the first carrier plate 301 and the second carrier plate 302, respectively. The converter also includes an input positive / negative electrical connector 32 and a signal electrical connector 303. The input positive / negative electrical connector 32 can be a metal post, with its first and second ends fixed and electrically connected to the first carrier plate 301 and the second carrier plate 302, respectively, for power transmission. The signal electrical connector 303 can be a third carrier plate, with its first and second ends fixed and electrically connected to the first carrier plate 301 and the second carrier plate 302, respectively, for transmitting control and / or sampling signals of the converter. In this embodiment, the winding 31 and the first end of the electrical connector protrude from the magnetic core, and the capacitor C is disposed within the space formed by the protrusion, the magnetic core, and the first carrier plate 301. The power semiconductor assembly 10 can be as follows: Figure 9A As shown, it is directly disposed on the upper surface of the first carrier plate 301; or it can be disposed as follows: Figure 9A1 As shown, it is first placed on a semiconductor carrier 106, then encapsulated into a single unit using molding compound 107, and then assembled with magnetic components such as Mag. This effectively prevents device displacement or falling off during assembly, improving the yield and reliability of the converter. On the other hand, as Figure 9A2 As shown, the power semiconductor component 10 can be embedded within the semiconductor carrier 106, and is fixed and electrically connected to the outside through the internal wiring and vias of the semiconductor carrier 106. The lower surface of the second carrier 302 is provided with the pins of the converter, which are fixed and electrically connected to the external components.

[0108] Figure 9BAnother structural layout of the converter is shown, with the magnetic component Mag disposed on the upper surface of the first carrier plate 301. The power semiconductor component 10 is disposed on the lower surface of the first carrier plate 301; the lower surface of the first carrier plate 301 and the power semiconductor component 10 are encapsulated, with the DC negative terminal of the power semiconductor component 10 exposed outside the encapsulation, directly fixed and electrically connected to external components; the input positive terminal Vin and output positive terminal Vo of the converter are fixed and electrically connected to external components via pre-placed conductive posts. A capacitor C is disposed on the upper surface of the first carrier plate 301, within the space formed by the winding / electrical connector, the magnetic core, and the first carrier plate, and is vertically positioned corresponding to the power semiconductor component 10, thereby reducing the parasitic inductance of the input circuit. Furthermore, this converter architecture enables bi-directional heat dissipation; the power semiconductor component 10 dissipates heat through external components (such as the motherboard), and the heat generated by the magnetic component can also be dissipated upwards via the windings in the magnetic component.

[0109] Figure 9C In the converter structure shown, the power semiconductor component 10 is embedded within the first carrier plate 301, and the magnetic component Mag and capacitor C are disposed on the upper surface of the first carrier plate 301, thus achieving the same result. Figure 9B The illustrated structure offers technical advantages such as double-sided heat dissipation and reduced parasitic inductance in the input loop. Furthermore, the embedded structure allows for a smaller loop inductance through internal wiring stack-up design, and the thinner substrate (typically less than 0.7mm) further facilitates reduction of parasitic inductance.

[0110] Figure 9D In the converter structure shown, capacitor C and power semiconductor component 10 are disposed together on the lower surface of the first carrier plate 301, and magnetic component Mag is disposed on the upper surface of the first carrier plate 301, thereby reducing the height of the magnetic component and thus reducing the overall height of the converter. The structure shown in this embodiment also achieves the benefits of double-sided heat dissipation and reduced parasitic inductance of the circuit.

[0111] Figure 9E In the converter structure shown, the power semiconductor component 10 is embedded within the first carrier plate 301; the capacitor C also adopts an embedded package, horizontally embedded within the capacitor carrier plate 304, with the plane of the internal electrode of the capacitor parallel to the plane of the paper. Besides high-frequency current, DC current also flows through the internal electrode. In this structure, the magnetic component Mag is disposed on the upper surface of the first carrier plate 301, and the capacitor carrier plate 304 is disposed on the lower surface of the first carrier plate 301. These capacitors C can be either input capacitors Cin or output capacitors Co. The positions of the input capacitor Cin, the output capacitor Co, the positive input terminal, the positive output terminal, and the negative input terminal of the converter can be flexibly set through the internal wiring layer of the carrier plate. The heat generated by the converter can also be dissipated upwards through the windings and downwards through the main board.

[0112] This invention also illustrates the implementation methods of the power and signal terminals of the converter, such as... Figure 9F1 and Figure 9F2 As shown. Figure 9F1 As shown, after the lower surface of the first molding substrate 301 and the power semiconductor assembly 10, a window is made in the molding compound 107, and solder balls are then inserted into the window for signal and power terminals to be brought out. Figure 9F2 Another implementation shown involves opening a window in the molding compound 107 and then bringing out the power and signal terminals through a metallized window. Both implementations can be applied to the aforementioned converter structure and achieve the same benefits.

[0113] This invention also optimizes the thermal conductivity of capacitor C from top to bottom. Figure 10A This is a side cross-sectional view of the internal structure of a traditional capacitor. The two electrodes of capacitor C are made of metal sheets, and in the vertical direction, multiple layers of metal sheets and multiple layers of ceramic are stacked sequentially. In the vertical direction, heat is transferred upwards through the multiple layers of spaced-apart metal and ceramic layers. Assuming the metal layers are made of copper, whose thermal conductivity is approximately 400 W / m•K, and the thermal conductivity of ceramic is approximately 20 W / m•K, and assuming that metal and ceramic each account for 50% of the total volume, then the equivalent thermal resistance from bottom to top is approximately 10 W / m•K. Therefore, there is room for optimization in the thermal conductivity of capacitor C in the vertical direction.

[0114] Figure 10B This is a side sectional view of the internal structure of the novel capacitor. The two electrodes of the capacitor are also made of metal sheets, but these sheets are mounted vertically, and the capacitor is composed of multiple layers of metal and ceramic stacked from front to back. In this structure, heat can be transferred directly along the metal layers from bottom to top. Assuming the metal layer is copper, its thermal conductivity is approximately 400 W / m•K, while the thermal conductivity of ceramic is around 20 W / m•K. Assuming that metal and ceramic each account for 50% of the total volume, the equivalent thermal resistance from bottom to top is approximately 200 W / m•K, increasing the capacitor's thermal conductivity by nearly 20 times.

[0115] The converter designs described above all include multiple ceramic capacitors. However, the effective space occupied by these capacitors is relatively small, perhaps only around 50% of the total capacitor layer space, resulting in significant wasted space across the converter's cross-section. This invention proposes a novel converter structure using stacked silicon capacitors, detailed as follows... Figures 11A to 11C As shown. Figure 11AThe diagram shows two layers of silicon capacitors stacked on the upper surface of a power semiconductor component 10. Electrodes are led out from both the upper and lower surfaces of the power semiconductor component 10, with a DC positive electrode Vin and a DC negative electrode GND led out from the upper surface. These two DC electrodes are electrically connected to the two ends of the capacitor C. Each layer of silicon capacitors then leads its positive and negative electrodes from the lower surface to the upper surface, electrically connecting to the two ends of the silicon capacitor above it. These electrical connections can be implemented using connectors 312, such as metal layers or other conductive materials. Finally, external pins are led out from the upper surface of the capacitor & semiconductor combination as external connections for the combination. If a larger capacitance is required, the number of silicon capacitor stacked layers can be increased. The capacitor layer includes a capacitor functional region 311. In this embodiment, the thickness of the functional layers of both the power semiconductor component and the silicon capacitors is very thin, so the overall thickness of the combination is only determined by the process capability and can be thinner than 100µm or even 50µm. With an overall thickness in the range of 200~300um, it is possible to integrate almost all Vbus capacitors (i.e. DC-side capacitors) and power semiconductor components, further improving the current density and power density of the combination.

[0116] Figure 11B In the embodiment shown, the electrodes of the capacitor & semiconductor combination are guided to the required interface (such as the electrical connection surface) as electrical connectors by means of processes such as welding copper sheets or embedding, forming an IPM unit (Intelligent Power Module).

[0117] Figure 11C The diagram shows a side cross-section of the converter, where the IPM unit and magnetic components are stacked. Furthermore, an output capacitor combination 313 can be stacked on the lower surface of the magnetic components. If the overall thickness requirement of the converter is 5mm, the aforementioned capacitor and semiconductor combination allows for an additional 3.5mm of thickness for the magnetic components. Therefore, it satisfies both ultra-thin converter applications and the demands for high conversion efficiency and high current density. Taking a practical design as an example, the converter dimensions are 6mm*6mm*5mm. Three layers of silicon capacitors are stacked on the power semiconductor components, enabling a two-phase buck module with currents up to 100 amps or even 150 amps. This module exceeds industry standards by more than 50% in both power density and current density. In the module dimensions shown in this embodiment, by utilizing stacking and an ultra-thin capacitor / semiconductor combination, as much thickness as possible is allocated to the magnetic components, allowing the module's operating frequency to be in the 1MHz~2MHz range, thereby reducing switching losses in the semiconductor devices.

[0118] In applications with higher operating frequencies, such as those in the range of 10MHz to 30MHz, Figures 12A to 12CAnother embodiment is shown. Due to the increased operating frequency, the thickness of the magnetic component can be further reduced, and even a semiconductor can be used as a substrate. Details are as follows... Figure 12A As shown, the top surface of the power semiconductor component 10 has a stacked input capacitor (also known as a bridge arm decoupling capacitor) C; the bottom surface of the power semiconductor component 10 has a magnetic component, in this embodiment, the magnetic component Mag is a silicon inductor L; the bottom surface of the silicon inductor L has a capacitor layer, which is the output capacitor Co (also known as a filter capacitor). In this embodiment, most or even all devices are manufactured using wafer technology, which is not limited to silicon materials, thus allowing for a further reduction in the overall thickness of the module. In this embodiment, except for the magnetic component, whose height needs to be adjusted according to actual requirements, the thickness of the capacitor layer and the power semiconductor component is basically determined by structural strength, so the module thickness can be less than 300µm, or even as small as 200µm. To maximize the thickness of the magnetic component within the limited module thickness, thereby improving module efficiency, the overall thickness of the module can be further reduced by directly generating the magnetic component on the wafer, eliminating the substrate of the traditional silicon inductor.

[0119] Figure 12B In the schematic diagram shown, anti-coupling of two or more inductors is achieved through wafer inductor technology; other technical features are similar to... Figure 12A The same applies as shown; by incorporating ultra-thin anti-coupling inductor components, the dynamic characteristics of the ultra-thin module can be further improved. Additionally, the power semiconductor components can also be configured with phase and phase matching. Figure 12C The image shows a high-capacitance module application, achieved through... Figure 12A and Figure 12B The top and bottom surfaces of the module shown are further stacked with capacitor layers to increase the capacitance value. Since the thickness of the capacitor layer is negligible relative to the thickness of the magnetic components, the thickness of the module changes very little even if the number of capacitor layers increases.

[0120] Figures 13A to 13C The ultra-thin module shown can be more flexibly applied to different systems. For example... Figure 13A As shown, the output surface OUT of the power supply module PSU is directly fixed and electrically connected to the computing chip XPU, and the output surface OUT is flush with the bottom of the signal pins S1~Sn; a connection part (such as...) is provided on the input surface IN of the power supply module PSU. Figure 12AThe connection portions GND and VIN are flush with the tops of the signal pins S1 to Sn. Directly mounting the power supply module (PSU) onto the computing power chip XPU minimizes the current path between the XPU and the PSU, reducing transmission path losses and improving the power supply module's fast response capability; thus enhancing system conversion efficiency and XPU computing speed.

[0121] Figure 13B Another application example is shown, where the power supply module (PSU) is embedded within the module carrier board 305 or within the system motherboard. The output side (OUT) of the power supply module (PSU) is connected to a connection point located on the bottom surface of the module carrier board 305 via vias and wiring layers to power the computing power chip (XPU) (i.e., the load). The input side (IN) of the power supply module (PSU) is connected to a connection point located on the top surface of the module carrier board 305 via vias and / or wiring layers to receive input power and / or control signals, etc. Furthermore, Figure 13C Another application example is shown. Due to the high operating frequency of the power supply unit (PSU), the requirements for the frequency and accuracy of the control signal also increase. In this embodiment, the control chip CTL is integrated into the computing power unit (XPU) using the same semiconductor process (e.g., 3nm process), making the size of the control chip CTL negligible. Furthermore, the close proximity of the computing power unit (XPU) and the power supply unit (PSU) also reduces distortion in the signal transmission path, ensuring the accuracy of the control signal and meeting the PSU's speed requirements. Moreover, the CTL's integration into the XPU allows for information transmission beyond just PWM control signals. It can also anticipate load demands, sample and monitor the power supply unit's operating status, and perform pre-adjustment loop control, ensuring the power supply unit's response speed and reliable operation.

[0122] Figure 14A In another embodiment of the power semiconductor component, the upper switch QH adopts a vertical MOSFET and the lower switch QL adopts a planar MOSFET. In this case, the drain of the upper switch QH, i.e. the DC positive terminal Vin, can be directly fanned out through the N+ substrate. It does not need to be conducted from the front to the back through vias or other means, as is the case with planar MOSFETs, which further reduces the conduction impedance and processing cost.

[0123] Figure 14B In another implementation method, relative Figure 14A On a vertical switch QH, a Vin' electrode is led out from the N-region, and a high-frequency capacitor can be placed close to GND on the same side. Of course, Vin' can be fanned out directly from the N-region, or it can be guided to the desired location through a wiring layer and then fanned out.

[0124] Figure 14C In another implementation method, relative Figure 14A The upper switch QH uses a horizontal MOSFET, and the lower switch QL uses a vertical MOSFET. At this time, the drain of the lower switch QL, i.e. the switching potential, can be directly fanned out through the N+ substrate. The switching potential of the upper switch is led out of the upper switch QH functional area through the inner bus layer and then connected to the switching electrode SW on the back side through the through-silicon via 121. Alternatively, it can be connected to the N+ substrate through a buried via.

[0125] Figures 11A to 11C The system shown is not limited to a single power module; multiple power modules can be connected in parallel to power the computing chip. Its control chip can be... Figure 11C The integrated structure shown is used to sample, control, or monitor the operation of the multiple power modules.

[0126] The switching transistor disclosed in this invention can be a Si MOSFET, SiC MOSFET, GaN device, or IGBT, etc., all of which can realize the switching function disclosed in this invention.

[0127] The power module described in the above embodiments can also be part of an electronic device, as long as it meets the technical features and benefits disclosed in this invention.

[0128] The terms "equal to," "identical to," or "equal to" disclosed in this invention must take into account the parameter distribution of the engineering process, with an error distribution within ±30%. "Parallel" is defined as the angle between two line segments or lines being less than or equal to 45 degrees. "Perpendicular" is defined as the angle between two line segments or lines being within the range of [60, 120] degrees. The definition of "phase misalignment" also needs to consider the parameter distribution of the engineering process, with an error distribution of the phase misalignment degree within ±30%.

[0129] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0130] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power electronic component, characterized in that, include: Power semiconductor components; The power semiconductor component includes a bridge arm unit, a DC positive electrode, a DC negative electrode, and a switching electrode; the bridge arm unit includes an upper switch and a lower switch; the upper switch is electrically connected to the DC positive electrode and the switching electrode, and the lower switch is electrically connected to the DC negative electrode and the switching electrode; The power semiconductor component includes a top surface and a bottom surface opposite to each other, and the DC positive electrode and the DC negative electrode are respectively disposed on the top surface and / or the bottom surface of the power semiconductor component; the switching electrode is disposed on the bottom surface of the power semiconductor component; capacitance, The capacitor is disposed on the top surface of the power semiconductor component, the positive terminal of the capacitor is electrically connected to the DC positive terminal, and the negative terminal of the capacitor is electrically connected to the DC negative terminal; Chips, The wafer is used to set the bridge arm unit; a large-area thermal interface is provided on the upper surface of the wafer, and the area of ​​the large-area thermal interface is greater than or equal to 50% of the cross-sectional area of ​​the wafer; the large-area thermal interface is thermally connected to the capacitor.

2. The power electronic component according to claim 1, characterized in that, Both the DC positive and DC negative electrodes are located on the top surface of the power semiconductor component; the large-area thermal interface is electrically connected to the DC negative electrode.

3. The power electronic component according to claim 1, characterized in that, The DC negative electrode is disposed on the top surface of the power semiconductor component, and the DC positive electrode is disposed on the bottom surface of the power semiconductor component; the DC positive electrode is electrically connected to the positive electrode of the capacitor through a vertical channel; the large-area thermal interface is electrically connected to the DC negative electrode.

4. The power electronic component according to claim 1, characterized in that, The chip is thermally connected to a capacitor through multiple small units.

5. The power electronic component according to claim 4, characterized in that, It also includes a large-area temperature equalization layer, which is disposed between the wafer and the multiple small cells.

6. The power electronic component according to claim 1, characterized in that, The number of capacitor electrodes located on the top surface of the power semiconductor component having the same polarity as the electrodes disposed on the top surface of the power semiconductor component is greater than the number of capacitor electrodes having different polarities from the electrodes disposed on the top surface of the power semiconductor component.

7. The power electronic component according to claim 1, characterized in that, A capacitor layer is disposed on the top surface of the power semiconductor component, the capacitor layer includes capacitors, and a thermally conductive insulating material is disposed between the capacitors.

8. The power electronic component according to claim 1, characterized in that, The capacitor is a ceramic capacitor, which includes multiple layers of metal sheets and multiple layers of ceramic sheets, with the metal sheets arranged perpendicularly to the top surface of the power semiconductor component.

9. The power electronic component according to claim 1, characterized in that, The wafer includes a substrate and a wafer functional area, wherein the upper switch and the lower switch are disposed in the wafer functional area.

10. The power electronic component according to claim 9, characterized in that, The substrate is stacked on the upper surface of the wafer functional area; the substrate is at the same potential as the DC negative electrode; the upper surface of the substrate is provided with a DC negative electrode and / or a DC positive electrode, and the lower surface of the wafer functional area is provided with a switching electrode.

11. The power electronic component according to claim 10, characterized in that, The lower surface of the functional area of ​​the wafer is also provided with a DC positive electrode and / or a DC negative electrode.

12. The power electronic component according to claim 9, characterized in that, The wafer functional area is stacked on the upper surface of the substrate; the substrate and the switching electrode are at the same potential; the upper surface of the wafer functional area is provided with a DC negative electrode and a DC positive electrode, and the lower surface of the substrate is provided with a switching electrode.

13. The power electronic component according to claim 1, characterized in that, The chip includes an upper switch chip and a lower switch chip, with the lower switch chip located above the upper switch chip. The upper surface of the lower switch chip is provided with a DC negative electrode, and the lower surface of the upper switch chip is provided with a DC positive electrode. A switching metal layer is provided between the lower switch chip and the upper switch chip, and a switching electrode is provided at least one end of the switching metal layer. The lower switch chip is electrically connected to both the DC negative electrode and the switching electrode, and the upper switch chip is electrically connected to both the DC positive electrode and the switching electrode.

14. The power electronic component according to claim 1, characterized in that, The wafer includes an upper switch wafer and a lower switch wafer, with the lower switch wafer located above the upper switch wafer. A DC positive electrode and a DC negative electrode are disposed on the top surface of the power semiconductor component, and a DC negative electrode and a switching electrode are disposed on the lower surface of the power semiconductor component. The lower switch wafer includes a DC negative potential and a switching potential, and the upper switch wafer includes a DC positive potential and a switching potential. The DC negative potential of the lower switch wafer is led out through a metal layer and / or a vertical channel to the top and bottom surfaces of the power semiconductor component and electrically connected to the DC negative electrode. The DC positive potential of the upper switch wafer is led out through a metal layer and / or a vertical channel to the top surface of the power semiconductor component and electrically connected to the DC positive electrode. The switching potentials of the upper and lower switch wafers are led out through a switching metal layer to the bottom surface of the power semiconductor component and electrically connected to the switching electrode.

15. The power electronic component according to claim 1, characterized in that, The chip includes an upper switch chip and a lower switch chip, which are arranged horizontally. The upper surface of the upper switch chip is electrically connected to a DC positive electrode, the upper surface of the lower switch chip is electrically connected to a DC negative electrode, and the lower surfaces of the upper and lower switch chips are electrically connected to a switching electrode.

16. The power electronic component according to claim 1, characterized in that, The DC positive and DC negative terminals are disposed on the top surface of the power semiconductor component, and the switching electrode is disposed on the bottom surface of the power semiconductor component; the capacitors are arranged horizontally to form a capacitor layer, and at least two capacitor layers are stacked on the top surface of the power semiconductor component; the positive and negative terminals of the capacitors respectively lead the DC positive and DC negative terminals of the top surface of the power semiconductor component from the lower surface of the capacitor to the upper surface of the capacitor, the positive and negative terminals of the lower layer capacitors correspond one-to-one with the positive and negative terminals of the upper layer capacitors and are electrically connected, and the positive and negative terminals of the uppermost layer capacitors and the switching electrode located on the bottom surface of the power semiconductor component are the external connection pins of the power electronic component.

17. The power electronic component according to claim 16, characterized in that, An electrical connector is provided on the outside of the external connection pin, and the external connection pin is led out to the electrical connection surface through the electrical connector. The power electronic component is electrically connected to the external component through the electrical connection surface.

18. The power electronic component according to claim 17, characterized in that, The connector is a metal sheet, which is made by welding or embedding.

19. The power electronic component according to claim 17, characterized in that, The capacitor is a silicon capacitor.

20. A high current density converter, characterized in that, It includes a magnetic component and a power electronic component as described in claim 1; the magnetic component is disposed on the lower surface of the power semiconductor component; the capacitor in the power electronic component is the high-voltage side capacitor of the high current density converter.

21. The high current density converter as described in claim 20, characterized in that, The magnetic component is a silicon wafer inductor; the high-voltage side capacitor is a silicon capacitor.

22. The high current density converter as described in claim 20, characterized in that, The silicon wafer inductor consists of two oppositely coupled inductors.

23. The high current density converter as described in claim 21, characterized in that, A low-voltage side capacitor layer is stacked on the lower surface of the silicon wafer inductor, and a low-voltage side capacitor is disposed in the low-voltage side capacitor layer. The low-voltage side capacitor is a silicon capacitor.

24. The high current density converter as described in claim 23, characterized in that, The upper surface of the high current density converter is the input surface, and an input connection portion is provided on the input surface; the high voltage side capacitor layer is disposed adjacent to the input surface; the lower surface of the high current density converter is the output surface, and an output connection portion is provided on the output surface; the low voltage side capacitor layer is disposed adjacent to the output surface; the output surface is electrically connected to the upper surface of the load; the projections of the high current density converter and the load on the same horizontal plane at least partially overlap.

25. The high current density converter as described in claim 24, characterized in that, The upper surface of the load is provided with signal pins; the lower surface of the output connection is flush with the bottom end of the signal pins, and the upper surface of the input connection is flush with the top end of the signal pins.

26. The high current density converter as described in claim 24, characterized in that, The high current density converter has a frequency higher than 10MHz.

27. The high current density converter as described in claim 21, characterized in that, It also includes a module carrier board, the upper surface of which is provided with an input connection portion, and the lower surface of which is provided with an output connection portion; the high current density converter is embedded in the module carrier board; the upper surface of the high current density converter is the input surface, which is electrically connected to the input connection portion through the module carrier board; the lower surface of the high current density converter is the output surface, which is electrically connected to the output connection portion through the module carrier board; the module carrier board is electrically connected to the load through the output connection portion and supplies power to the load.

28. The high current density converter as described in claim 23, characterized in that, The lower surface of the high current density converter is fixed to and electrically connected to the load. A control chip is integrated on the load and is disposed adjacent to the high current density converter. The control chip is used to transmit information between the high current density converter and the load.

29. An intelligent computing chip system, characterized in that, The device includes a high current density converter and a load chip as described in claim 20, wherein the high current density converter and the load chip are stacked vertically, and the projections of the high current density converter and the load chip in the vertical direction at least partially overlap. The high current density converter includes an output capacitor layer, an inductor layer, a power semiconductor wafer layer, an input capacitor layer, and a converter input layer, wherein the load chip, output capacitor layer, inductor layer, power semiconductor wafer layer, input capacitor layer, and converter input layer are arranged sequentially in the vertical direction; the frequency of the high current density converter is higher than 10MHz.

30. The intelligent computing chip system according to claim 29, wherein the input capacitor layer and the output capacitor layer are both silicon capacitor layers, and the inductor layer is a silicon wafer inductor.

31. A power semiconductor component, characterized in that, include: Chips, The wafer includes a substrate, an upper switching wafer region, and a lower switching wafer region. The upper switching wafer region and the lower switching wafer region are horizontally distributed, and the substrate is located above the upper switching wafer region and the lower switching wafer region. The upper switching wafer region includes a DC potential and a switching potential, and the lower switching wafer region includes a DC potential and a switching potential. Two electrode layers, namely an upper electrode layer disposed on the upper surface of the power semiconductor component and a lower electrode layer disposed on the lower surface of the power semiconductor component; An isolation layer that isolates the upper switch wafer region and the lower switch wafer region; An inner bus layer is used to lead the DC potential and switching potential of the wafer to the electrode layer. It also includes a DC positive electrode, a DC negative electrode, and a switching electrode, which are located in the electrode layer. The DC potential of the upper switching chip is led out to the DC positive electrode, the DC potential of the lower switching chip region is led out to the DC negative electrode, and the switching potential is led out to the switching electrode.

32. The power semiconductor component according to claim 31, characterized in that, The isolation layer is "n" shaped, with the upper switch wafer area located inside the isolation layer and the lower switch wafer area located outside the isolation layer.

33. The power semiconductor component according to claim 31, characterized in that, The inner bus layer is located below the wafer; the upper electrode layer is provided with a DC negative electrode, the lower electrode layer is provided with a switching electrode, and the DC positive electrode is provided in the upper electrode layer and / or the lower electrode layer; the DC potential and switching potential of the upper switching wafer region are led out to the inner bus layer through vias, and then led out to the DC positive electrode and the switching electrode through vias and / or conductive vias, respectively; the switching potential of the lower switching wafer region is led out to the inner bus layer through vias, and then led out to the switching electrode through vias; the DC potential of the lower switching wafer region is led out to the DC negative electrode through the substrate.

34. The power semiconductor component according to claim 33, characterized in that, The DC potential of the lower switch wafer region is led out to the DC negative electrode through a via provided above the substrate, or led out to the inner bus layer through a via and then led out to the DC negative electrode through a conductive via.

35. The power semiconductor component according to claim 31, characterized in that, The lower switching chip region includes a source region and a drain region. The source region includes an N+ buried layer, a P+ buried layer, and a P- buried layer. The source region is electrically connected to the DC negative electrode, and the drain region is electrically connected to the switching electrode.

36. The power semiconductor component according to claim 35, characterized in that, The substrate is a P+ substrate, the P+ buried layer is electrically connected to the DC negative electrode through the P+ substrate, the upper electrode layer is provided with a DC negative electrode, and the lower electrode layer is provided with a switching electrode and a DC positive electrode.

37. The power semiconductor component according to claim 36, characterized in that, A P epitaxial layer is further disposed between the P+ buried layer and the P+ substrate, and the P+ buried layer is electrically connected to the DC negative electrode through the P epitaxial layer and the P+ substrate.

38. The power semiconductor component according to claim 36, characterized in that, The lower electrode layer is provided with a DC negative electrode, and the area of ​​the DC negative electrode provided in the lower electrode layer is less than half the area of ​​the switching electrode; a GND wiring layer is provided on the lower surface of the source region, and the GND wiring layer is electrically connected to the DC negative electrode of the lower electrode layer through the inner bus layer.

39. The power semiconductor component according to claim 35, characterized in that, The substrate is an N+ substrate, and the N+ buried layer is electrically connected to the DC negative electrode through the N+ substrate; the upper electrode layer is provided with a DC negative electrode, and the lower electrode layer is provided with a switching electrode and a DC positive electrode.

40. The power semiconductor component according to claim 39, characterized in that, A buried via / groove is provided between the source region and the N+ substrate, and the source region is electrically connected to the N+ substrate through the buried via / groove.

41. The power semiconductor component according to claim 39, characterized in that, A GND wiring layer is provided on the surface of the source region. The GND wiring layer extends to the outside of the projection area of ​​the source region on the upper surface of the wafer. The GND wiring layer outside the projection area is electrically connected to the N+ substrate through vias / grooves.

42. The power semiconductor component according to claim 41, characterized in that, A docking hole / groove is provided on the N+ substrate, and the docking hole / groove is electrically connected to the via / groove and the DC negative electrode, respectively.

43. The power semiconductor component according to claim 39, characterized in that, The N+ substrate includes an N+ substrate diffusion region, which extends from the upper surface of the N+ substrate to the upper surface of the wafer and is located adjacent to the upper switch wafer region; a bridge arm capacitor is integrated on the N+ substrate diffusion region, and the bridge arm capacitor is electrically connected to the DC positive terminal and the DC negative terminal nearby.

44. The power semiconductor component according to claim 43, characterized in that, The bridge arm capacitor includes a high-density deep trench, the surface of which is provided with a dielectric layer, and the interior of which is filled with tungsten, ruthenium, or polycrystalline silicon.

45. The power semiconductor component according to claim 39, characterized in that, Multiple buried vias / grooves are disposed between the source region and the substrate, and a GND wiring layer is disposed on the lower surface of the source region; at least one buried via / groove is electrically connected to the N+ substrate and the N+ buried layer, and at least another buried via / groove is electrically connected to the P+ buried layer. The buried via / groove electrically connected to the P+ buried layer is electrically connected to the N+ buried layer through the GND wiring layer.

46. ​​The power semiconductor component according to claim 39, characterized in that, An N+ electrical connection path is provided between the source region and the N+ substrate, and the N+ electrical connection path is realized through multiple epitaxy and multiple implantation.

47. The power semiconductor component according to claim 46, characterized in that, The N+ electrical connection path extends to the P+ buried layer and is electrically connected to the P+ buried layer.

48. The power semiconductor component according to claim 39, characterized in that, An N+ electrical connection path is provided between the source region and the N+ substrate. The N+ electrical connection path includes an implanted N+ layer and a buried via / trench. The source region is electrically connected to the N+ substrate in sequence through the buried via / trench and the implanted N+ layer.

49. The power semiconductor component according to claim 35, characterized in that, The substrate is an N+ substrate. The upper electrode layer has a DC positive electrode, and the lower electrode layer has a switching electrode and a DC negative electrode. The upper switch wafer region has a vertical upper switch. The upper surface of the vertical upper switch includes a drain region, and the lower surface of the vertical upper switch includes a source region and a gate region. The drain region of the vertical upper switch is electrically connected to the DC positive electrode of the upper electrode layer through the N+ substrate. The source region of the vertical upper switch is electrically connected to the switching electrode through the inner bus layer.

50. The power semiconductor component according to claim 49, characterized in that, The lower electrode layer is also provided with a DC positive electrode. The area of ​​the DC positive electrode of the lower electrode layer is less than 50% of the area of ​​the switching electrode. A high-frequency capacitor is provided between the DC positive electrode and the DC negative electrode of the lower electrode layer.

51. The power semiconductor component according to claim 35, characterized in that, The substrate is an N+ substrate. Both the upper and lower electrode layers are provided with switching electrodes. The lower electrode layer is also provided with a DC positive electrode and a DC negative electrode. The upper switch wafer region is provided with a planar upper switch, and the lower switch wafer region is provided with a vertical lower switch. The upper surface of the vertical lower switch includes a drain region, and the lower surface of the vertical lower switch includes a source region and a gate region. The drain region of the vertical lower switch is electrically connected to the switching electrode of the upper electrode layer through the N+ substrate, and the source region of the vertical lower switch is electrically connected to the DC negative electrode. The source, drain, and gate regions of the planar upper switch are all disposed on the lower surface of the upper switch wafer region. The drain region of the planar upper switch is electrically connected to the DC electrode through the inner bus layer. The source region of the planar upper switch is electrically connected to the switching electrode located on the lower electrode layer through the inner bus layer. The switching electrode located on the lower electrode layer is electrically connected to the switching electrode located on the upper electrode layer through through-silicon vias or buried vias / grooves.

52. The power semiconductor component according to claim 31, characterized in that, The lower switching wafer region includes a source region and a drain region. The source region includes an N+ buried layer and a P- buried layer. A buried via / groove is provided between the source region and the substrate. One end of the buried via / groove is electrically connected to the N+ buried layer. A parasitic diode is included between the source region and the drain region, and the conductive path of the parasitic diode is formed by direct electrical connection between the buried via / groove and the P-buried layer.

53. A high current density converter, characterized in that, include: The power semiconductor component as described in claim 31, High-voltage end and low-voltage end; A magnetic component, comprising a magnetic core and a winding, wherein one end of the winding is electrically connected to the switching electrode and the other end of the winding is electrically connected to the high-voltage end or the low-voltage end; A capacitor is disposed adjacent to the power semiconductor component and is electrically connected to the DC positive and DC negative terminals.

54. The high current density converter as described in claim 53, characterized in that, It also includes a first carrier plate, which has an upper surface and a lower surface opposite to each other; the magnetic component is disposed on the upper surface of the first carrier plate, and both ends of the winding are fixed to the upper surface of the first carrier plate and electrically connected to the switching electrode and the high-voltage end or the low-voltage end through the first carrier plate.

55. The high current density converter as described in claim 54, characterized in that, The capacitor is disposed on the upper surface of the first carrier plate, and an accommodating space is formed between the magnetic core, the winding and the upper surface of the first carrier plate, and the capacitor is located within the accommodating space.

56. The high current density converter as described in claim 54, characterized in that, The power semiconductor component is disposed on the lower surface of the first carrier plate, and the top surface of the power semiconductor component is fixed and electrically connected to the lower surface of the first carrier plate; the power semiconductor component and the lower surface of the first carrier plate are encapsulated with molding compound to form a molded body, and the DC negative electrode is disposed on the bottom surface of the power semiconductor component and exposed outside the molded body.

57. The high current density converter as described in claim 56, characterized in that, The encapsulation body is provided with a carrier plate connection end, which is used to transmit signals and / or power.

58. The high current density converter as described in claim 57, characterized in that, The carrier plate connection end is a conductive post.

59. The high current density converter as described in claim 57, characterized in that, A window is provided on the lower surface of the encapsulation, and the carrier board connection end is formed by setting solder balls or metallized windows in the window.

60. The high current density converter as described in claim 56, characterized in that, The capacitor is disposed on the lower surface of the first carrier board and located within the plastic encapsulation.

61. The high current density converter as described in claim 54, characterized in that, The capacitor and power conductor assembly are embedded in the first carrier plate and are electrically connected to external components through the first carrier plate.

62. The high current density converter as described in claim 54, characterized in that, It also includes a capacitor carrier plate, in which the capacitor is embedded. The high current density converter is electrically connected to external components through the lower surface of the capacitor carrier plate, and the upper surface of the capacitor carrier plate is electrically connected to the power semiconductor component and / or the magnetic component and / or the lower surface of the first carrier plate.

63. The high current density converter as described in claim 53, characterized in that, | The DC negative electrode is disposed on the upper surface of the power semiconductor component; the DC positive electrode and the switching electrode are disposed on the lower surface of the power semiconductor component. It also includes a DC negative electrode conductive strip, through which the DC negative electrode of the power semiconductor component is electrically connected to the upper surface of the first carrier plate; the lower surface of the power semiconductor component is fixed and electrically connected to the upper surface of the first carrier plate; The magnetic component is disposed on the lower surface of the first carrier plate, and the capacitor is disposed on the upper and / or lower surface of the first carrier plate.

64. The high current density converter as described in claim 63, characterized in that, It also includes a semiconductor substrate, wherein the power semiconductor component is disposed on the semiconductor substrate and encapsulated as a single unit by molding compound or the power semiconductor component is embedded in the semiconductor substrate, and the power semiconductor component is assembled on the upper surface of the semiconductor substrate through the semiconductor substrate.

65. The high current density converter as described in claim 63, characterized in that, It also includes a power connector, a signal connector, and a second carrier board, wherein the two ends of the power connector, the signal connector, and the winding are electrically connected to the lower surface of the first carrier board and the upper surface of the second carrier board, respectively.

66. A high current density converter, characterized in that, include: High-voltage end and low-voltage end; A first carrier plate, the first carrier plate including opposing upper and lower surfaces; Power semiconductor components, The power semiconductor component includes opposing upper and lower surfaces, an electrode assembly, a DC negative electrode, a bridge arm unit, a wafer, and a bridge arm capacitor; the electrode assembly includes a DC positive electrode, a switching electrode, and / or a DC negative electrode; the bridge arm unit includes an upper switch and a lower switch; the upper switch and the lower switch are disposed on the wafer; the upper switch is electrically connected to the DC positive electrode and the switching electrode, and the lower switch is electrically connected to the DC negative electrode and the switching electrode; The bridge arm capacitor is disposed above the wafer, with its positive terminal electrically connected to the DC positive terminal and its negative terminal electrically connected to the DC negative terminal; the bridge arm capacitor absorbs at least 50% of the AC component in the bridge arm unit. A magnetic component, comprising a magnetic core and a winding, wherein one end of the winding is electrically connected to the switching electrode and the other end of the winding is electrically connected to the high-voltage end or the low-voltage end; A DC-side capacitor is disposed adjacent to the power semiconductor component and is electrically connected to the DC positive and DC negative terminals.

67. The high current density converter as described in claim 66, characterized in that, The magnetic component is disposed on the upper surface of the first carrier plate, and both ends of the winding are fixed to the upper surface of the first carrier plate and electrically connected to the switching electrode and the high-voltage end or the low-voltage end through the first carrier plate; the DC-side capacitor is disposed on the upper surface and / or the lower surface of the first carrier plate; the power semiconductor component is disposed on the lower surface of the first carrier plate.

68. The high current density converter as described in claim 67, characterized in that, It also includes a DC-side capacitor carrier plate, in which the DC-side capacitor is embedded. The high current density converter is electrically connected to external components through the lower surface of the DC-side capacitor carrier plate, and the upper surface of the DC-side capacitor carrier plate is electrically connected to the power semiconductor component and / or the magnetic component and / or the lower surface of the carrier plate.

69. The high current density converter as described in claim 66, characterized in that, The DC negative electrode is disposed on the upper surface of the power semiconductor component, and the electrode assembly is disposed on the lower surface of the power semiconductor component. It also includes a DC negative electrode conductive strip, through which the DC negative electrode of the power semiconductor component is electrically connected to the upper surface of the first carrier plate; the lower surface of the power semiconductor component is fixed and electrically connected to the upper surface of the first carrier plate; The magnetic component is disposed on the lower surface of the first carrier plate, and the DC-side capacitor is disposed on the upper and / or lower surface of the first carrier plate.

Images